- Timestamp:
- Jul 30, 2021 4:03:48 PM (4 years ago)
- Location:
- trunk/src/VBox
- Files:
-
- 9 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp
r90421 r90436 197 197 } while (0) 198 198 199 /** Acquires the PDM lock ( shouldn't really fail). */199 /** Acquires the PDM lock (can fail under extraordinary circumstance in in ring-0). */ 200 200 #ifdef IN_RING3 201 201 # define IOMMU_LOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED) … … 204 204 do { \ 205 205 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VINF_SUCCESS); \ 206 AssertRC(rcLock); \206 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV((a_pDevIns), NULL, rcLock); \ 207 207 } while (0) 208 208 #endif -
trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp
r90429 r90436 66 66 } while (0) 67 67 68 /** Acquires the DMAR lock ( not expected to fail). */68 /** Acquires the DMAR lock (can fail under extraordinary circumstance in in ring-0). */ 69 69 #ifdef IN_RING3 70 70 # define DMAR_LOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED) … … 73 73 do { \ 74 74 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VINF_SUCCESS); \ 75 AssertRC(rcLock); \75 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV((a_pDevIns), NULL, rcLock); \ 76 76 } while (0) 77 77 #endif -
trunk/src/VBox/Devices/Bus/DevPCI.cpp
r87789 r90436 819 819 { 820 820 PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT); 821 PCI_LOCK (pDevIns, VINF_IOM_R3_IOPORT_WRITE);821 PCI_LOCK_RET(pDevIns, VINF_IOM_R3_IOPORT_WRITE); 822 822 pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */ 823 823 PCI_UNLOCK(pDevIns); … … 839 839 { 840 840 PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT); 841 PCI_LOCK (pDevIns, VINF_IOM_R3_IOPORT_READ);841 PCI_LOCK_RET(pDevIns, VINF_IOM_R3_IOPORT_READ); 842 842 *pu32 = pThis->uConfigReg; 843 843 PCI_UNLOCK(pDevIns); … … 863 863 if (!(offPort % cb)) 864 864 { 865 PCI_LOCK (pDevIns, VINF_IOM_R3_IOPORT_WRITE);865 PCI_LOCK_RET(pDevIns, VINF_IOM_R3_IOPORT_WRITE); 866 866 rcStrict = pci_data_write(pDevIns, PDMINS_2_DATA(pDevIns, PDEVPCIROOT), offPort, u32, cb); 867 867 PCI_UNLOCK(pDevIns); … … 882 882 if (!(offPort % cb)) 883 883 { 884 PCI_LOCK (pDevIns, VINF_IOM_R3_IOPORT_READ);884 PCI_LOCK_RET(pDevIns, VINF_IOM_R3_IOPORT_READ); 885 885 VBOXSTRICTRC rcStrict = pci_data_read(PDMINS_2_DATA(pDevIns, PDEVPCIROOT), offPort, cb, pu32); 886 886 PCI_UNLOCK(pDevIns); -
trunk/src/VBox/Devices/Bus/DevPciIch9.cpp
r85912 r90436 282 282 u32 &= ~3; 283 283 284 PCI_LOCK (pDevIns, VINF_IOM_R3_IOPORT_WRITE);284 PCI_LOCK_RET(pDevIns, VINF_IOM_R3_IOPORT_WRITE); 285 285 pThis->uConfigReg = u32; 286 286 PCI_UNLOCK(pDevIns); … … 306 306 PDEVPCIROOT pThis = PDMINS_2_DATA(pDevIns, PDEVPCIROOT); 307 307 308 PCI_LOCK (pDevIns, VINF_IOM_R3_IOPORT_READ);308 PCI_LOCK_RET(pDevIns, VINF_IOM_R3_IOPORT_READ); 309 309 *pu32 = pThis->uConfigReg; 310 310 PCI_UNLOCK(pDevIns); … … 388 388 if (!(offPort % cb)) 389 389 { 390 PCI_LOCK (pDevIns, VINF_IOM_R3_IOPORT_WRITE);390 PCI_LOCK_RET(pDevIns, VINF_IOM_R3_IOPORT_WRITE); 391 391 392 392 if (pThis->uConfigReg & (1 << 31)) … … 486 486 *pu32 = 0xffffffff; 487 487 488 PCI_LOCK (pDevIns, VINF_IOM_R3_IOPORT_READ);488 PCI_LOCK_RET(pDevIns, VINF_IOM_R3_IOPORT_READ); 489 489 490 490 /* Configuration space mapping enabled? */ … … 678 678 679 679 /* Perform configuration space write */ 680 PCI_LOCK (pDevIns, VINF_IOM_R3_MMIO_WRITE);680 PCI_LOCK_RET(pDevIns, VINF_IOM_R3_MMIO_WRITE); 681 681 VBOXSTRICTRC rcStrict = ich9pciConfigWrite(pDevIns, pPciRoot, &aDest, u32, cb, VINF_IOM_R3_MMIO_WRITE); 682 682 PCI_UNLOCK(pDevIns); … … 702 702 /* Perform configuration space read */ 703 703 uint32_t u32Value = 0; 704 PCI_LOCK (pDevIns, VINF_IOM_R3_MMIO_READ);704 PCI_LOCK_RET(pDevIns, VINF_IOM_R3_MMIO_READ); 705 705 VBOXSTRICTRC rcStrict = ich9pciConfigRead(pPciRoot, &aDest, cb, &u32Value, VINF_IOM_R3_MMIO_READ); 706 706 PCI_UNLOCK(pDevIns); -
trunk/src/VBox/Devices/Bus/DevPciInternal.h
r82968 r90436 187 187 #define DEVPCIBUS_2_DEVPCIROOT(pPciBus) RT_FROM_MEMBER(pPciBus, DEVPCIROOT, PciBus) 188 188 189 /** @def PCI_LOCK 189 190 /** @def PCI_LOCK_RET 190 191 * Acquires the PDM lock. This is a NOP if locking is disabled. */ 192 #define PCI_LOCK_RET(pDevIns, rcBusy) \ 193 do { \ 194 int const rcLock = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rcBusy); \ 195 if (rcLock == VINF_SUCCESS) \ 196 { /* likely */ } \ 197 else \ 198 return rcLock; \ 199 } while (0) 191 200 /** @def PCI_UNLOCK 192 201 * Releases the PDM lock. This is a NOP if locking is disabled. */ 193 #define PCI_LOCK(pDevIns, rc) \194 do { \195 int rc2 = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \196 if (rc2 != VINF_SUCCESS) \197 return rc2; \198 } while (0)199 202 #define PCI_UNLOCK(pDevIns) \ 200 203 PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns) -
trunk/src/VBox/Devices/PC/DevIoApic.cpp
r90363 r90436 874 874 bool fRemoteIrrCleared = false; 875 875 int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS); 876 AssertRC(rc);876 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, NULL, rc); 877 877 878 878 for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++) … … 937 937 { 938 938 int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS); 939 AssertRC(rc);939 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, NULL, rc); 940 940 941 941 uint8_t const idxRte = iIrq; -
trunk/src/VBox/Devices/PC/DevPIC.cpp
r84334 r90436 58 58 * Defined Constants And Macros * 59 59 *********************************************************************************************************************************/ 60 /** @def PIC_LOCK 60 /** @def PIC_LOCK_RET 61 61 * Acquires the PDM lock. This is a NOP if locking is disabled. */ 62 #define PIC_LOCK_RET(a_pDevIns, a_pThisCC, rcBusy) \ 63 do { \ 64 int const rcLock = (a_pThisCC)->pPicHlp->pfnLock((a_pDevIns), rcBusy); \ 65 if (rcLock == VINF_SUCCESS) \ 66 { /* likely */ } \ 67 else \ 68 return rcLock; \ 69 } while (0) 62 70 /** @def PIC_UNLOCK 63 71 * Releases the PDM lock. This is a NOP if locking is disabled. */ 64 #define PIC_LOCK(a_pDevIns, a_pThisCC, rc) \65 do { \66 int rc2 = (a_pThisCC)->pPicHlp->pfnLock((a_pDevIns), rc); \67 if (rc2 != VINF_SUCCESS) \68 return rc2; \69 } while (0)70 72 #define PIC_UNLOCK(a_pDevIns, a_pThisCC) \ 71 73 (a_pThisCC)->pPicHlp->pfnUnlock((a_pDevIns)) … … 681 683 { 682 684 int rc; 683 PIC_LOCK (pDevIns, pThisCC, VINF_IOM_R3_IOPORT_READ);685 PIC_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_IOPORT_READ); 684 686 *pu32 = pic_ioport_read(pDevIns, pThis, pThisCC, &RT_SAFE_SUBSCRIPT(pThis->aPics, iPic), offPort, &rc); 685 687 PIC_UNLOCK(pDevIns, pThisCC); … … 704 706 { 705 707 VBOXSTRICTRC rc; 706 PIC_LOCK (pDevIns, pThisCC, VINF_IOM_R3_IOPORT_WRITE);708 PIC_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_IOPORT_WRITE); 707 709 rc = pic_ioport_write(pDevIns, pThis, pThisCC, &RT_SAFE_SUBSCRIPT(pThis->aPics, iPic), offPort, u32); 708 710 PIC_UNLOCK(pDevIns, pThisCC); … … 722 724 PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC); 723 725 PPICSTATE pPic = (PPICSTATE)pvUser; 724 PIC_LOCK (pDevIns, pThisCC, VINF_IOM_R3_IOPORT_READ);726 PIC_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_IOPORT_READ); 725 727 *pu32 = pPic->elcr; 726 728 PIC_UNLOCK(pDevIns, pThisCC); … … 741 743 PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC); 742 744 PPICSTATE pPic = (PPICSTATE)pvUser; 743 PIC_LOCK (pDevIns, pThisCC, VINF_IOM_R3_IOPORT_WRITE);745 PIC_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_IOPORT_WRITE); 744 746 pPic->elcr = u32 & pPic->elcr_mask; 745 747 PIC_UNLOCK(pDevIns, pThisCC); -
trunk/src/VBox/VMM/VMMAll/PDMAll.cpp
r90346 r90436 300 300 /** 301 301 * Locks PDM. 302 * This might call back to Ring-3 in order to deal with lock contention in GC and R3. 302 * 303 * This might call back to Ring-3 in order to deal with lock contention in RC 304 * and R0. 303 305 * 304 306 * @param pVM The cross context VM structure. … … 308 310 #ifdef IN_RING3 309 311 int rc = PDMCritSectEnter(pVM, &pVM->pdm.s.CritSect, VERR_IGNORED); 312 AssertRC(rc); 310 313 #else 311 314 int rc = PDMCritSectEnter(pVM, &pVM->pdm.s.CritSect, VERR_GENERAL_FAILURE); 312 if (rc == VERR_GENERAL_FAILURE) 313 rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PDM_LOCK, 0); 315 if (RT_SUCCESS(rc)) 316 { /* likely */ } 317 else 318 { 319 if (rc == VERR_GENERAL_FAILURE) 320 rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PDM_LOCK, 0); 321 PDM_CRITSECT_RELEASE_ASSERT_RC(pVM, &pVM->pdm.s.CritSect, rc); 322 } 314 323 #endif 315 AssertRC(rc);316 324 } 317 325 … … 323 331 * @returns rc if we're in GC or R0 and can't get the lock. 324 332 * @param pVM The cross context VM structure. 325 * @param rc 326 */ 327 int pdmLockEx(PVMCC pVM, int rc )328 { 329 return PDMCritSectEnter(pVM, &pVM->pdm.s.CritSect, rc );333 * @param rcBusy The RC to return in GC or R0 when we can't get the lock. 334 */ 335 int pdmLockEx(PVMCC pVM, int rcBusy) 336 { 337 return PDMCritSectEnter(pVM, &pVM->pdm.s.CritSect, rcBusy); 330 338 } 331 339 -
trunk/src/VBox/VMM/include/PDMInternal.h
r90420 r90436 1694 1694 1695 1695 void pdmLock(PVMCC pVM); 1696 int pdmLockEx(PVMCC pVM, int rc );1696 int pdmLockEx(PVMCC pVM, int rcBusy); 1697 1697 void pdmUnlock(PVMCC pVM); 1698 1698 bool pdmLockIsOwner(PVMCC pVM);
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