Changeset 90445 in vbox
- Timestamp:
- Jul 30, 2021 10:18:24 PM (4 years ago)
- svn:sync-xref-src-repo-rev:
- 146049
- Location:
- trunk/src/VBox/Devices
- Files:
-
- 7 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp
r90436 r90445 173 173 174 174 /** Acquires the cache lock. */ 175 # ifdef IN_RING3176 # define IOMMU_CACHE_LOCK(a_pDevIns, a_pThis)PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSectCache, VERR_IGNORED)177 # else178 # define IOMMU_CACHE_LOCK(a_pDevIns, a_pThis) \175 # ifdef IN_RING3 176 # define IOMMU_CACHE_LOCK(a_pDevIns, a_pThis) PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSectCache, VERR_IGNORED) 177 # else 178 # define IOMMU_CACHE_LOCK(a_pDevIns, a_pThis) \ 179 179 do { \ 180 180 int const rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSectCache, VINF_SUCCESS); \ 181 AssertRC(rcLock); \181 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV((a_pDevIns), &(a_pThis)->CritSectCache, rcLock); \ 182 182 } while (0) 183 # endif183 # endif 184 184 185 185 /** Releases the cache lock. */ -
trunk/src/VBox/Devices/PC/DevRTC.cpp
r89735 r90445 924 924 pHlp->pfnSSMGetS64(pSSM, &pThis->next_second_time); 925 925 PDMDevHlpTimerLoad(pDevIns, pThis->hSecondTimer, pSSM); 926 PDMDevHlpTimerLoad(pDevIns, pThis->hSecondTimer2, pSSM); 926 rc = PDMDevHlpTimerLoad(pDevIns, pThis->hSecondTimer2, pSSM); 927 AssertRCReturn(rc, rc); 927 928 928 929 if (uVersion > RTC_SAVED_STATE_VERSION_VBOX_31) 929 pHlp->pfnSSMGetBool(pSSM, &pThis->fDisabledByHpet); 930 { 931 rc = pHlp->pfnSSMGetBool(pSSM, &pThis->fDisabledByHpet); 932 AssertRCReturn(rc, rc); 933 } 930 934 931 935 if (uVersion > RTC_SAVED_STATE_VERSION_VBOX_32PRE) … … 933 937 /* Second CMOS bank. */ 934 938 pHlp->pfnSSMGetMem(pSSM, &pThis->cmos_data[CMOS_BANK_SIZE], CMOS_BANK_SIZE); 935 pHlp->pfnSSMGetU8(pSSM, &pThis->cmos_index[1]); 939 rc = pHlp->pfnSSMGetU8(pSSM, &pThis->cmos_index[1]); 940 AssertRCReturn(rc, rc); 936 941 } 937 942 … … 944 949 int period = 1 << (period_code - 1); 945 950 LogRel(("RTC: period=%#x (%d) %u Hz (restore)\n", period, period, _32K / period)); 946 PDMDevHlpCritSectEnter(pDevIns, pDevIns->pCritSectRoR3, VINF_SUCCESS); 951 rc = PDMDevHlpCritSectEnter(pDevIns, pDevIns->pCritSectRoR3, VINF_SUCCESS); 952 AssertRCReturn(rc, rc); 947 953 PDMDevHlpTimerSetFrequencyHint(pDevIns, pThis->hPeriodicTimer, _32K / period); 948 954 PDMDevHlpCritSectLeave(pDevIns, pDevIns->pCritSectRoR3); -
trunk/src/VBox/Devices/Parallel/DevParallel.cpp
r90332 r90445 304 304 PPARALLELPORT pThis = PDMDEVINS_2_DATA(pDevIns, PPARALLELPORT); 305 305 306 PDMDevHlpCritSectEnter(pDevIns, pDevIns->pCritSectRoR3, VINF_SUCCESS); 306 int rc = PDMDevHlpCritSectEnter(pDevIns, pDevIns->pCritSectRoR3, VINF_SUCCESS); 307 AssertRCReturn(rc, rc); 308 307 309 parallelR3IrqSet(pDevIns, pThis); 310 308 311 PDMDevHlpCritSectLeave(pDevIns, pDevIns->pCritSectRoR3); 309 312 -
trunk/src/VBox/Devices/Serial/UartCore.cpp
r90332 r90445 877 877 PDMDevHlpTimerSetRelative(pDevIns, pThis->hTimerTxUnconnected, pThis->cSymbolXferTicks, NULL); 878 878 879 PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VINF_SUCCESS);879 rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VINF_SUCCESS); 880 880 } 881 881 #endif -
trunk/src/VBox/Devices/Storage/DevATA.cpp
r90209 r90445 897 897 { 898 898 int rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->AsyncIORequestLock, VINF_SUCCESS); 899 AssertRC(rc);899 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pCtl->AsyncIORequestLock, rc); 900 900 901 901 pCtl->AsyncIOReqHead = 0; … … 910 910 { 911 911 int rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->AsyncIORequestLock, VINF_SUCCESS); 912 AssertRC(rc);912 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pCtl->AsyncIORequestLock, rc); 913 913 914 914 uint8_t const iAsyncIORequest = pCtl->AsyncIOReqHead % RT_ELEMENTS(pCtl->aAsyncIORequests); … … 935 935 936 936 int rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->AsyncIORequestLock, VINF_SUCCESS); 937 AssertRC(rc);937 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pCtl->AsyncIORequestLock, rc); 938 938 939 939 if (pCtl->AsyncIOReqHead != pCtl->AsyncIOReqTail) … … 960 960 { 961 961 int rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->AsyncIORequestLock, VINF_SUCCESS); 962 AssertRC(rc);962 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pCtl->AsyncIORequestLock, rc); 963 963 964 964 if (pCtl->AsyncIOReqHead != pCtl->AsyncIOReqTail && pCtl->aAsyncIORequests[pCtl->AsyncIOReqTail].ReqType == ReqType) … … 984 984 { 985 985 int rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->AsyncIORequestLock, VINF_SUCCESS); 986 AssertRC(rc);986 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pCtl->AsyncIORequestLock, rc); 987 987 988 988 LogRel(("PIIX3 ATA: Ctl#%d: request queue dump (topmost is current):\n", pCtl->iCtl)); … … 1038 1038 { 1039 1039 int rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->AsyncIORequestLock, VINF_SUCCESS); 1040 AssertRC(rc);1040 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pCtl->AsyncIORequestLock, rc); 1041 1041 1042 1042 bool fIdle = pCtl->fRedoIdle; … … 1268 1268 { 1269 1269 STAM_PROFILE_START(&pCtl->StatLockWait, a); 1270 PDMDevHlpCritSectEnter(pDevIns, &pCtl->lock, VINF_SUCCESS); 1270 int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pCtl->lock, VINF_SUCCESS); 1271 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pCtl->lock, rcLock); 1271 1272 STAM_PROFILE_STOP(&pCtl->StatLockWait, a); 1272 1273 } … … 5766 5767 */ 5767 5768 int rc = PDMDevHlpCritSectEnter(pDevIns, &pCtl->AsyncIORequestLock, VINF_SUCCESS); 5768 AssertRC(rc);5769 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pCtl->AsyncIORequestLock, rc); 5769 5770 5770 5771 if ( pCtlR3->fSignalIdle -
trunk/src/VBox/Devices/Storage/DevBusLogic.cpp
r89266 r90445 1375 1375 1376 1376 int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSectIntr, VINF_SUCCESS); 1377 AssertRC(rc);1377 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSectIntr, rc); 1378 1378 1379 1379 RTGCPHYS GCPhysAddrMailboxIncoming = pThis->GCPhysAddrMailboxIncomingBase -
trunk/src/VBox/Devices/Storage/DevLsiLogicSCSI.cpp
r89196 r90445 729 729 static void lsilogicR3FinishContextReply(PPDMDEVINS pDevIns, PLSILOGICSCSI pThis, uint32_t u32MessageContext) 730 730 { 731 int rc;732 733 731 LogFlowFunc(("pThis=%#p u32MessageContext=%#x\n", pThis, u32MessageContext)); 734 732 … … 736 734 737 735 /* Write message context ID into reply post queue. */ 738 rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->ReplyPostQueueCritSect, VINF_SUCCESS);739 AssertRC(rc);736 int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->ReplyPostQueueCritSect, VINF_SUCCESS); 737 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->ReplyPostQueueCritSect, rc); 740 738 741 739 /* Check for a entry in the queue. */ … … 792 790 */ 793 791 # ifdef IN_RING3 794 int rc;795 792 /* Grab a free reply message from the queue. */ 796 rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->ReplyFreeQueueCritSect, VINF_SUCCESS);797 AssertRC(rc);793 int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->ReplyFreeQueueCritSect, VINF_SUCCESS); 794 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->ReplyFreeQueueCritSect, rc); 798 795 799 796 /* Check for a free reply frame. */ … … 822 819 /* Write low 32bits of reply frame into post reply queue. */ 823 820 rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->ReplyPostQueueCritSect, VINF_SUCCESS); 824 AssertRC(rc);821 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->ReplyPostQueueCritSect, rc); 825 822 826 823 /* Check for a entry in the queue. */
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