VirtualBox

Changeset 9069 in vbox for trunk


Ignore:
Timestamp:
May 23, 2008 11:35:22 AM (17 years ago)
Author:
vboxsync
Message:

Interpret msr reads and writes (currently disabled in order not to break anything at this point in time)

Location:
trunk
Files:
5 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/em.h

    r8225 r9069  
    332332EMDECL(uint32_t) EMEmulateLockCmpXchg8b(RTHCPTR pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX);
    333333EMDECL(uint32_t) EMEmulateCmpXchg8b32(RTHCPTR pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX);
     334EMDECL(int)      EMInterpretRdmsr(PVM pVM, PCPUMCTXCORE pRegFrame);
     335EMDECL(int)      EMInterpretWrmsr(PVM pVM, PCPUMCTXCORE pRegFrame);
    334336
    335337#ifdef IN_RING3

  • trunk/include/VBox/x86.h

    r8536 r9069  
    260260    /** Bit 8 - CX8 - CMPXCHG8B instruction. */
    261261    unsigned    u1CX8 : 1;
    262     /** Bit 9 - APIC - APIC On-Chick. */
     262    /** Bit 9 - APIC - APIC On-Chip. */
    263263    unsigned    u1APIC : 1;
    264264    /** Bit 10 - Reserved. */
    … …  
    698698 * @{
    699699 */
     700#ifndef MSR_IA32_APICBASE /* qemu cpu.h klugde */
     701#define MSR_IA32_APICBASE                   0x1b
     702#endif
     703
    700704/** CPU Feature control. */
    701705#define MSR_IA32_FEATURE_CONTROL            0x3A
    … …  
    718722
    719723/* Page Attribute Table. */
    720 #define IA32_CR_PAT                         0x277
     724#define MSR_IA32_CR_PAT                     0x277
    721725
    722726/** Basic VMX information. */

  • trunk/src/VBox/VMM/EM.cpp

    r8985 r9069  
    209209    STAM_REG_USED(pVM, &pStats->StatGCXAdd,                 STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/XAdd",      STAMUNIT_OCCURENCES,    "The number of times XADD was successfully interpreted.");
    210210    STAM_REG_USED(pVM, &pStats->StatHCXAdd,                 STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/XAdd",      STAMUNIT_OCCURENCES,    "The number of times XADD was successfully interpreted.");
     211    STAM_REG_USED(pVM, &pStats->StatHCRdmsr,                STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Rdmsr",      STAMUNIT_OCCURENCES,   "The number of times RDMSR was not interpreted.");
     212    STAM_REG_USED(pVM, &pStats->StatGCRdmsr,                STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Rdmsr",      STAMUNIT_OCCURENCES,   "The number of times RDMSR was not interpreted.");
     213    STAM_REG_USED(pVM, &pStats->StatHCWrmsr,                STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Wrmsr",      STAMUNIT_OCCURENCES,   "The number of times WRMSR was not interpreted.");
     214    STAM_REG_USED(pVM, &pStats->StatGCWrmsr,                STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Wrmsr",      STAMUNIT_OCCURENCES,   "The number of times WRMSR was not interpreted.");
    211215
    212216    STAM_REG(pVM, &pStats->StatGCInterpretFailed,           STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed",            STAMUNIT_OCCURENCES,    "The number of times an instruction was not interpreted.");
    … …  
    251255    STAM_REG_USED(pVM, &pStats->StatGCFailedRdtsc,          STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Rdtsc",      STAMUNIT_OCCURENCES,    "The number of times RDTSC was not interpreted.");
    252256    STAM_REG_USED(pVM, &pStats->StatHCFailedRdtsc,          STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Rdtsc",      STAMUNIT_OCCURENCES,    "The number of times RDTSC was not interpreted.");
     257    STAM_REG_USED(pVM, &pStats->StatGCFailedRdmsr,          STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Rdmsr",      STAMUNIT_OCCURENCES,    "The number of times RDMSR was not interpreted.");
     258    STAM_REG_USED(pVM, &pStats->StatHCFailedRdmsr,          STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Rdmsr",      STAMUNIT_OCCURENCES,    "The number of times RDMSR was not interpreted.");
     259    STAM_REG_USED(pVM, &pStats->StatGCFailedWrmsr,          STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Wrmsr",      STAMUNIT_OCCURENCES,    "The number of times WRMSR was not interpreted.");
     260    STAM_REG_USED(pVM, &pStats->StatHCFailedWrmsr,          STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Wrmsr",      STAMUNIT_OCCURENCES,    "The number of times WRMSR was not interpreted.");
    253261
    254262    STAM_REG_USED(pVM, &pStats->StatGCFailedMisc,           STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Misc",       STAMUNIT_OCCURENCES,    "The number of times some misc instruction was encountered.");

  • trunk/src/VBox/VMM/EMInternal.h

    r8155 r9069  
    141141    STAMCOUNTER             StatGCClts;
    142142    STAMCOUNTER             StatHCClts;
     143    STAMCOUNTER             StatHCRdmsr;
     144    STAMCOUNTER             StatHCWrmsr;
     145    STAMCOUNTER             StatGCRdmsr;
     146    STAMCOUNTER             StatGCWrmsr;
    143147
    144148    STAMCOUNTER             StatGCInterpretFailed;
    … …  
    183187    STAMCOUNTER             StatGCFailedMWait;
    184188    STAMCOUNTER             StatHCFailedMWait;
     189    STAMCOUNTER             StatHCFailedRdmsr;
     190    STAMCOUNTER             StatHCFailedWrmsr;
     191    STAMCOUNTER             StatGCFailedRdmsr;
     192    STAMCOUNTER             StatGCFailedWrmsr;
    185193
    186194    STAMCOUNTER             StatGCFailedAdd;

  • trunk/src/VBox/VMM/VMMAll/EMAll.cpp

    r8242 r9069  
    3737#include <VBox/hwaccm.h>
    3838#include <VBox/tm.h>
     39#include <VBox/pdmapi.h>
    3940
    4041#include <VBox/param.h>
    … …  
    20422043}
    20432044
     2045/**
     2046 * Interpret RDMSR
     2047 *
     2048 * @returns VBox status code.
     2049 * @param   pVM         The VM handle.
     2050 * @param   pRegFrame   The register frame.
     2051 *
     2052 */
     2053EMDECL(int) EMInterpretRdmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
     2054{
     2055    uint32_t u32Dummy, u32Features, cpl;
     2056    uint64_t val;
     2057    CPUMCTX *pCtx;
     2058    int      rc;
     2059
     2060    rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
     2061    AssertRC(rc);
     2062
     2063    /* Get the current privilege level. */
     2064    cpl = CPUMGetGuestCPL(pVM, pRegFrame);
     2065    if (cpl != 0)
     2066        return VERR_EM_INTERPRETER; /* supervisor only */
     2067
     2068    CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
     2069    if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
     2070        return VERR_EM_INTERPRETER; /* not supported */
     2071
     2072    switch (pRegFrame->ecx)
     2073    {
     2074    case MSR_IA32_APICBASE:
     2075        rc = PDMApicGetBase(pVM, &val);
     2076        AssertRC(rc);
     2077        break;
     2078
     2079    case MSR_IA32_CR_PAT:
     2080        val = pCtx->msrPAT;
     2081        break;
     2082
     2083    case MSR_IA32_SYSENTER_CS:
     2084        val = pCtx->SysEnter.cs;
     2085        break;
     2086
     2087    case MSR_IA32_SYSENTER_EIP:
     2088        val = pCtx->SysEnter.eip;
     2089        break;
     2090
     2091    case MSR_IA32_SYSENTER_ESP:
     2092        val = pCtx->SysEnter.esp;
     2093        break;
     2094
     2095    case MSR_K6_EFER:
     2096        val = pCtx->msrEFER;
     2097        break;
     2098
     2099    case MSR_K8_SF_MASK:
     2100        val = pCtx->msrSFMASK;
     2101        break;
     2102
     2103    case MSR_K6_STAR:
     2104        val = pCtx->msrSTAR;
     2105        break;
     2106
     2107    case MSR_K8_LSTAR:
     2108        val = pCtx->msrLSTAR;
     2109        break;
     2110
     2111    case MSR_K8_CSTAR:
     2112        val = pCtx->msrCSTAR;
     2113        break;
     2114
     2115    case MSR_K8_FS_BASE:
     2116        val = pCtx->msrFSBASE;
     2117        break;
     2118
     2119    case MSR_K8_GS_BASE:
     2120        val = pCtx->msrGSBASE;
     2121        break;
     2122
     2123    case MSR_K8_KERNEL_GS_BASE:
     2124        val = pCtx->msrKERNELGSBASE;
     2125        break;
     2126
     2127    default:
     2128        /* We should actually trigger a #GP here, but don't as that might cause more trouble. */
     2129        val = 0;
     2130        break;
     2131    }
     2132    Log(("EMInterpretRdmsr %x -> val=%VX64\n", pRegFrame->ecx, val));
     2133    pRegFrame->eax = (uint32_t) val;
     2134    pRegFrame->edx = (uint32_t) (val >> 32ULL);
     2135    return VINF_SUCCESS;
     2136}
     2137
     2138/**
     2139 * RDMSR Emulation.
     2140 */
     2141static int emInterpretRdmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     2142{
     2143    return EMInterpretRdmsr(pVM, pRegFrame);
     2144}
     2145
     2146/**
     2147 * Interpret WRMSR
     2148 *
     2149 * @returns VBox status code.
     2150 * @param   pVM         The VM handle.
     2151 * @param   pRegFrame   The register frame.
     2152 *
     2153 */
     2154EMDECL(int) EMInterpretWrmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
     2155{
     2156    uint32_t u32Dummy, u32Features, cpl;
     2157    uint64_t val;
     2158    CPUMCTX *pCtx;
     2159    int      rc;
     2160
     2161    rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
     2162    AssertRC(rc);
     2163
     2164    /* Get the current privilege level. */
     2165    cpl = CPUMGetGuestCPL(pVM, pRegFrame);
     2166    if (cpl != 0)
     2167        return VERR_EM_INTERPRETER; /* supervisor only */
     2168
     2169    CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
     2170    if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
     2171        return VERR_EM_INTERPRETER; /* not supported */
     2172
     2173    val = (uint64_t)pRegFrame->eax | ((uint64_t)pRegFrame->edx << 32ULL);
     2174    Log(("EMInterpretWrmsr %x val=%VX64\n", pRegFrame->ecx, val));
     2175    switch (pRegFrame->ecx)
     2176    {
     2177    case MSR_IA32_APICBASE:
     2178        rc = PDMApicSetBase(pVM, val);
     2179        AssertRC(rc);
     2180        break;
     2181
     2182    case MSR_IA32_CR_PAT:
     2183        pCtx->msrPAT = val;
     2184        break;
     2185
     2186    case MSR_IA32_SYSENTER_CS:
     2187        pCtx->SysEnter.cs = val;
     2188        break;
     2189
     2190    case MSR_IA32_SYSENTER_EIP:
     2191        pCtx->SysEnter.eip = val;
     2192        break;
     2193
     2194    case MSR_IA32_SYSENTER_ESP:
     2195        pCtx->SysEnter.esp = val;
     2196        break;
     2197
     2198    case MSR_K6_EFER:
     2199        AssertFailed();
     2200        pCtx->msrEFER = val;
     2201        break;
     2202
     2203    case MSR_K8_SF_MASK:
     2204        pCtx->msrSFMASK = val;
     2205        break;
     2206
     2207    case MSR_K6_STAR:
     2208        pCtx->msrSTAR = val;
     2209        break;
     2210
     2211    case MSR_K8_LSTAR:
     2212        pCtx->msrLSTAR = val;
     2213        break;
     2214
     2215    case MSR_K8_CSTAR:
     2216        pCtx->msrCSTAR = val;
     2217        break;
     2218
     2219    case MSR_K8_FS_BASE:
     2220        pCtx->msrFSBASE = val;
     2221        break;
     2222
     2223    case MSR_K8_GS_BASE:
     2224        pCtx->msrGSBASE = val;
     2225        break;
     2226
     2227    case MSR_K8_KERNEL_GS_BASE:
     2228        pCtx->msrKERNELGSBASE = val;
     2229        break;
     2230
     2231    default:
     2232        /* We should actually trigger a #GP here, but don't as that might cause more trouble. */
     2233        break;
     2234    }
     2235    return VINF_SUCCESS;
     2236}
     2237
     2238/**
     2239 * WRMSR Emulation.
     2240 */
     2241static int emInterpretWrmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
     2242{
     2243    return EMInterpretWrmsr(pVM, pRegFrame);
     2244}
    20442245
    20452246/**
    … …  
    21452346        INTERPRET_CASE(OP_MONITOR, Monitor);
    21462347        INTERPRET_CASE(OP_MWAIT, MWait);
     2348#ifdef VBOX_WITH_MSR_EMULATION
     2349        INTERPRET_CASE(OP_RDMSR, Rdmsr);
     2350        INTERPRET_CASE(OP_WRMSR, Wrmsr);
     2351#endif
    21472352        INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
    21482353        INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
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