include

Timestamp:

Sep 15, 2021 10:26:50 PM (3 years ago)

Author:

vboxsync

Message:

VMM/CPUM: Moved CPUIDs and MSRs from the hyper heap and into the VM structure (might not be such a great idea for MSRs actually). bugref:10093

Location:

trunk/src/VBox/VMM/include

Files:

trunk/src/VBox/VMM/include/CPUMInternal.h

-              r91120
+              r91266
     uint64_t                    uScalableBusFreq;
+    /** Pointer to the MSR ranges (ring-0 pointer). */
+    R0PTRTYPE(PCPUMMSRRANGE)    paMsrRangesR0;
+    /** Pointer to the CPUID leaves (ring-0 pointer). */
+    R0PTRTYPE(PCPUMCPUIDLEAF)   paCpuIdLeavesR0;
+    /** Pointer to the MSR ranges (ring-3 pointer). */
+    /** Pointer to the MSR ranges (for compatibility with old hyper heap code). */
     R3PTRTYPE(PCPUMMSRRANGE)    paMsrRangesR3;
     /** Pointer to the CPUID leaves (ring-3 pointer). */
+    /** Pointer to the CPUID leaves (for compatibility with old hyper heap code). */
     R3PTRTYPE(PCPUMCPUIDLEAF)   paCpuIdLeavesR3;
+    /** CPUID leaves. */
+    CPUMCPUIDLEAF               aCpuIdLeaves[256];
+    /** MSR ranges.
+     * @todo This is insane, so might want to move this into a separate
+     *       allocation.  The insanity is mainly for more recent AMD CPUs. */
+    CPUMMSRRANGE                aMsrRanges[8192];
 } CPUMINFO;
 /** Pointer to a CPU info structure. */

-              r87766
+              r91266
     .DefCpuId               resb CPUMCPUID_size     ; CPUMCPUID
     .uScalableBusFreq       resq 1                  ; uint64_t
-    .paMsrRangesR0          RTR0PTR_RES 1           ; R0PTRTYPE(PCPUMMSRRANGE)
-    .paCpuIdLeavesR0        RTR0PTR_RES 1           ; R0PTRTYPE(PCPUMCPUIDLEAF)
     .paMsrRangesR3          RTR3PTR_RES 1           ; R3PTRTYPE(PCPUMMSRRANGE)
     .paCpuIdLeavesR3        RTR3PTR_RES 1           ; R3PTRTYPE(PCPUMCPUIDLEAF)
+    .aCpuIdLeaves           resb 256*32
+    .aMsrRanges             resb 8192*128
 endstruc
 …
     .HostFeatures               resb    48
     .GuestFeatures              resb    48
     .GuestInfo                  resb    RTHCPTR_CB*4 + 4*12
+    .GuestInfo                  resb    CPUMINFO_size
     ; Patch manager saved state compatability CPUID leaf arrays

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