Index: /trunk/include/VBox/vmm/cpum.h
===================================================================
--- /trunk/include/VBox/vmm/cpum.h	(revision 91322)
+++ /trunk/include/VBox/vmm/cpum.h	(revision 91323)
@@ -1481,4 +1481,5 @@
                                           uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
 VMMDECL(uint64_t)       CPUMGetGuestEFER(PCVMCPU pVCpu);
+VMM_INT_DECL(uint64_t)  CPUMGetGuestIa32FeatCtrl(PCVMCPUCC pVCpu);
 VMM_INT_DECL(uint64_t)  CPUMGetGuestIa32MtrrCap(PCVMCPU pVCpu);
 VMM_INT_DECL(uint64_t)  CPUMGetGuestIa32SmmMonitorCtl(PCVMCPU pVCpu);
Index: /trunk/include/VBox/vmm/hm_vmx.h
===================================================================
--- /trunk/include/VBox/vmm/hm_vmx.h	(revision 91322)
+++ /trunk/include/VBox/vmm/hm_vmx.h	(revision 91323)
@@ -1197,6 +1197,4 @@
 typedef struct VMXMSRS
 {
-    /** VMX/SMX Feature control. */
-    uint64_t        u64FeatCtrl;
     /** Basic information. */
     uint64_t        u64Basic;
@@ -1238,5 +1236,5 @@
     uint64_t        u64ProcCtls3;
     /** Reserved for future. */
-    uint64_t        a_u64Reserved[8];
+    uint64_t        a_u64Reserved[9];
 } VMXMSRS;
 AssertCompileSizeAlignment(VMXMSRS, 8);
Index: /trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp	(revision 91322)
+++ /trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp	(revision 91323)
@@ -236,4 +236,18 @@
 }
 
+/**
+ * Get IA32_FEATURE_CONTROL value for IEM, NEM and cpumMsrRd_Ia32FeatureControl.
+ *
+ * @returns IA32_FEATURE_CONTROL value.
+ * @param   pVCpu           The cross context per CPU structure.
+ */
+VMM_INT_DECL(uint64_t) CPUMGetGuestIa32FeatCtrl(PCVMCPUCC pVCpu)
+{
+    uint64_t uFeatCtrlMsr = MSR_IA32_FEATURE_CONTROL_LOCK;
+    if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
+        uFeatCtrlMsr |= MSR_IA32_FEATURE_CONTROL_VMXON;
+    return uFeatCtrlMsr;
+}
+
 
 /** @callback_method_impl{FNCPUMRDMSR} */
@@ -241,5 +255,5 @@
 {
     RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
-    *puValue = pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64FeatCtrl;
+    *puValue = CPUMGetGuestIa32FeatCtrl(pVCpu);
     return VINF_SUCCESS;
 }
Index: /trunk/src/VBox/VMM/VMMAll/HMAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/HMAll.cpp	(revision 91322)
+++ /trunk/src/VBox/VMM/VMMAll/HMAll.cpp	(revision 91323)
@@ -821,5 +821,4 @@
     AssertReturnVoid(pHwvirtMsrs);
     AssertReturnVoid(pVmxMsrs);
-    pVmxMsrs->u64FeatCtrl      = pHwvirtMsrs->u.vmx.u64FeatCtrl;
     pVmxMsrs->u64Basic         = pHwvirtMsrs->u.vmx.u64Basic;
     pVmxMsrs->PinCtls.u        = pHwvirtMsrs->u.vmx.PinCtls.u;
Index: /trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h	(revision 91322)
+++ /trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h	(revision 91323)
@@ -8495,5 +8495,5 @@
 
         /* Feature control MSR's LOCK and VMXON bits. */
-        uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
+        uint64_t const uMsrFeatCtl = CPUMGetGuestIa32FeatCtrl(pVCpu);
         if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
                         == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
Index: /trunk/src/VBox/VMM/VMMR0/HMR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HMR0.cpp	(revision 91322)
+++ /trunk/src/VBox/VMM/VMMR0/HMR0.cpp	(revision 91323)
@@ -388,5 +388,5 @@
         g_uHmVmxHostMsrEfer = ASMRdMsr(MSR_K6_EFER);
 
-        /* Get VMX MSRs for determining VMX features we can ultimately use. */
+        /* Get VMX MSRs (and feature control MSR) for determining VMX features we can ultimately use. */
         SUPR0GetHwvirtMsrs(&g_HmMsrs, SUPVTCAPS_VT_X, false /* fForce */);
 
@@ -1178,4 +1178,5 @@
         pVM->hm.s.ForR3.vmx.u64HostMsrEfer          = g_uHmVmxHostMsrEfer;
         pVM->hm.s.ForR3.vmx.u64HostSmmMonitorCtl    = g_uHmVmxHostSmmMonitorCtl;
+        pVM->hm.s.ForR3.vmx.u64HostFeatCtrl         = g_HmMsrs.u.vmx.u64FeatCtrl;
         HMGetVmxMsrsFromHwvirtMsrs(&g_HmMsrs, &pVM->hm.s.ForR3.vmx.Msrs);
         /* If you need to tweak host MSRs for testing VMX R0 code, do it here. */
Index: /trunk/src/VBox/VMM/VMMR0/NEMR0Native-win.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/NEMR0Native-win.cpp	(revision 91322)
+++ /trunk/src/VBox/VMM/VMMR0/NEMR0Native-win.cpp	(revision 91323)
@@ -2115,6 +2115,7 @@
         {
             Assert(pInput->Names[iReg] == HvX64RegisterIa32FeatureControl);
-            if (paValues[iReg].Reg64 != pCtx->hwvirt.vmx.Msrs.u64FeatCtrl)
-                Log7(("NEM/%u: MSR FEATURE_CONTROL changed %RX64 -> %RX64 (!!)\n", pGVCpu->idCpu, pCtx->hwvirt.vmx.Msrs.u64FeatCtrl, paValues[iReg].Reg64));
+            uint64_t const uFeatCtrl = CPUMGetGuestIa32FeatCtrl(pVCpu);
+            if (paValues[iReg].Reg64 != uFeatCtrl)
+                Log7(("NEM/%u: MSR FEATURE_CONTROL changed %RX64 -> %RX64 (!!)\n", pGVCpu->idCpu, uFeatCtrl, paValues[iReg].Reg64));
             iReg++;
         }
Index: /trunk/src/VBox/VMM/VMMR3/CPUM.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/CPUM.cpp	(revision 91322)
+++ /trunk/src/VBox/VMM/VMMR3/CPUM.cpp	(revision 91323)
@@ -1277,7 +1277,4 @@
      */
 
-    /* Feature control. */
-    pGuestVmxMsrs->u64FeatCtrl = MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON;
-
     /* Basic information. */
     {
@@ -2407,5 +2404,5 @@
             SSMR3PutU16(pSSM,      pGstCtx->hwvirt.vmx.offVirtApicWrite);
             SSMR3PutBool(pSSM,     pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
-            SSMR3PutU64(pSSM,      pGstCtx->hwvirt.vmx.Msrs.u64FeatCtrl);
+            SSMR3PutU64(pSSM,      MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON); /* Deprecated since 2021/09/22. Value kept backwards compatibile with 6.1.26. */
             SSMR3PutU64(pSSM,      pGstCtx->hwvirt.vmx.Msrs.u64Basic);
             SSMR3PutU64(pSSM,      pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
@@ -2697,5 +2694,5 @@
                         SSMR3GetU16(pSSM,      &pGstCtx->hwvirt.vmx.offVirtApicWrite);
                         SSMR3GetBool(pSSM,     &pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
-                        SSMR3GetU64(pSSM,      &pGstCtx->hwvirt.vmx.Msrs.u64FeatCtrl);
+                        SSMR3Skip(pSSM,        sizeof(uint64_t)); /* Unused - used to be IA32_FEATURE_CONTROL, see @bugref{10106}. */
                         SSMR3GetU64(pSSM,      &pGstCtx->hwvirt.vmx.Msrs.u64Basic);
                         SSMR3GetU64(pSSM,      &pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
Index: /trunk/src/VBox/VMM/VMMR3/HM.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/HM.cpp	(revision 91322)
+++ /trunk/src/VBox/VMM/VMMR3/HM.cpp	(revision 91323)
@@ -1052,5 +1052,5 @@
     {
         LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.ForR3.rcInit));
-        LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.ForR3.vmx.Msrs.u64FeatCtrl));
+        LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.ForR3.vmx.u64HostFeatCtrl));
         switch (pVM->hm.s.ForR3.rcInit)
         {
@@ -1493,13 +1493,13 @@
 
     LogFunc(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
-    AssertLogRelReturn(pVM->hm.s.ForR3.vmx.Msrs.u64FeatCtrl != 0, VERR_HM_IPE_4);
+    AssertLogRelReturn(pVM->hm.s.ForR3.vmx.u64HostFeatCtrl != 0, VERR_HM_IPE_4);
 
     LogRel(("HM: Using VT-x implementation 3.0\n"));
     LogRel(("HM: Max resume loops                  = %u\n",     pVM->hm.s.cMaxResumeLoopsCfg));
     LogRel(("HM: Host CR4                          = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostCr4));
-    LogRel(("HM: Host EFER                         = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostMsrEfer));
+    LogRel(("HM: MSR_IA32_EFER                     = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostMsrEfer));
     LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL          = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostSmmMonitorCtl));
 
-    hmR3VmxReportFeatCtlMsr(pVM->hm.s.ForR3.vmx.Msrs.u64FeatCtrl);
+    hmR3VmxReportFeatCtlMsr(pVM->hm.s.ForR3.vmx.u64HostFeatCtrl);
     hmR3VmxReportBasicMsr(pVM->hm.s.ForR3.vmx.Msrs.u64Basic);
 
Index: /trunk/src/VBox/VMM/include/HMInternal.h
===================================================================
--- /trunk/src/VBox/VMM/include/HMInternal.h	(revision 91322)
+++ /trunk/src/VBox/VMM/include/HMInternal.h	(revision 91323)
@@ -545,4 +545,6 @@
             /** Host EFER value (set by ring-0 VMX init, for logging and guest NX). */
             uint64_t                    u64HostMsrEfer;
+            /** Host IA32_FEATURE_CONTROL MSR (set by ring-0 VMX init, for logging). */
+            uint64_t                    u64HostFeatCtrl;
 
             /** The first valid host LBR branch-from-IP stack range. */
