Changeset 91378 in vbox for trunk

Timestamp:

Sep 27, 2021 9:04:31 AM (3 years ago)

Author:

vboxsync

Message:

VMM/IEM: Nested VMX: bugref:10092 VM-exit handler for EPT violation.

File:

• trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h

@@ -3712 +3712 @@
     return VINF_VMX_INTERCEPT_NOT_ACTIVE;
 }
+
+
+#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
+/**
+ * VMX VM-exit handler for EPT violation.
+ *
+ * @param   pVCpu       The cross context virtual CPU structure.
+ * @param   fAccess     The access causing the EPT violation, IEM_ACCESS_XXX.
+ * @param   fEptAccess  The EPT paging structure bits.
+ * @param   GCPhysAddr  The physical address causing the EPT violation.
+ * @param   GCPtrAddr   The linear address causing the EPT violation.
+ * @param   cbInstr     The VM-exit instruction length.
+ */
+IEM_STATIC VBOXSTRICTRC iemVmxVmexitEptViolation(PVMCPUCC pVCpu, uint32_t fAccess, uint64_t fEptAccess, RTGCPHYS GCPhysAddr,
+                                                 uint64_t GCPtrAddr, bool fLinearAddrValid, uint8_t cbInstr)
+{
+    /*
+     * If the linear address isn't valid (can happen when loading PDPTEs
+     * as part of MOV CR execution) the linear address field is undefined.
+     * While we can leave it this way, it's preferrable to zero it for consistency.
+     */
+    Assert(fLinearAddrValid || GCPtrAddr == 0);
+
+    uint64_t const fCaps = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64EptVpidCaps;
+    uint8_t const fSupportsAccessDirty = fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY;
+
+    uint8_t const fDataRead   = ((fAccess & IEM_ACCESS_DATA_R)  == IEM_ACCESS_DATA_R)  | fSupportsAccessDirty;
+    uint8_t const fDataWrite  = ((fAccess & IEM_ACCESS_DATA_RW) == IEM_ACCESS_DATA_RW) | fSupportsAccessDirty;
+    uint8_t const fInstrFetch = (fAccess & IEM_ACCESS_INSTRUCTION) == IEM_ACCESS_INSTRUCTION;
+    uint8_t const fEptRead    = fEptAccess & EPT_E_READ;
+    uint8_t const fEptWrite   = fEptAccess & EPT_E_WRITE;
+    uint8_t const fEptExec    = fEptAccess & EPT_E_EXECUTE;
+    bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
+
+    uint64_t const u64ExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_READ,        fDataRead)
+                               | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE,       fDataWrite)
+                               | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH, fInstrFetch)
+                               | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_READ,         fEptRead)
+                               | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE,        fEptWrite)
+                               | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE,      fEptExec)
+                               | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID,  fLinearAddrValid)
+                               | RT_BF_MAKE(VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET,   fNmiUnblocking);
+
+    /** @todo bit 8 of Exit Qualification!
+     *  If the access causing the EPT violation is to a guest-physical address that is
+     *  the translation of a linear address.
+     *   - OR -
+     *  if the access causing the EPT violation is to a paging-structure entry as part
+     *  of a page walk or the update of an accessed or dirty bit.
+     *
+     *  Caller needs to be able to distinguish this... */
+
+    uint64_t const fMiscCaps  = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
+    uint32_t const fProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u32ProcCtls2;
+    Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION));   /* Advanced VM-exit info. not supported */
+    Assert(!(fCaps & MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK));             /* Supervisor shadow stack control not supported. */
+    Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT)));                    /* Intel PT not supported. */
+    Assert(!(RT_BF_GET(fMiscCaps, VMX_BF_MISC_INTEL_PT)));                    /* Intel PT not supported. */
+    Assert(!(fProcCtls2 & VMX_PROC_CTLS2_MODE_BASED_EPT_PERM));               /* Mode-based execute control not supported. */
+
+    iemVmxVmcsSetExitGuestPhysAddr(pVCpu, GCPhysAddr);
+    iemVmxVmcsSetExitGuestLinearAddr(pVCpu, GCPtrAddr);
+    iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
+
+    return iemVmxVmexit(pVCpu, VMX_EXIT_EPT_VIOLATION, u64ExitQual);
+}
+#endif