Changeset 92189 in vbox for trunk/src/VBox
- Timestamp:
- Nov 3, 2021 10:41:34 AM (4 years ago)
- svn:sync-xref-src-repo-rev:
- 148018
- File:
-
- 1 edited
-
trunk/src/VBox/VMM/VMMAll/VMXAllTemplate.cpp.h (modified) (228 diffs)
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trunk/src/VBox/VMM/VMMAll/VMXAllTemplate.cpp.h
r92188 r92189 20 20 * Defined Constants And Macros * 21 21 *********************************************************************************************************************************/ 22 #if !defined(VMX_VMCS_WRITE_16) || !defined(VMX_VMCS_WRITE_32) || !defined(VMX_VMCS_WRITE_64) || !defined(VMX_VMCS_WRITE_64) 23 # error "At least one of the VMX_VMCS_WRITE_16, VMX_VMCS_WRITE_32, VMX_VMCS_WRITE_64 or VMX_VMCS_WRITE_64 is missing" 24 #endif 25 26 27 #if !defined(VMX_VMCS_READ_16) || !defined(VMX_VMCS_READ_32) || !defined(VMX_VMCS_READ_64) || !defined(VMX_VMCS_READ_64) 28 # error "At least one of the VMX_VMCS_READ_16, VMX_VMCS_READ_32, VMX_VMCS_READ_64 or VMX_VMCS_READ_64 is missing" 29 #endif 30 31 22 32 /** Use the function table. */ 23 33 #define HMVMX_USE_FUNCTION_TABLE … … 1013 1023 * Sets the given Processor-based VM-execution controls. 1014 1024 * 1025 * @param pVCpu The cross context virtual CPU structure. 1015 1026 * @param pVmxTransient The VMX-transient structure. 1016 1027 * @param uProcCtls The Processor-based VM-execution controls to set. 1017 1028 */ 1018 static void vmxHCSetProcCtlsVmcs(PVM XTRANSIENT pVmxTransient, uint32_t uProcCtls)1029 static void vmxHCSetProcCtlsVmcs(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient, uint32_t uProcCtls) 1019 1030 { 1020 1031 PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo; … … 1022 1033 { 1023 1034 pVmcsInfo->u32ProcCtls |= uProcCtls; 1024 int rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls);1035 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls); 1025 1036 AssertRC(rc); 1026 1037 } … … 1052 1063 { 1053 1064 pVmcsInfo->u32ProcCtls &= ~uProcCtls; 1054 int rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls);1065 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls); 1055 1066 AssertRC(rc); 1056 1067 } … … 1062 1073 * Sets the TSC offset for the current VMCS. 1063 1074 * 1064 * @param uTscOffset The TSC offset to set. 1065 * @param pVmcsInfo The VMCS info. object. 1066 */ 1067 static void vmxHCSetTscOffsetVmcs(PVMXVMCSINFO pVmcsInfo, uint64_t uTscOffset) 1075 * @param pVCpu The cross context virtual CPU structure. 1076 * @param uTscOffset The TSC offset to set. 1077 * @param pVmcsInfo The VMCS info. object. 1078 */ 1079 static void vmxHCSetTscOffsetVmcs(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo, uint64_t uTscOffset) 1068 1080 { 1069 1081 if (pVmcsInfo->u64TscOffset != uTscOffset) 1070 1082 { 1071 int rc = VMX WriteVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, uTscOffset);1083 int rc = VMX_VMCS_WRITE_64(pVCpu, VMX_VMCS64_CTRL_TSC_OFFSET_FULL, uTscOffset); 1072 1084 AssertRC(rc); 1073 1085 pVmcsInfo->u64TscOffset = uTscOffset; … … 1080 1092 * VMCS. 1081 1093 * 1094 * @param pVCpu The cross context virtual CPU structure. 1082 1095 * @param pVmxTransient The VMX-transient structure. 1083 1096 * @param uXcptMask The exception(s) to add. 1084 1097 */ 1085 static void vmxHCAddXcptInterceptMask(P CVMXTRANSIENT pVmxTransient, uint32_t uXcptMask)1098 static void vmxHCAddXcptInterceptMask(PVMCPUCC pVCpu, PCVMXTRANSIENT pVmxTransient, uint32_t uXcptMask) 1086 1099 { 1087 1100 PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo; … … 1090 1103 { 1091 1104 uXcptBitmap |= uXcptMask; 1092 int rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, uXcptBitmap);1105 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_EXCEPTION_BITMAP, uXcptBitmap); 1093 1106 AssertRC(rc); 1094 1107 pVmcsInfo->u32XcptBitmap = uXcptBitmap; … … 1100 1113 * Adds an exception to the exception bitmap and commits it to the current VMCS. 1101 1114 * 1115 * @param pVCpu The cross context virtual CPU structure. 1102 1116 * @param pVmxTransient The VMX-transient structure. 1103 1117 * @param uXcpt The exception to add. 1104 1118 */ 1105 static void vmxHCAddXcptIntercept(P CVMXTRANSIENT pVmxTransient, uint8_t uXcpt)1119 static void vmxHCAddXcptIntercept(PVMCPUCC pVCpu, PCVMXTRANSIENT pVmxTransient, uint8_t uXcpt) 1106 1120 { 1107 1121 Assert(uXcpt <= X86_XCPT_LAST); 1108 vmxHCAddXcptInterceptMask(pV mxTransient, RT_BIT_32(uXcpt));1122 vmxHCAddXcptInterceptMask(pVCpu, pVmxTransient, RT_BIT_32(uXcpt)); 1109 1123 } 1110 1124 … … 1162 1176 if (pVmcsInfo->u32XcptBitmap != u32XcptBitmap) 1163 1177 { 1164 int rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, u32XcptBitmap);1178 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_EXCEPTION_BITMAP, u32XcptBitmap); 1165 1179 AssertRC(rc); 1166 1180 pVmcsInfo->u32XcptBitmap = u32XcptBitmap; … … 1411 1425 { 1412 1426 AssertPtrReturnVoid(pVCpu); 1413 VMX ReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &pVCpu->hm.s.vmx.LastError.u32InstrError);1427 VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_RO_VM_INSTR_ERROR, &pVCpu->hm.s.vmx.LastError.u32InstrError); 1414 1428 } 1415 1429 pVCpu->CTX_SUFF(pVM)->hm.s.ForR3.rcInit = rc; … … 1422 1436 * transient structure. 1423 1437 * 1438 * @param pVCpu The cross context virtual CPU structure. 1424 1439 * @param pVmxTransient The VMX-transient structure. 1425 1440 */ 1426 DECLINLINE(void) vmxHCReadEntryIntInfoVmcs(PVM XTRANSIENT pVmxTransient)1427 { 1428 int rc = VMX ReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &pVmxTransient->uEntryIntInfo);1441 DECLINLINE(void) vmxHCReadEntryIntInfoVmcs(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient) 1442 { 1443 int rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &pVmxTransient->uEntryIntInfo); 1429 1444 AssertRC(rc); 1430 1445 } … … 1435 1450 * the VMX transient structure. 1436 1451 * 1452 * @param pVCpu The cross context virtual CPU structure. 1437 1453 * @param pVmxTransient The VMX-transient structure. 1438 1454 */ 1439 DECLINLINE(void) vmxHCReadEntryXcptErrorCodeVmcs(PVM XTRANSIENT pVmxTransient)1440 { 1441 int rc = VMX ReadVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, &pVmxTransient->uEntryXcptErrorCode);1455 DECLINLINE(void) vmxHCReadEntryXcptErrorCodeVmcs(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient) 1456 { 1457 int rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, &pVmxTransient->uEntryXcptErrorCode); 1442 1458 AssertRC(rc); 1443 1459 } … … 1448 1464 * the VMX transient structure. 1449 1465 * 1466 * @param pVCpu The cross context virtual CPU structure. 1450 1467 * @param pVmxTransient The VMX-transient structure. 1451 1468 */ 1452 DECLINLINE(void) vmxHCReadEntryInstrLenVmcs(PVM XTRANSIENT pVmxTransient)1453 { 1454 int rc = VMX ReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, &pVmxTransient->cbEntryInstr);1469 DECLINLINE(void) vmxHCReadEntryInstrLenVmcs(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient) 1470 { 1471 int rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, &pVmxTransient->cbEntryInstr); 1455 1472 AssertRC(rc); 1456 1473 } … … 1462 1479 * transient structure. 1463 1480 * 1481 * @param pVCpu The cross context virtual CPU structure. 1464 1482 * @param pVmxTransient The VMX-transient structure. 1465 1483 */ 1466 DECLINLINE(void) vmxHCReadExitIntInfoVmcs(PVM XTRANSIENT pVmxTransient)1484 DECLINLINE(void) vmxHCReadExitIntInfoVmcs(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient) 1467 1485 { 1468 1486 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_INTERRUPTION_INFO)) 1469 1487 { 1470 int rc = VMX ReadVmcs32(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &pVmxTransient->uExitIntInfo);1488 int rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &pVmxTransient->uExitIntInfo); 1471 1489 AssertRC(rc); 1472 1490 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_EXIT_INTERRUPTION_INFO; … … 1479 1497 * transient structure. 1480 1498 * 1499 * @param pVCpu The cross context virtual CPU structure. 1481 1500 * @param pVmxTransient The VMX-transient structure. 1482 1501 */ 1483 DECLINLINE(void) vmxHCReadExitIntErrorCodeVmcs(PVM XTRANSIENT pVmxTransient)1502 DECLINLINE(void) vmxHCReadExitIntErrorCodeVmcs(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient) 1484 1503 { 1485 1504 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_INTERRUPTION_ERROR_CODE)) 1486 1505 { 1487 int rc = VMX ReadVmcs32(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE, &pVmxTransient->uExitIntErrorCode);1506 int rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE, &pVmxTransient->uExitIntErrorCode); 1488 1507 AssertRC(rc); 1489 1508 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_EXIT_INTERRUPTION_ERROR_CODE; … … 1496 1515 * transient structure. 1497 1516 * 1517 * @param pVCpu The cross context virtual CPU structure. 1498 1518 * @param pVmxTransient The VMX-transient structure. 1499 1519 */ 1500 DECLINLINE(void) vmxHCReadExitInstrLenVmcs(PVM XTRANSIENT pVmxTransient)1520 DECLINLINE(void) vmxHCReadExitInstrLenVmcs(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient) 1501 1521 { 1502 1522 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_INSTR_LEN)) 1503 1523 { 1504 int rc = VMX ReadVmcs32(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &pVmxTransient->cbExitInstr);1524 int rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &pVmxTransient->cbExitInstr); 1505 1525 AssertRC(rc); 1506 1526 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_EXIT_INSTR_LEN; … … 1513 1533 * the VMX transient structure. 1514 1534 * 1535 * @param pVCpu The cross context virtual CPU structure. 1515 1536 * @param pVmxTransient The VMX-transient structure. 1516 1537 */ 1517 DECLINLINE(void) vmxHCReadExitInstrInfoVmcs(PVM XTRANSIENT pVmxTransient)1538 DECLINLINE(void) vmxHCReadExitInstrInfoVmcs(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient) 1518 1539 { 1519 1540 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_INSTR_INFO)) 1520 1541 { 1521 int rc = VMX ReadVmcs32(VMX_VMCS32_RO_EXIT_INSTR_INFO, &pVmxTransient->ExitInstrInfo.u);1542 int rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_RO_EXIT_INSTR_INFO, &pVmxTransient->ExitInstrInfo.u); 1522 1543 AssertRC(rc); 1523 1544 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_EXIT_INSTR_INFO; … … 1529 1550 * Reads the Exit Qualification from the VMCS into the VMX transient structure. 1530 1551 * 1552 * @param pVCpu The cross context virtual CPU structure. 1531 1553 * @param pVmxTransient The VMX-transient structure. 1532 1554 */ 1533 DECLINLINE(void) vmxHCReadExitQualVmcs(PVM XTRANSIENT pVmxTransient)1555 DECLINLINE(void) vmxHCReadExitQualVmcs(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient) 1534 1556 { 1535 1557 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_QUALIFICATION)) 1536 1558 { 1537 int rc = VMX ReadVmcsNw(VMX_VMCS_RO_EXIT_QUALIFICATION, &pVmxTransient->uExitQual);1559 int rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_RO_EXIT_QUALIFICATION, &pVmxTransient->uExitQual); 1538 1560 AssertRC(rc); 1539 1561 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_EXIT_QUALIFICATION; … … 1545 1567 * Reads the Guest-linear address from the VMCS into the VMX transient structure. 1546 1568 * 1569 * @param pVCpu The cross context virtual CPU structure. 1547 1570 * @param pVmxTransient The VMX-transient structure. 1548 1571 */ 1549 DECLINLINE(void) vmxHCReadGuestLinearAddrVmcs(PVM XTRANSIENT pVmxTransient)1572 DECLINLINE(void) vmxHCReadGuestLinearAddrVmcs(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient) 1550 1573 { 1551 1574 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_GUEST_LINEAR_ADDR)) 1552 1575 { 1553 int rc = VMX ReadVmcsNw(VMX_VMCS_RO_GUEST_LINEAR_ADDR, &pVmxTransient->uGuestLinearAddr);1576 int rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_RO_GUEST_LINEAR_ADDR, &pVmxTransient->uGuestLinearAddr); 1554 1577 AssertRC(rc); 1555 1578 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_GUEST_LINEAR_ADDR; … … 1561 1584 * Reads the Guest-physical address from the VMCS into the VMX transient structure. 1562 1585 * 1586 * @param pVCpu The cross context virtual CPU structure. 1563 1587 * @param pVmxTransient The VMX-transient structure. 1564 1588 */ 1565 DECLINLINE(void) vmxHCReadGuestPhysicalAddrVmcs(PVM XTRANSIENT pVmxTransient)1589 DECLINLINE(void) vmxHCReadGuestPhysicalAddrVmcs(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient) 1566 1590 { 1567 1591 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_GUEST_PHYSICAL_ADDR)) 1568 1592 { 1569 int rc = VMX ReadVmcs64(VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL, &pVmxTransient->uGuestPhysicalAddr);1593 int rc = VMX_VMCS_READ_64(pVCpu, VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL, &pVmxTransient->uGuestPhysicalAddr); 1570 1594 AssertRC(rc); 1571 1595 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_GUEST_PHYSICAL_ADDR; … … 1578 1602 * structure. 1579 1603 * 1604 * @param pVCpu The cross context virtual CPU structure. 1580 1605 * @param pVmxTransient The VMX-transient structure. 1581 1606 */ 1582 DECLINLINE(void) vmxHCReadGuestPendingDbgXctps(PVM XTRANSIENT pVmxTransient)1607 DECLINLINE(void) vmxHCReadGuestPendingDbgXctps(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient) 1583 1608 { 1584 1609 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_GUEST_PENDING_DBG_XCPTS)) 1585 1610 { 1586 int rc = VMX ReadVmcsNw(VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, &pVmxTransient->uGuestPendingDbgXcpts);1611 int rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, &pVmxTransient->uGuestPendingDbgXcpts); 1587 1612 AssertRC(rc); 1588 1613 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_GUEST_PENDING_DBG_XCPTS; … … 1595 1620 * transient structure. 1596 1621 * 1622 * @param pVCpu The cross context virtual CPU structure. 1597 1623 * @param pVmxTransient The VMX-transient structure. 1598 1624 * 1599 1625 * @remarks No-long-jump zone!!! 1600 1626 */ 1601 DECLINLINE(void) vmxHCReadIdtVectoringInfoVmcs(PVM XTRANSIENT pVmxTransient)1627 DECLINLINE(void) vmxHCReadIdtVectoringInfoVmcs(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient) 1602 1628 { 1603 1629 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_IDT_VECTORING_INFO)) 1604 1630 { 1605 int rc = VMX ReadVmcs32(VMX_VMCS32_RO_IDT_VECTORING_INFO, &pVmxTransient->uIdtVectoringInfo);1631 int rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_RO_IDT_VECTORING_INFO, &pVmxTransient->uIdtVectoringInfo); 1606 1632 AssertRC(rc); 1607 1633 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_IDT_VECTORING_INFO; … … 1614 1640 * transient structure. 1615 1641 * 1642 * @param pVCpu The cross context virtual CPU structure. 1616 1643 * @param pVmxTransient The VMX-transient structure. 1617 1644 */ 1618 DECLINLINE(void) vmxHCReadIdtVectoringErrorCodeVmcs(PVM XTRANSIENT pVmxTransient)1645 DECLINLINE(void) vmxHCReadIdtVectoringErrorCodeVmcs(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient) 1619 1646 { 1620 1647 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_IDT_VECTORING_ERROR_CODE)) 1621 1648 { 1622 int rc = VMX ReadVmcs32(VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE, &pVmxTransient->uIdtVectoringErrorCode);1649 int rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE, &pVmxTransient->uIdtVectoringErrorCode); 1623 1650 AssertRC(rc); 1624 1651 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_IDT_VECTORING_ERROR_CODE; … … 1630 1657 * Reads all relevant read-only VMCS fields into the VMX transient structure. 1631 1658 * 1659 * @param pVCpu The cross context virtual CPU structure. 1632 1660 * @param pVmxTransient The VMX-transient structure. 1633 1661 */ 1634 static void vmxHCReadAllRoFieldsVmcs(PVM XTRANSIENT pVmxTransient)1635 { 1636 int rc = VMX ReadVmcsNw(VMX_VMCS_RO_EXIT_QUALIFICATION, &pVmxTransient->uExitQual);1637 rc |= VMX ReadVmcs32(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &pVmxTransient->cbExitInstr);1638 rc |= VMX ReadVmcs32(VMX_VMCS32_RO_EXIT_INSTR_INFO, &pVmxTransient->ExitInstrInfo.u);1639 rc |= VMX ReadVmcs32(VMX_VMCS32_RO_IDT_VECTORING_INFO, &pVmxTransient->uIdtVectoringInfo);1640 rc |= VMX ReadVmcs32(VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE, &pVmxTransient->uIdtVectoringErrorCode);1641 rc |= VMX ReadVmcs32(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &pVmxTransient->uExitIntInfo);1642 rc |= VMX ReadVmcs32(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE, &pVmxTransient->uExitIntErrorCode);1643 rc |= VMX ReadVmcsNw(VMX_VMCS_RO_GUEST_LINEAR_ADDR, &pVmxTransient->uGuestLinearAddr);1644 rc |= VMX ReadVmcs64(VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL, &pVmxTransient->uGuestPhysicalAddr);1662 static void vmxHCReadAllRoFieldsVmcs(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient) 1663 { 1664 int rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_RO_EXIT_QUALIFICATION, &pVmxTransient->uExitQual); 1665 rc |= VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &pVmxTransient->cbExitInstr); 1666 rc |= VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_RO_EXIT_INSTR_INFO, &pVmxTransient->ExitInstrInfo.u); 1667 rc |= VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_RO_IDT_VECTORING_INFO, &pVmxTransient->uIdtVectoringInfo); 1668 rc |= VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE, &pVmxTransient->uIdtVectoringErrorCode); 1669 rc |= VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &pVmxTransient->uExitIntInfo); 1670 rc |= VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE, &pVmxTransient->uExitIntErrorCode); 1671 rc |= VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_RO_GUEST_LINEAR_ADDR, &pVmxTransient->uGuestLinearAddr); 1672 rc |= VMX_VMCS_READ_64(pVCpu, VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL, &pVmxTransient->uGuestPhysicalAddr); 1645 1673 AssertRC(rc); 1646 1674 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_EXIT_QUALIFICATION … … 1787 1815 if (pVmcsInfo->cEntryMsrLoad != cMsrs) 1788 1816 { 1789 int rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, cMsrs); AssertRC(rc);1790 rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, cMsrs); AssertRC(rc);1791 rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, cMsrs); AssertRC(rc);1817 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, cMsrs); AssertRC(rc); 1818 rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, cMsrs); AssertRC(rc); 1819 rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, cMsrs); AssertRC(rc); 1792 1820 pVmcsInfo->cEntryMsrLoad = cMsrs; 1793 1821 pVmcsInfo->cExitMsrStore = cMsrs; … … 2192 2220 2193 2221 uint32_t u32Val; 2194 int rc = VMX ReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val);2222 int rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_CTRL_ENTRY, &u32Val); 2195 2223 AssertRC(rc); 2196 2224 AssertMsgReturnStmt(pVmcsInfo->u32EntryCtls == u32Val, … … 2199 2227 VERR_VMX_VMCS_FIELD_CACHE_INVALID); 2200 2228 2201 rc = VMX ReadVmcs32(VMX_VMCS32_CTRL_EXIT, &u32Val);2229 rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_CTRL_EXIT, &u32Val); 2202 2230 AssertRC(rc); 2203 2231 AssertMsgReturnStmt(pVmcsInfo->u32ExitCtls == u32Val, … … 2206 2234 VERR_VMX_VMCS_FIELD_CACHE_INVALID); 2207 2235 2208 rc = VMX ReadVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, &u32Val);2236 rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_CTRL_PIN_EXEC, &u32Val); 2209 2237 AssertRC(rc); 2210 2238 AssertMsgReturnStmt(pVmcsInfo->u32PinCtls == u32Val, … … 2213 2241 VERR_VMX_VMCS_FIELD_CACHE_INVALID); 2214 2242 2215 rc = VMX ReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, &u32Val);2243 rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC, &u32Val); 2216 2244 AssertRC(rc); 2217 2245 AssertMsgReturnStmt(pVmcsInfo->u32ProcCtls == u32Val, … … 2222 2250 if (pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS) 2223 2251 { 2224 rc = VMX ReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, &u32Val);2252 rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC2, &u32Val); 2225 2253 AssertRC(rc); 2226 2254 AssertMsgReturnStmt(pVmcsInfo->u32ProcCtls2 == u32Val, … … 2233 2261 if (pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_TERTIARY_CTLS) 2234 2262 { 2235 rc = VMX ReadVmcs64(VMX_VMCS64_CTRL_PROC_EXEC3_FULL, &u64Val);2263 rc = VMX_VMCS_READ_64(pVCpu, VMX_VMCS64_CTRL_PROC_EXEC3_FULL, &u64Val); 2236 2264 AssertRC(rc); 2237 2265 AssertMsgReturnStmt(pVmcsInfo->u64ProcCtls3 == u64Val, … … 2241 2269 } 2242 2270 2243 rc = VMX ReadVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, &u32Val);2271 rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_CTRL_EXCEPTION_BITMAP, &u32Val); 2244 2272 AssertRC(rc); 2245 2273 AssertMsgReturnStmt(pVmcsInfo->u32XcptBitmap == u32Val, … … 2248 2276 VERR_VMX_VMCS_FIELD_CACHE_INVALID); 2249 2277 2250 rc = VMX ReadVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, &u64Val);2278 rc = VMX_VMCS_READ_64(pVCpu, VMX_VMCS64_CTRL_TSC_OFFSET_FULL, &u64Val); 2251 2279 AssertRC(rc); 2252 2280 AssertMsgReturnStmt(pVmcsInfo->u64TscOffset == u64Val, … … 2275 2303 uint64_t const uHostEferMsrCache = g_uHmVmxHostMsrEfer; 2276 2304 uint64_t uVmcsEferMsrVmcs; 2277 int rc = VMX ReadVmcs64(VMX_VMCS64_HOST_EFER_FULL, &uVmcsEferMsrVmcs);2305 int rc = VMX_VMCS_READ_64(pVCpu, VMX_VMCS64_HOST_EFER_FULL, &uVmcsEferMsrVmcs); 2278 2306 AssertRC(rc); 2279 2307 … … 2302 2330 uint32_t cExitStoreMsrs; 2303 2331 uint32_t cExitLoadMsrs; 2304 int rc = VMX ReadVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, &cEntryLoadMsrs); AssertRC(rc);2305 rc = VMX ReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, &cExitStoreMsrs); AssertRC(rc);2306 rc = VMX ReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, &cExitLoadMsrs); AssertRC(rc);2332 int rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, &cEntryLoadMsrs); AssertRC(rc); 2333 rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, &cExitStoreMsrs); AssertRC(rc); 2334 rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, &cExitLoadMsrs); AssertRC(rc); 2307 2335 2308 2336 /* Verify all the MSR counts are the same. */ … … 2614 2642 2615 2643 /* Update VMCS with the VPID. */ 2616 int rc = VMX WriteVmcs16(VMX_VMCS16_VPID, pVCpu->hmr0.s.uCurrentAsid);2644 int rc = VMX_VMCS_WRITE_16(pVCpu, VMX_VMCS16_VPID, pVCpu->hmr0.s.uCurrentAsid); 2617 2645 AssertRC(rc); 2618 2646 … … 2765 2793 ("Cpu[%u] pVCpu->uCurrentAsid=%u\n", pHostCpu->idCpu, pVCpu->hmr0.s.uCurrentAsid)); 2766 2794 2767 int rc = VMX WriteVmcs16(VMX_VMCS16_VPID, pVCpu->hmr0.s.uCurrentAsid);2795 int rc = VMX_VMCS_WRITE_16(pVCpu, VMX_VMCS16_VPID, pVCpu->hmr0.s.uCurrentAsid); 2768 2796 AssertRC(rc); 2769 2797 } … … 3147 3175 Assert(HCPhysVirtApic != NIL_RTHCPHYS); 3148 3176 Assert(!(HCPhysVirtApic & 0xfff)); /* Bits 11:0 MBZ. */ 3149 int rc = VMX WriteVmcs64(VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL, HCPhysVirtApic);3177 int rc = VMX_VMCS_WRITE_64(pVCpu, VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL, HCPhysVirtApic); 3150 3178 AssertRC(rc); 3151 3179 } … … 3162 3190 Assert(HCPhysMsrBitmap != NIL_RTHCPHYS); 3163 3191 Assert(!(HCPhysMsrBitmap & 0xfff)); /* Bits 11:0 MBZ. */ 3164 int rc = VMX WriteVmcs64(VMX_VMCS64_CTRL_MSR_BITMAP_FULL, HCPhysMsrBitmap);3192 int rc = VMX_VMCS_WRITE_64(pVCpu, VMX_VMCS64_CTRL_MSR_BITMAP_FULL, HCPhysMsrBitmap); 3165 3193 AssertRC(rc); 3166 3194 } … … 3177 3205 Assert(HCPhysApicAccess != NIL_RTHCPHYS); 3178 3206 Assert(!(HCPhysApicAccess & 0xfff)); /* Bits 11:0 MBZ. */ 3179 int rc = VMX WriteVmcs64(VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL, HCPhysApicAccess);3207 int rc = VMX_VMCS_WRITE_64(pVCpu, VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL, HCPhysApicAccess); 3180 3208 AssertRC(rc); 3181 3209 } … … 3193 3221 Assert(HCPhysVmreadBitmap != NIL_RTHCPHYS); 3194 3222 Assert(!(HCPhysVmreadBitmap & 0xfff)); /* Bits 11:0 MBZ. */ 3195 int rc = VMX WriteVmcs64(VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL, HCPhysVmreadBitmap);3223 int rc = VMX_VMCS_WRITE_64(pVCpu, VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL, HCPhysVmreadBitmap); 3196 3224 AssertRC(rc); 3197 3225 } … … 3208 3236 Assert(HCPhysVmwriteBitmap != NIL_RTHCPHYS); 3209 3237 Assert(!(HCPhysVmwriteBitmap & 0xfff)); /* Bits 11:0 MBZ. */ 3210 int rc = VMX WriteVmcs64(VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL, HCPhysVmwriteBitmap);3238 int rc = VMX_VMCS_WRITE_64(pVCpu, VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL, HCPhysVmwriteBitmap); 3211 3239 AssertRC(rc); 3212 3240 } … … 3235 3263 Assert(!(HCPhysHostMsrLoad & 0xf)); /* Bits 3:0 MBZ. */ 3236 3264 3237 int rc = VMX WriteVmcs64(VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL, HCPhysGuestMsrLoad); AssertRC(rc);3238 rc = VMX WriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL, HCPhysGuestMsrStore); AssertRC(rc);3239 rc = VMX WriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL, HCPhysHostMsrLoad); AssertRC(rc);3265 int rc = VMX_VMCS_WRITE_64(pVCpu, VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL, HCPhysGuestMsrLoad); AssertRC(rc); 3266 rc = VMX_VMCS_WRITE_64(pVCpu, VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL, HCPhysGuestMsrStore); AssertRC(rc); 3267 rc = VMX_VMCS_WRITE_64(pVCpu, VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL, HCPhysHostMsrLoad); AssertRC(rc); 3240 3268 return VINF_SUCCESS; 3241 3269 } … … 3358 3386 3359 3387 /* Commit it to the VMCS and update our cache. */ 3360 int rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, fVal);3388 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PIN_EXEC, fVal); 3361 3389 AssertRC(rc); 3362 3390 pVmcsInfo->u32PinCtls = fVal; … … 3437 3465 fVal |= VMX_PROC_CTLS2_PAUSE_LOOP_EXIT; 3438 3466 3439 int rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_PLE_GAP, pVM->hm.s.vmx.cPleGapTicks); AssertRC(rc);3440 rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_PLE_WINDOW, pVM->hm.s.vmx.cPleWindowTicks); AssertRC(rc);3467 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PLE_GAP, pVM->hm.s.vmx.cPleGapTicks); AssertRC(rc); 3468 rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PLE_WINDOW, pVM->hm.s.vmx.cPleWindowTicks); AssertRC(rc); 3441 3469 } 3442 3470 … … 3450 3478 3451 3479 /* Commit it to the VMCS and update our cache. */ 3452 int rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, fVal);3480 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC2, fVal); 3453 3481 AssertRC(rc); 3454 3482 pVmcsInfo->u32ProcCtls2 = fVal; … … 3535 3563 3536 3564 /* Commit it to the VMCS and update our cache. */ 3537 int rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, fVal);3565 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC, fVal); 3538 3566 AssertRC(rc); 3539 3567 pVmcsInfo->u32ProcCtls = fVal; … … 3580 3608 3581 3609 Assert(pVmcsInfo->u64VmcsLinkPtr == NIL_RTHCPHYS); 3582 int rc = VMX WriteVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, NIL_RTHCPHYS);3610 int rc = VMX_VMCS_WRITE_64(pVCpu, VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, NIL_RTHCPHYS); 3583 3611 AssertRC(rc); 3584 3612 … … 3589 3617 uint64_t const u64Cr4Mask = vmxHCGetFixedCr4Mask(pVCpu); 3590 3618 3591 rc = VMX WriteVmcsNw(VMX_VMCS_CTRL_CR0_MASK, u64Cr0Mask); AssertRC(rc);3592 rc = VMX WriteVmcsNw(VMX_VMCS_CTRL_CR4_MASK, u64Cr4Mask); AssertRC(rc);3619 rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_CTRL_CR0_MASK, u64Cr0Mask); AssertRC(rc); 3620 rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_CTRL_CR4_MASK, u64Cr4Mask); AssertRC(rc); 3593 3621 3594 3622 pVmcsInfo->u64Cr0Mask = u64Cr0Mask; … … 3597 3625 if (pVCpu->CTX_SUFF(pVM)->hmr0.s.vmx.fLbr) 3598 3626 { 3599 rc = VMX WriteVmcsNw(VMX_VMCS64_GUEST_DEBUGCTL_FULL, MSR_IA32_DEBUGCTL_LBR);3627 rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS64_GUEST_DEBUGCTL_FULL, MSR_IA32_DEBUGCTL_LBR); 3600 3628 AssertRC(rc); 3601 3629 } … … 3635 3663 3636 3664 /* Commit it to the VMCS. */ 3637 int rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, uXcptBitmap);3665 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_EXCEPTION_BITMAP, uXcptBitmap); 3638 3666 AssertRC(rc); 3639 3667 … … 3653 3681 { 3654 3682 Assert(pVmcsInfo->u64VmcsLinkPtr == NIL_RTHCPHYS); 3655 int rc = VMX WriteVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, NIL_RTHCPHYS);3683 int rc = VMX_VMCS_WRITE_64(pVCpu, VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, NIL_RTHCPHYS); 3656 3684 AssertRC(rc); 3657 3685 … … 3949 3977 if (pVmcsInfo->u32EntryCtls != fVal) 3950 3978 { 3951 int rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_ENTRY, fVal);3979 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_ENTRY, fVal); 3952 3980 AssertRC(rc); 3953 3981 pVmcsInfo->u32EntryCtls = fVal; … … 4027 4055 if (pVmcsInfo->u32ExitCtls != fVal) 4028 4056 { 4029 int rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_EXIT, fVal);4057 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_EXIT, fVal); 4030 4058 AssertRC(rc); 4031 4059 pVmcsInfo->u32ExitCtls = fVal; … … 4050 4078 Assert(pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW); 4051 4079 RT_NOREF(pVmcsInfo); 4052 int rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, u32TprThreshold);4080 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_TPR_THRESHOLD, u32TprThreshold); 4053 4081 AssertRC(rc); 4054 4082 } … … 4192 4220 if ( !pVmxTransient->fIsNestedGuest 4193 4221 && pVCpu->hm.s.fGIMTrapXcptUD) 4194 vmxHCAddXcptIntercept(pV mxTransient, X86_XCPT_UD);4222 vmxHCAddXcptIntercept(pVCpu, pVmxTransient, X86_XCPT_UD); 4195 4223 else 4196 4224 vmxHCRemoveXcptIntercept(pVCpu, pVmxTransient, X86_XCPT_UD); … … 4215 4243 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RIP); 4216 4244 4217 int rc = VMX WriteVmcsNw(VMX_VMCS_GUEST_RIP, pVCpu->cpum.GstCtx.rip);4245 int rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_GUEST_RIP, pVCpu->cpum.GstCtx.rip); 4218 4246 AssertRC(rc); 4219 4247 … … 4237 4265 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RSP); 4238 4266 4239 int rc = VMX WriteVmcsNw(VMX_VMCS_GUEST_RSP, pVCpu->cpum.GstCtx.rsp);4267 int rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_GUEST_RSP, pVCpu->cpum.GstCtx.rsp); 4240 4268 AssertRC(rc); 4241 4269 … … 4283 4311 } 4284 4312 4285 int rc = VMX WriteVmcsNw(VMX_VMCS_GUEST_RFLAGS, fEFlags.u32);4313 int rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_GUEST_RFLAGS, fEFlags.u32); 4286 4314 AssertRC(rc); 4287 4315 … … 4334 4362 uint32_t const uVmcsField = pVM->hmr0.s.vmx.paShadowVmcsFields[i]; 4335 4363 IEMReadVmxVmcsField(pVmcsNstGst, uVmcsField, &u64Val); 4336 VMX WriteVmcs64(uVmcsField, u64Val);4364 VMX_VMCS_WRITE_64(pVCpu, uVmcsField, u64Val); 4337 4365 } 4338 4366 … … 4349 4377 uint32_t const uVmcsField = pVM->hmr0.s.vmx.paShadowVmcsRoFields[i]; 4350 4378 IEMReadVmxVmcsField(pVmcsNstGst, uVmcsField, &u64Val); 4351 VMX WriteVmcs64(uVmcsField, u64Val);4379 VMX_VMCS_WRITE_64(pVCpu, uVmcsField, u64Val); 4352 4380 } 4353 4381 } … … 4393 4421 uint64_t u64Val; 4394 4422 uint32_t const uVmcsField = pVM->hmr0.s.vmx.paShadowVmcsFields[i]; 4395 VMX ReadVmcs64(uVmcsField, &u64Val);4423 VMX_VMCS_READ_64(pVCpu, uVmcsField, &u64Val); 4396 4424 IEMWriteVmxVmcsField(pVmcsNstGst, uVmcsField, u64Val); 4397 4425 } … … 4418 4446 Assert(pVmcsInfo->HCPhysShadowVmcs != 0 && pVmcsInfo->HCPhysShadowVmcs != NIL_RTHCPHYS); 4419 4447 uProcCtls2 |= VMX_PROC_CTLS2_VMCS_SHADOWING; 4420 int rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, uProcCtls2); AssertRC(rc);4421 rc = VMX WriteVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, pVmcsInfo->HCPhysShadowVmcs); AssertRC(rc);4448 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC2, uProcCtls2); AssertRC(rc); 4449 rc = VMX_VMCS_WRITE_64(pVCpu, VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, pVmcsInfo->HCPhysShadowVmcs); AssertRC(rc); 4422 4450 pVmcsInfo->u32ProcCtls2 = uProcCtls2; 4423 4451 pVmcsInfo->u64VmcsLinkPtr = pVmcsInfo->HCPhysShadowVmcs; … … 4449 4477 { 4450 4478 uProcCtls2 &= ~VMX_PROC_CTLS2_VMCS_SHADOWING; 4451 int rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, uProcCtls2); AssertRC(rc);4452 rc = VMX WriteVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, NIL_RTHCPHYS); AssertRC(rc);4479 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC2, uProcCtls2); AssertRC(rc); 4480 rc = VMX_VMCS_WRITE_64(pVCpu, VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, NIL_RTHCPHYS); AssertRC(rc); 4453 4481 pVmcsInfo->u32ProcCtls2 = uProcCtls2; 4454 4482 pVmcsInfo->u64VmcsLinkPtr = NIL_RTHCPHYS; … … 4641 4669 4642 4670 /* Commit the CR0 and related fields to the guest VMCS. */ 4643 int rc = VMX WriteVmcsNw(VMX_VMCS_GUEST_CR0, u64GuestCr0); AssertRC(rc);4644 rc = VMX WriteVmcsNw(VMX_VMCS_CTRL_CR0_READ_SHADOW, u64ShadowCr0); AssertRC(rc);4671 int rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_GUEST_CR0, u64GuestCr0); AssertRC(rc); 4672 rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_CTRL_CR0_READ_SHADOW, u64ShadowCr0); AssertRC(rc); 4645 4673 if (uProcCtls != pVmcsInfo->u32ProcCtls) 4646 4674 { 4647 rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, uProcCtls);4675 rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC, uProcCtls); 4648 4676 AssertRC(rc); 4649 4677 } 4650 4678 if (uXcptBitmap != pVmcsInfo->u32XcptBitmap) 4651 4679 { 4652 rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, uXcptBitmap);4680 rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_EXCEPTION_BITMAP, uXcptBitmap); 4653 4681 AssertRC(rc); 4654 4682 } … … 4681 4709 4682 4710 /* Commit the CR0 and CR0 read-shadow to the nested-guest VMCS. */ 4683 int rc = VMX WriteVmcsNw(VMX_VMCS_GUEST_CR0, u64GuestCr0); AssertRC(rc);4684 rc = VMX WriteVmcsNw(VMX_VMCS_CTRL_CR0_READ_SHADOW, u64ShadowCr0); AssertRC(rc);4711 int rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_GUEST_CR0, u64GuestCr0); AssertRC(rc); 4712 rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_CTRL_CR0_READ_SHADOW, u64ShadowCr0); AssertRC(rc); 4685 4713 4686 4714 Log4Func(("cr0=%#RX64 shadow=%#RX64 (set=%#RX64 zap=%#RX64)\n", u64GuestCr0, u64ShadowCr0, fSetCr0, fZapCr0)); … … 4747 4775 ("EPTP accessed/dirty bit not supported by CPU but set %#RX64\n", pVmcsInfo->HCPhysEPTP)); 4748 4776 4749 rc = VMX WriteVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, pVmcsInfo->HCPhysEPTP);4777 rc = VMX_VMCS_WRITE_64(pVCpu, VMX_VMCS64_CTRL_EPTP_FULL, pVmcsInfo->HCPhysEPTP); 4750 4778 AssertRC(rc); 4751 4779 … … 4758 4786 if (CPUMIsGuestInPAEModeEx(pCtx)) 4759 4787 { 4760 rc = VMX WriteVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, pCtx->aPaePdpes[0].u); AssertRC(rc);4761 rc = VMX WriteVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, pCtx->aPaePdpes[1].u); AssertRC(rc);4762 rc = VMX WriteVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, pCtx->aPaePdpes[2].u); AssertRC(rc);4763 rc = VMX WriteVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, pCtx->aPaePdpes[3].u); AssertRC(rc);4788 rc = VMX_VMCS_WRITE_64(pVCpu, VMX_VMCS64_GUEST_PDPTE0_FULL, pCtx->aPaePdpes[0].u); AssertRC(rc); 4789 rc = VMX_VMCS_WRITE_64(pVCpu, VMX_VMCS64_GUEST_PDPTE1_FULL, pCtx->aPaePdpes[1].u); AssertRC(rc); 4790 rc = VMX_VMCS_WRITE_64(pVCpu, VMX_VMCS64_GUEST_PDPTE2_FULL, pCtx->aPaePdpes[2].u); AssertRC(rc); 4791 rc = VMX_VMCS_WRITE_64(pVCpu, VMX_VMCS64_GUEST_PDPTE3_FULL, pCtx->aPaePdpes[3].u); AssertRC(rc); 4764 4792 } 4765 4793 … … 4798 4826 4799 4827 Log4Func(("guest_cr3=%#RX64 (GstN)\n", u64GuestCr3)); 4800 rc = VMX WriteVmcsNw(VMX_VMCS_GUEST_CR3, u64GuestCr3);4828 rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_GUEST_CR3, u64GuestCr3); 4801 4829 AssertRC(rc); 4802 4830 } … … 4808 4836 4809 4837 Log4Func(("guest_cr3=%#RX64 (HstN)\n", HCPhysGuestCr3)); 4810 rc = VMX WriteVmcsNw(VMX_VMCS_GUEST_CR3, HCPhysGuestCr3);4838 rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_GUEST_CR3, HCPhysGuestCr3); 4811 4839 AssertRC(rc); 4812 4840 } … … 4914 4942 4915 4943 /* Commit the CR4 and CR4 read-shadow to the guest VMCS. */ 4916 rc = VMX WriteVmcsNw(VMX_VMCS_GUEST_CR4, u64GuestCr4); AssertRC(rc);4917 rc = VMX WriteVmcsNw(VMX_VMCS_CTRL_CR4_READ_SHADOW, u64ShadowCr4); AssertRC(rc);4944 rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_GUEST_CR4, u64GuestCr4); AssertRC(rc); 4945 rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_CTRL_CR4_READ_SHADOW, u64ShadowCr4); AssertRC(rc); 4918 4946 4919 4947 /* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */ … … 4954 4982 if (pVmxTransient->fIsNestedGuest) 4955 4983 { 4956 int rc = VMX WriteVmcsNw(VMX_VMCS_GUEST_DR7, CPUMGetGuestDR7(pVCpu));4984 int rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_GUEST_DR7, CPUMGetGuestDR7(pVCpu)); 4957 4985 AssertRC(rc); 4958 4986 … … 5071 5099 if (uProcCtls != pVmcsInfo->u32ProcCtls) 5072 5100 { 5073 int rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, uProcCtls);5101 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC, uProcCtls); 5074 5102 AssertRC(rc); 5075 5103 pVmcsInfo->u32ProcCtls = uProcCtls; … … 5079 5107 * Update guest DR7. 5080 5108 */ 5081 int rc = VMX WriteVmcsNw(VMX_VMCS_GUEST_DR7, u64GuestDr7);5109 int rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_GUEST_DR7, u64GuestDr7); 5082 5110 AssertRC(rc); 5083 5111 … … 5094 5122 5095 5123 uint32_t fIntrState = 0; 5096 rc = VMX ReadVmcs32(VMX_VMCS32_GUEST_INT_STATE, &fIntrState);5124 rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_GUEST_INT_STATE, &fIntrState); 5097 5125 AssertRC(rc); 5098 5126 … … 5100 5128 { 5101 5129 fIntrState &= ~(VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS); 5102 rc = VMX WriteVmcs32(VMX_VMCS32_GUEST_INT_STATE, fIntrState);5130 rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_GUEST_INT_STATE, fIntrState); 5103 5131 AssertRC(rc); 5104 5132 } … … 5337 5365 Assert((uint32_t)VMX_VMCS32_GUEST_SEG_ACCESS_RIGHTS(iSegReg) == g_aVmcsSegAttr[iSegReg]); 5338 5366 Assert((uint32_t)VMX_VMCS_GUEST_SEG_BASE(iSegReg) == g_aVmcsSegBase[iSegReg]); 5339 int rc = VMX WriteVmcs32(VMX_VMCS16_GUEST_SEG_SEL(iSegReg), pSelReg->Sel); AssertRC(rc);5340 rc = VMX WriteVmcs32(VMX_VMCS32_GUEST_SEG_LIMIT(iSegReg), pSelReg->u32Limit); AssertRC(rc);5341 rc = VMX WriteVmcsNw(VMX_VMCS_GUEST_SEG_BASE(iSegReg), pSelReg->u64Base); AssertRC(rc);5342 rc = VMX WriteVmcs32(VMX_VMCS32_GUEST_SEG_ACCESS_RIGHTS(iSegReg), u32Access); AssertRC(rc);5367 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS16_GUEST_SEG_SEL(iSegReg), pSelReg->Sel); AssertRC(rc); 5368 rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_GUEST_SEG_LIMIT(iSegReg), pSelReg->u32Limit); AssertRC(rc); 5369 rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_GUEST_SEG_BASE(iSegReg), pSelReg->u64Base); AssertRC(rc); 5370 rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_GUEST_SEG_ACCESS_RIGHTS(iSegReg), u32Access); AssertRC(rc); 5343 5371 return VINF_SUCCESS; 5344 5372 } … … 5496 5524 || (u32AccessRights & RT_BIT(15))); /* Granularity MB1. */ 5497 5525 5498 rc = VMX WriteVmcs16(VMX_VMCS16_GUEST_TR_SEL, u16Sel); AssertRC(rc);5499 rc = VMX WriteVmcs32(VMX_VMCS32_GUEST_TR_LIMIT, u32Limit); AssertRC(rc);5500 rc = VMX WriteVmcs32(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, u32AccessRights); AssertRC(rc);5501 rc = VMX WriteVmcsNw(VMX_VMCS_GUEST_TR_BASE, u64Base); AssertRC(rc);5526 rc = VMX_VMCS_WRITE_16(pVCpu, VMX_VMCS16_GUEST_TR_SEL, u16Sel); AssertRC(rc); 5527 rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_GUEST_TR_LIMIT, u32Limit); AssertRC(rc); 5528 rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, u32AccessRights); AssertRC(rc); 5529 rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_GUEST_TR_BASE, u64Base); AssertRC(rc); 5502 5530 5503 5531 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_TR); … … 5512 5540 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_GDTR); 5513 5541 5514 rc = VMX WriteVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt); AssertRC(rc);5515 rc = VMX WriteVmcsNw(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt); AssertRC(rc);5542 rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt); AssertRC(rc); 5543 rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt); AssertRC(rc); 5516 5544 5517 5545 /* Validate. */ … … 5537 5565 u32Access = pCtx->ldtr.Attr.u; 5538 5566 5539 rc = VMX WriteVmcs16(VMX_VMCS16_GUEST_LDTR_SEL, pCtx->ldtr.Sel); AssertRC(rc);5540 rc = VMX WriteVmcs32(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtr.u32Limit); AssertRC(rc);5541 rc = VMX WriteVmcs32(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, u32Access); AssertRC(rc);5542 rc = VMX WriteVmcsNw(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtr.u64Base); AssertRC(rc);5567 rc = VMX_VMCS_WRITE_16(pVCpu, VMX_VMCS16_GUEST_LDTR_SEL, pCtx->ldtr.Sel); AssertRC(rc); 5568 rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtr.u32Limit); AssertRC(rc); 5569 rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, u32Access); AssertRC(rc); 5570 rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtr.u64Base); AssertRC(rc); 5543 5571 5544 5572 /* Validate. */ … … 5568 5596 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_IDTR); 5569 5597 5570 rc = VMX WriteVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt); AssertRC(rc);5571 rc = VMX WriteVmcsNw(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt); AssertRC(rc);5598 rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt); AssertRC(rc); 5599 rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt); AssertRC(rc); 5572 5600 5573 5601 /* Validate. */ … … 5636 5664 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SYSENTER_CS_MSR) 5637 5665 { 5638 int rc = VMX WriteVmcs32(VMX_VMCS32_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);5666 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_GUEST_SYSENTER_CS, pCtx->SysEnter.cs); 5639 5667 AssertRC(rc); 5640 5668 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_SYSENTER_CS_MSR); … … 5643 5671 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SYSENTER_EIP_MSR) 5644 5672 { 5645 int rc = VMX WriteVmcsNw(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);5673 int rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip); 5646 5674 AssertRC(rc); 5647 5675 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_SYSENTER_EIP_MSR); … … 5650 5678 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SYSENTER_ESP_MSR) 5651 5679 { 5652 int rc = VMX WriteVmcsNw(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);5680 int rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp); 5653 5681 AssertRC(rc); 5654 5682 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_SYSENTER_ESP_MSR); … … 5692 5720 if (g_fHmVmxSupportsVmcsEfer) 5693 5721 { 5694 int rc = VMX WriteVmcs64(VMX_VMCS64_GUEST_EFER_FULL, uGuestEferMsr);5722 int rc = VMX_VMCS_WRITE_64(pVCpu, VMX_VMCS64_GUEST_EFER_FULL, uGuestEferMsr); 5695 5723 AssertRC(rc); 5696 5724 } … … 5818 5846 case VERR_VMX_UNABLE_TO_START_VM: /* VMLAUNCH/VMRESUME itself failed. */ 5819 5847 { 5820 int rc = VMX ReadVmcs32(VMX_VMCS32_RO_EXIT_REASON, &pVCpu->hm.s.vmx.LastError.u32ExitReason);5821 rc |= VMX ReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &pVCpu->hm.s.vmx.LastError.u32InstrError);5848 int rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_RO_EXIT_REASON, &pVCpu->hm.s.vmx.LastError.u32ExitReason); 5849 rc |= VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_RO_VM_INSTR_ERROR, &pVCpu->hm.s.vmx.LastError.u32InstrError); 5822 5850 AssertRC(rc); 5823 vmxHCReadExitQualVmcs(pV mxTransient);5851 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 5824 5852 5825 5853 pVCpu->hm.s.vmx.LastError.idEnteredCpu = pVCpu->hmr0.s.idEnteredCpu; … … 5931 5959 { 5932 5960 uint16_t u16Val; 5933 rc = VMX ReadVmcs16(uVmcsField, &u16Val);5961 rc = VMX_VMCS_READ_16(pVCpu, uVmcsField, &u16Val); 5934 5962 AssertRC(rc); 5935 5963 Log4(("%-40s = %#RX16\n", s_aVmcsFields[i].pszName, u16Val)); … … 5957 5985 { 5958 5986 uint32_t u32Val; 5959 rc = VMX ReadVmcs32(uVmcsField, &u32Val);5987 rc = VMX_VMCS_READ_32(pVCpu, uVmcsField, &u32Val); 5960 5988 AssertRC(rc); 5961 5989 Log4(("%-40s = %#RX32\n", s_aVmcsFields[i].pszName, u32Val)); … … 5967 5995 { 5968 5996 uint64_t u64Val; 5969 rc = VMX ReadVmcs64(uVmcsField, &u64Val);5997 rc = VMX_VMCS_READ_64(pVCpu, uVmcsField, &u64Val); 5970 5998 AssertRC(rc); 5971 5999 Log4(("%-40s = %#RX64\n", s_aVmcsFields[i].pszName, u64Val)); … … 6057 6085 * after converting the timer value to the host. */ 6058 6086 uint32_t const cPreemptionTickCount = (uint32_t)RT_MIN(cTicksToDeadline, UINT32_MAX - 16); 6059 int rc = VMX WriteVmcs32(VMX_VMCS32_PREEMPT_TIMER_VALUE, cPreemptionTickCount);6087 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_PREEMPT_TIMER_VALUE, cPreemptionTickCount); 6060 6088 AssertRC(rc); 6061 6089 } … … 6079 6107 if (pVmxTransient->fIsNestedGuest) 6080 6108 uTscOffset = CPUMApplyNestedGuestTscOffset(pVCpu, uTscOffset); 6081 vmxHCSetTscOffsetVmcs(pV mcsInfo, uTscOffset);6109 vmxHCSetTscOffsetVmcs(pVCpu, pVmcsInfo, uTscOffset); 6082 6110 vmxHCRemoveProcCtlsVmcs(pVCpu, pVmxTransient, VMX_PROC_CTLS_RDTSC_EXIT); 6083 6111 } … … 6354 6382 6355 6383 uint16_t u16Sel; 6356 int rc = VMX ReadVmcs16(VMX_VMCS16_GUEST_SEG_SEL(iSegReg), &u16Sel); AssertRC(rc);6384 int rc = VMX_VMCS_READ_16(pVCpu, VMX_VMCS16_GUEST_SEG_SEL(iSegReg), &u16Sel); AssertRC(rc); 6357 6385 pSelReg->Sel = u16Sel; 6358 6386 pSelReg->ValidSel = u16Sel; 6359 6387 6360 rc = VMX ReadVmcs32(VMX_VMCS32_GUEST_SEG_LIMIT(iSegReg), &pSelReg->u32Limit); AssertRC(rc);6361 rc = VMX ReadVmcsNw(VMX_VMCS_GUEST_SEG_BASE(iSegReg), &pSelReg->u64Base); AssertRC(rc);6388 rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_GUEST_SEG_LIMIT(iSegReg), &pSelReg->u32Limit); AssertRC(rc); 6389 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_GUEST_SEG_BASE(iSegReg), &pSelReg->u64Base); AssertRC(rc); 6362 6390 6363 6391 uint32_t u32Attr; 6364 rc = VMX ReadVmcs32(VMX_VMCS32_GUEST_SEG_ACCESS_RIGHTS(iSegReg), &u32Attr); AssertRC(rc);6392 rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_GUEST_SEG_ACCESS_RIGHTS(iSegReg), &u32Attr); AssertRC(rc); 6365 6393 pSelReg->Attr.u = u32Attr; 6366 6394 if (u32Attr & X86DESCATTR_UNUSABLE) … … 6383 6411 uint64_t u64Base; 6384 6412 uint32_t u32Limit, u32Attr; 6385 int rc = VMX ReadVmcs16(VMX_VMCS16_GUEST_LDTR_SEL, &u16Sel); AssertRC(rc);6386 rc = VMX ReadVmcs32(VMX_VMCS32_GUEST_LDTR_LIMIT, &u32Limit); AssertRC(rc);6387 rc = VMX ReadVmcs32(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, &u32Attr); AssertRC(rc);6388 rc = VMX ReadVmcsNw(VMX_VMCS_GUEST_LDTR_BASE, &u64Base); AssertRC(rc);6413 int rc = VMX_VMCS_READ_16(pVCpu, VMX_VMCS16_GUEST_LDTR_SEL, &u16Sel); AssertRC(rc); 6414 rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_GUEST_LDTR_LIMIT, &u32Limit); AssertRC(rc); 6415 rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, &u32Attr); AssertRC(rc); 6416 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_GUEST_LDTR_BASE, &u64Base); AssertRC(rc); 6389 6417 6390 6418 pVCpu->cpum.GstCtx.ldtr.Sel = u16Sel; … … 6411 6439 uint64_t u64Base; 6412 6440 uint32_t u32Limit, u32Attr; 6413 int rc = VMX ReadVmcs16(VMX_VMCS16_GUEST_TR_SEL, &u16Sel); AssertRC(rc);6414 rc = VMX ReadVmcs32(VMX_VMCS32_GUEST_TR_LIMIT, &u32Limit); AssertRC(rc);6415 rc = VMX ReadVmcs32(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, &u32Attr); AssertRC(rc);6416 rc = VMX ReadVmcsNw(VMX_VMCS_GUEST_TR_BASE, &u64Base); AssertRC(rc);6441 int rc = VMX_VMCS_READ_16(pVCpu, VMX_VMCS16_GUEST_TR_SEL, &u16Sel); AssertRC(rc); 6442 rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_GUEST_TR_LIMIT, &u32Limit); AssertRC(rc); 6443 rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, &u32Attr); AssertRC(rc); 6444 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_GUEST_TR_BASE, &u64Base); AssertRC(rc); 6417 6445 6418 6446 pVCpu->cpum.GstCtx.tr.Sel = u16Sel; … … 6442 6470 if (pCtx->fExtrn & CPUMCTX_EXTRN_RIP) 6443 6471 { 6444 int rc = VMX ReadVmcsNw(VMX_VMCS_GUEST_RIP, &u64Val);6472 int rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_GUEST_RIP, &u64Val); 6445 6473 AssertRC(rc); 6446 6474 … … 6468 6496 { 6469 6497 uint64_t u64Val; 6470 int rc = VMX ReadVmcsNw(VMX_VMCS_GUEST_RFLAGS, &u64Val);6498 int rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_GUEST_RFLAGS, &u64Val); 6471 6499 AssertRC(rc); 6472 6500 … … 6498 6526 { 6499 6527 uint32_t u32Val; 6500 int rc = VMX ReadVmcs32(VMX_VMCS32_GUEST_INT_STATE, &u32Val); AssertRC(rc);6528 int rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_GUEST_INT_STATE, &u32Val); AssertRC(rc); 6501 6529 if (!u32Val) 6502 6530 { … … 6579 6607 if (fWhat & CPUMCTX_EXTRN_RSP) 6580 6608 { 6581 rc = VMX ReadVmcsNw(VMX_VMCS_GUEST_RSP, &pCtx->rsp);6609 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_GUEST_RSP, &pCtx->rsp); 6582 6610 AssertRC(rc); 6583 6611 } … … 6634 6662 if (fWhat & CPUMCTX_EXTRN_GDTR) 6635 6663 { 6636 rc = VMX ReadVmcsNw(VMX_VMCS_GUEST_GDTR_BASE, &pCtx->gdtr.pGdt); AssertRC(rc);6637 rc = VMX ReadVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, &u32Val); AssertRC(rc);6664 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_GUEST_GDTR_BASE, &pCtx->gdtr.pGdt); AssertRC(rc); 6665 rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_GUEST_GDTR_LIMIT, &u32Val); AssertRC(rc); 6638 6666 pCtx->gdtr.cbGdt = u32Val; 6639 6667 } … … 6642 6670 if (fWhat & CPUMCTX_EXTRN_IDTR) 6643 6671 { 6644 rc = VMX ReadVmcsNw(VMX_VMCS_GUEST_IDTR_BASE, &pCtx->idtr.pIdt); AssertRC(rc);6645 rc = VMX ReadVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, &u32Val); AssertRC(rc);6672 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_GUEST_IDTR_BASE, &pCtx->idtr.pIdt); AssertRC(rc); 6673 rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_GUEST_IDTR_LIMIT, &u32Val); AssertRC(rc); 6646 6674 pCtx->idtr.cbIdt = u32Val; 6647 6675 } … … 6661 6689 if (!pVCpu->hmr0.s.fUsingHyperDR7) 6662 6690 { 6663 rc = VMX ReadVmcsNw(VMX_VMCS_GUEST_DR7, &pCtx->dr[7]);6691 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_GUEST_DR7, &pCtx->dr[7]); 6664 6692 AssertRC(rc); 6665 6693 } … … 6668 6696 if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS) 6669 6697 { 6670 rc = VMX ReadVmcsNw(VMX_VMCS_GUEST_SYSENTER_EIP, &pCtx->SysEnter.eip); AssertRC(rc);6671 rc = VMX ReadVmcsNw(VMX_VMCS_GUEST_SYSENTER_ESP, &pCtx->SysEnter.esp); AssertRC(rc);6672 rc = VMX ReadVmcs32(VMX_VMCS32_GUEST_SYSENTER_CS, &u32Val); AssertRC(rc);6698 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_GUEST_SYSENTER_EIP, &pCtx->SysEnter.eip); AssertRC(rc); 6699 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_GUEST_SYSENTER_ESP, &pCtx->SysEnter.esp); AssertRC(rc); 6700 rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_GUEST_SYSENTER_CS, &u32Val); AssertRC(rc); 6673 6701 pCtx->SysEnter.cs = u32Val; 6674 6702 } … … 6748 6776 uint64_t u64Cr0; 6749 6777 uint64_t u64Shadow; 6750 rc = VMX ReadVmcsNw(VMX_VMCS_GUEST_CR0, &u64Cr0); AssertRC(rc);6751 rc = VMX ReadVmcsNw(VMX_VMCS_CTRL_CR0_READ_SHADOW, &u64Shadow); AssertRC(rc);6778 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_GUEST_CR0, &u64Cr0); AssertRC(rc); 6779 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_CTRL_CR0_READ_SHADOW, &u64Shadow); AssertRC(rc); 6752 6780 #ifndef VBOX_WITH_NESTED_HWVIRT_VMX 6753 6781 u64Cr0 = (u64Cr0 & ~pVmcsInfo->u64Cr0Mask) … … 6782 6810 uint64_t u64Cr4; 6783 6811 uint64_t u64Shadow; 6784 rc = VMX ReadVmcsNw(VMX_VMCS_GUEST_CR4, &u64Cr4); AssertRC(rc);6785 rc |= VMX ReadVmcsNw(VMX_VMCS_CTRL_CR4_READ_SHADOW, &u64Shadow); AssertRC(rc);6812 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_GUEST_CR4, &u64Cr4); AssertRC(rc); 6813 rc |= VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_CTRL_CR4_READ_SHADOW, &u64Shadow); AssertRC(rc); 6786 6814 #ifndef VBOX_WITH_NESTED_HWVIRT_VMX 6787 6815 u64Cr4 = (u64Cr4 & ~pVmcsInfo->u64Cr4Mask) … … 6818 6846 { 6819 6847 uint64_t u64Cr3; 6820 rc = VMX ReadVmcsNw(VMX_VMCS_GUEST_CR3, &u64Cr3); AssertRC(rc);6848 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_GUEST_CR3, &u64Cr3); AssertRC(rc); 6821 6849 if (pCtx->cr3 != u64Cr3) 6822 6850 { … … 6832 6860 { 6833 6861 X86PDPE aPaePdpes[4]; 6834 rc = VMX ReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &aPaePdpes[0].u); AssertRC(rc);6835 rc = VMX ReadVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, &aPaePdpes[1].u); AssertRC(rc);6836 rc = VMX ReadVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, &aPaePdpes[2].u); AssertRC(rc);6837 rc = VMX ReadVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, &aPaePdpes[3].u); AssertRC(rc);6862 rc = VMX_VMCS_READ_64(pVCpu, VMX_VMCS64_GUEST_PDPTE0_FULL, &aPaePdpes[0].u); AssertRC(rc); 6863 rc = VMX_VMCS_READ_64(pVCpu, VMX_VMCS64_GUEST_PDPTE1_FULL, &aPaePdpes[1].u); AssertRC(rc); 6864 rc = VMX_VMCS_READ_64(pVCpu, VMX_VMCS64_GUEST_PDPTE2_FULL, &aPaePdpes[2].u); AssertRC(rc); 6865 rc = VMX_VMCS_READ_64(pVCpu, VMX_VMCS64_GUEST_PDPTE3_FULL, &aPaePdpes[3].u); AssertRC(rc); 6838 6866 if (memcmp(&aPaePdpes[0], &pCtx->aPaePdpes[0], sizeof(aPaePdpes))) 6839 6867 { … … 7160 7188 { 7161 7189 pVmcsInfo->u32ProcCtls |= VMX_PROC_CTLS_INT_WINDOW_EXIT; 7162 int rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls);7190 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls); 7163 7191 AssertRC(rc); 7164 7192 } … … 7177 7205 { 7178 7206 pVmcsInfo->u32ProcCtls &= ~VMX_PROC_CTLS_INT_WINDOW_EXIT; 7179 int rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls);7207 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls); 7180 7208 AssertRC(rc); 7181 7209 } … … 7196 7224 { 7197 7225 pVmcsInfo->u32ProcCtls |= VMX_PROC_CTLS_NMI_WINDOW_EXIT; 7198 int rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls);7226 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls); 7199 7227 AssertRC(rc); 7200 7228 Log4Func(("Setup NMI-window exiting\n")); … … 7214 7242 { 7215 7243 pVmcsInfo->u32ProcCtls &= ~VMX_PROC_CTLS_NMI_WINDOW_EXIT; 7216 int rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls);7244 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls); 7217 7245 AssertRC(rc); 7218 7246 } … … 7441 7469 7442 7470 /* Clear the events from the VMCS. */ 7443 int rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, 0); AssertRC(rc);7444 rc = VMX WriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, 0); AssertRC(rc);7471 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, 0); AssertRC(rc); 7472 rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, 0); AssertRC(rc); 7445 7473 } 7446 7474 #ifdef VBOX_STRICT … … 7464 7492 uint32_t uExitReason; 7465 7493 uint32_t uEntryIntInfo; 7466 int rc = VMX ReadVmcs32(VMX_VMCS32_RO_EXIT_REASON, &uExitReason);7467 rc |= VMX ReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &uEntryIntInfo);7494 int rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_RO_EXIT_REASON, &uExitReason); 7495 rc |= VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &uEntryIntInfo); 7468 7496 AssertRC(rc); 7469 7497 AssertMsg(VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason) || !VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo), … … 7793 7821 * Inject the event into the VMCS. 7794 7822 */ 7795 int rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, u32IntInfo);7823 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, u32IntInfo); 7796 7824 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(u32IntInfo)) 7797 rc |= VMX WriteVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, u32ErrCode);7798 rc |= VMX WriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, cbInstr);7825 rc |= VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, u32ErrCode); 7826 rc |= VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, cbInstr); 7799 7827 AssertRC(rc); 7800 7828 … … 8066 8094 Assert(!DBGFIsStepping(pVCpu)); 8067 8095 uint8_t const fTrapFlag = !!(pVCpu->cpum.GstCtx.eflags.u32 & X86_EFL_TF); 8068 int rc = VMX WriteVmcsNw(VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, fTrapFlag << VMX_BF_VMCS_PENDING_DBG_XCPT_BS_SHIFT);8096 int rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, fTrapFlag << VMX_BF_VMCS_PENDING_DBG_XCPT_BS_SHIFT); 8069 8097 AssertRC(rc); 8070 8098 } … … 8088 8116 * pending debug exceptions as well as updates to the guest state from ring-3 (IEM). 8089 8117 */ 8090 int rc = VMX WriteVmcs32(VMX_VMCS32_GUEST_INT_STATE, fIntrState);8118 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_GUEST_INT_STATE, fIntrState); 8091 8119 AssertRC(rc); 8092 8120 … … 8340 8368 * VMCS value and avoids causing further confusion. 8341 8369 */ 8342 rc = VMX ReadVmcs32(VMX_VMCS32_GUEST_INT_STATE, &u32IntrState);8370 rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_GUEST_INT_STATE, &u32IntrState); 8343 8371 AssertRC(rc); 8344 8372 … … 8358 8386 8359 8387 uint64_t u64GuestCr0; 8360 rc = VMX ReadVmcsNw(VMX_VMCS_GUEST_CR0, &u64GuestCr0);8388 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_GUEST_CR0, &u64GuestCr0); 8361 8389 AssertRC(rc); 8362 8390 HMVMX_CHECK_BREAK((u64GuestCr0 & fSetCr0) == fSetCr0, VMX_IGS_CR0_FIXED1); … … 8375 8403 8376 8404 uint64_t u64GuestCr4; 8377 rc = VMX ReadVmcsNw(VMX_VMCS_GUEST_CR4, &u64GuestCr4);8405 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_GUEST_CR4, &u64GuestCr4); 8378 8406 AssertRC(rc); 8379 8407 HMVMX_CHECK_BREAK((u64GuestCr4 & fSetCr4) == fSetCr4, VMX_IGS_CR4_FIXED1); … … 8383 8411 * IA32_DEBUGCTL MSR. 8384 8412 */ 8385 rc = VMX ReadVmcs64(VMX_VMCS64_GUEST_DEBUGCTL_FULL, &u64Val);8413 rc = VMX_VMCS_READ_64(pVCpu, VMX_VMCS64_GUEST_DEBUGCTL_FULL, &u64Val); 8386 8414 AssertRC(rc); 8387 8415 if ( (pVmcsInfo->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG) … … 8393 8421 8394 8422 #ifdef VBOX_STRICT 8395 rc = VMX ReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val);8423 rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_CTRL_ENTRY, &u32Val); 8396 8424 AssertRC(rc); 8397 8425 Assert(u32Val == pVmcsInfo->u32EntryCtls); … … 8402 8430 * RIP and RFLAGS. 8403 8431 */ 8404 rc = VMX ReadVmcsNw(VMX_VMCS_GUEST_RIP, &u64Val);8432 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_GUEST_RIP, &u64Val); 8405 8433 AssertRC(rc); 8406 8434 /* pCtx->rip can be different than the one in the VMCS (e.g. run guest code and VM-exits that don't update it). */ … … 8414 8442 8415 8443 /* Flags in pCtx can be different (real-on-v86 for instance). We are only concerned about the VMCS contents here. */ 8416 rc = VMX ReadVmcsNw(VMX_VMCS_GUEST_RFLAGS, &u64Val);8444 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_GUEST_RFLAGS, &u64Val); 8417 8445 AssertRC(rc); 8418 8446 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffffffc08028)), /* Bit 63:22, Bit 15, 5, 3 MBZ. */ … … 8429 8457 8430 8458 uint32_t u32EntryInfo; 8431 rc = VMX ReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &u32EntryInfo);8459 rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &u32EntryInfo); 8432 8460 AssertRC(rc); 8433 8461 if (VMX_ENTRY_INT_INFO_IS_EXT_INT(u32EntryInfo)) … … 8454 8482 HMVMX_ERROR_BREAK(VMX_IGS_DR7_RESERVED); 8455 8483 8456 rc = VMX ReadVmcsNw(VMX_VMCS_HOST_SYSENTER_ESP, &u64Val);8484 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_HOST_SYSENTER_ESP, &u64Val); 8457 8485 AssertRC(rc); 8458 8486 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_SYSENTER_ESP_NOT_CANONICAL); 8459 8487 8460 rc = VMX ReadVmcsNw(VMX_VMCS_HOST_SYSENTER_EIP, &u64Val);8488 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_HOST_SYSENTER_EIP, &u64Val); 8461 8489 AssertRC(rc); 8462 8490 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_SYSENTER_EIP_NOT_CANONICAL); … … 8467 8495 if (pVmcsInfo->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR) 8468 8496 { 8469 rc = VMX ReadVmcs64(VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL, &u64Val);8497 rc = VMX_VMCS_READ_64(pVCpu, VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL, &u64Val); 8470 8498 AssertRC(rc); 8471 8499 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xfffffff8fffffffc)), … … 8478 8506 if (pVmcsInfo->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR) 8479 8507 { 8480 rc = VMX ReadVmcs64(VMX_VMCS64_GUEST_PAT_FULL, &u64Val);8508 rc = VMX_VMCS_READ_64(pVCpu, VMX_VMCS64_GUEST_PAT_FULL, &u64Val); 8481 8509 AssertRC(rc); 8482 8510 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0x707070707070707)), VMX_IGS_PAT_MSR_RESERVED); … … 8501 8529 { 8502 8530 Assert(g_fHmVmxSupportsVmcsEfer); 8503 rc = VMX ReadVmcs64(VMX_VMCS64_GUEST_EFER_FULL, &u64Val);8531 rc = VMX_VMCS_READ_64(pVCpu, VMX_VMCS64_GUEST_EFER_FULL, &u64Val); 8504 8532 AssertRC(rc); 8505 8533 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xfffffffffffff2fe)), … … 8721 8749 * GDTR and IDTR (64-bit capable checks). 8722 8750 */ 8723 rc = VMX ReadVmcsNw(VMX_VMCS_GUEST_GDTR_BASE, &u64Val);8751 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_GUEST_GDTR_BASE, &u64Val); 8724 8752 AssertRC(rc); 8725 8753 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_GDTR_BASE_NOT_CANONICAL); 8726 8754 8727 rc = VMX ReadVmcsNw(VMX_VMCS_GUEST_IDTR_BASE, &u64Val);8755 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_GUEST_IDTR_BASE, &u64Val); 8728 8756 AssertRC(rc); 8729 8757 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_IDTR_BASE_NOT_CANONICAL); 8730 8758 8731 rc = VMX ReadVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, &u32Val);8759 rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_GUEST_GDTR_LIMIT, &u32Val); 8732 8760 AssertRC(rc); 8733 8761 HMVMX_CHECK_BREAK(!(u32Val & 0xffff0000), VMX_IGS_GDTR_LIMIT_INVALID); /* Bits 31:16 MBZ. */ 8734 8762 8735 rc = VMX ReadVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, &u32Val);8763 rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_GUEST_IDTR_LIMIT, &u32Val); 8736 8764 AssertRC(rc); 8737 8765 HMVMX_CHECK_BREAK(!(u32Val & 0xffff0000), VMX_IGS_IDTR_LIMIT_INVALID); /* Bits 31:16 MBZ. */ … … 8742 8770 /* Activity State. */ 8743 8771 uint32_t u32ActivityState; 8744 rc = VMX ReadVmcs32(VMX_VMCS32_GUEST_ACTIVITY_STATE, &u32ActivityState);8772 rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_GUEST_ACTIVITY_STATE, &u32ActivityState); 8745 8773 AssertRC(rc); 8746 8774 HMVMX_CHECK_BREAK( !u32ActivityState … … 8792 8820 8793 8821 /* Pending debug exceptions. */ 8794 rc = VMX ReadVmcsNw(VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, &u64Val);8822 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, &u64Val); 8795 8823 AssertRC(rc); 8796 8824 /* Bits 63:15, Bit 13, Bits 11:4 MBZ. */ … … 8817 8845 8818 8846 /* VMCS link pointer. */ 8819 rc = VMX ReadVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, &u64Val);8847 rc = VMX_VMCS_READ_64(pVCpu, VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, &u64Val); 8820 8848 AssertRC(rc); 8821 8849 if (u64Val != UINT64_C(0xffffffffffffffff)) … … 8840 8868 && CPUMIsGuestInPAEModeEx(pCtx)) 8841 8869 { 8842 rc = VMX ReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &u64Val);8870 rc = VMX_VMCS_READ_64(pVCpu, VMX_VMCS64_GUEST_PDPTE0_FULL, &u64Val); 8843 8871 AssertRC(rc); 8844 8872 HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED); 8845 8873 8846 rc = VMX ReadVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, &u64Val);8874 rc = VMX_VMCS_READ_64(pVCpu, VMX_VMCS64_GUEST_PDPTE1_FULL, &u64Val); 8847 8875 AssertRC(rc); 8848 8876 HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED); 8849 8877 8850 rc = VMX ReadVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, &u64Val);8878 rc = VMX_VMCS_READ_64(pVCpu, VMX_VMCS64_GUEST_PDPTE2_FULL, &u64Val); 8851 8879 AssertRC(rc); 8852 8880 HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED); 8853 8881 8854 rc = VMX ReadVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, &u64Val);8882 rc = VMX_VMCS_READ_64(pVCpu, VMX_VMCS64_GUEST_PDPTE3_FULL, &u64Val); 8855 8883 AssertRC(rc); 8856 8884 HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED); … … 9263 9291 int rc = VINF_SUCCESS; 9264 9292 if (pVmcsInfoNstGst->u32PinCtls != u32PinCtls) 9265 rc |= VMX WriteVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, u32PinCtls);9293 rc |= VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PIN_EXEC, u32PinCtls); 9266 9294 if (pVmcsInfoNstGst->u32ProcCtls != u32ProcCtls) 9267 rc |= VMX WriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, u32ProcCtls);9295 rc |= VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC, u32ProcCtls); 9268 9296 if (pVmcsInfoNstGst->u32ProcCtls2 != u32ProcCtls2) 9269 rc |= VMX WriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, u32ProcCtls2);9297 rc |= VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC2, u32ProcCtls2); 9270 9298 if (pVmcsInfoNstGst->u32XcptBitmap != u32XcptBitmap) 9271 rc |= VMX WriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, u32XcptBitmap);9299 rc |= VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_EXCEPTION_BITMAP, u32XcptBitmap); 9272 9300 if (pVmcsInfoNstGst->u64Cr0Mask != u64Cr0Mask) 9273 rc |= VMX WriteVmcsNw(VMX_VMCS_CTRL_CR0_MASK, u64Cr0Mask);9301 rc |= VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_CTRL_CR0_MASK, u64Cr0Mask); 9274 9302 if (pVmcsInfoNstGst->u64Cr4Mask != u64Cr4Mask) 9275 rc |= VMX WriteVmcsNw(VMX_VMCS_CTRL_CR4_MASK, u64Cr4Mask);9303 rc |= VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_CTRL_CR4_MASK, u64Cr4Mask); 9276 9304 if (pVmcsInfoNstGst->u32XcptPFMask != u32XcptPFMask) 9277 rc |= VMX WriteVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, u32XcptPFMask);9305 rc |= VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, u32XcptPFMask); 9278 9306 if (pVmcsInfoNstGst->u32XcptPFMatch != u32XcptPFMatch) 9279 rc |= VMX WriteVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, u32XcptPFMatch);9307 rc |= VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, u32XcptPFMatch); 9280 9308 if ( !(u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT) 9281 9309 && (u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)) 9282 9310 { 9283 9311 Assert(g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT); 9284 rc |= VMX WriteVmcs32(VMX_VMCS32_CTRL_PLE_GAP, cPleGapTicks);9285 rc |= VMX WriteVmcs32(VMX_VMCS32_CTRL_PLE_WINDOW, cPleWindowTicks);9312 rc |= VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PLE_GAP, cPleGapTicks); 9313 rc |= VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PLE_WINDOW, cPleWindowTicks); 9286 9314 } 9287 9315 if (u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW) 9288 9316 { 9289 rc |= VMX WriteVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, u32TprThreshold);9290 rc |= VMX WriteVmcs64(VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL, HCPhysVirtApic);9317 rc |= VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_TPR_THRESHOLD, u32TprThreshold); 9318 rc |= VMX_VMCS_WRITE_64(pVCpu, VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL, HCPhysVirtApic); 9291 9319 } 9292 9320 if (u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS) 9293 rc |= VMX WriteVmcs64(VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL, HCPhysApicAccess);9294 rc |= VMX WriteVmcsNw(VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, uPendingDbgXcpts);9321 rc |= VMX_VMCS_WRITE_64(pVCpu, VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL, HCPhysApicAccess); 9322 rc |= VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, uPendingDbgXcpts); 9295 9323 AssertRC(rc); 9296 9324 … … 9807 9835 */ 9808 9836 uint32_t uExitReason; 9809 int rc = VMX ReadVmcs32(VMX_VMCS32_RO_EXIT_REASON, &uExitReason);9837 int rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_RO_EXIT_REASON, &uExitReason); 9810 9838 AssertRC(rc); 9811 9839 pVmxTransient->uExitReason = VMX_EXIT_REASON_BASIC(uExitReason); … … 9860 9888 9861 9889 #ifdef HMVMX_ALWAYS_SAVE_RO_GUEST_STATE 9862 vmxHCReadAllRoFieldsVmcs(pV mxTransient);9890 vmxHCReadAllRoFieldsVmcs(pVCpu, pVmxTransient); 9863 9891 #endif 9864 9892 … … 10261 10289 pVmcsInfo->u32ProcCtls |= pDbgState->fCpe1Extra; 10262 10290 pVmcsInfo->u32ProcCtls &= ~pDbgState->fCpe1Unwanted; 10263 VMX WriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls);10291 VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls); 10264 10292 Log6Func(("VMX_VMCS32_CTRL_PROC_EXEC: %#RX32\n", pVmcsInfo->u32ProcCtls)); 10265 10293 pDbgState->fModifiedProcCtls = true; … … 10269 10297 { 10270 10298 pVmcsInfo->u32ProcCtls2 |= pDbgState->fCpe2Extra; 10271 VMX WriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, pVmcsInfo->u32ProcCtls2);10299 VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC2, pVmcsInfo->u32ProcCtls2); 10272 10300 Log6Func(("VMX_VMCS32_CTRL_PROC_EXEC2: %#RX32\n", pVmcsInfo->u32ProcCtls2)); 10273 10301 pDbgState->fModifiedProcCtls2 = true; … … 10277 10305 { 10278 10306 pVmcsInfo->u32XcptBitmap |= pDbgState->bmXcptExtra; 10279 VMX WriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVmcsInfo->u32XcptBitmap);10307 VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVmcsInfo->u32XcptBitmap); 10280 10308 Log6Func(("VMX_VMCS32_CTRL_EXCEPTION_BITMAP: %#RX32\n", pVmcsInfo->u32XcptBitmap)); 10281 10309 pDbgState->fModifiedXcptBitmap = true; … … 10285 10313 { 10286 10314 pVmcsInfo->u64Cr0Mask = 0; 10287 VMX WriteVmcsNw(VMX_VMCS_CTRL_CR0_MASK, 0);10315 VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_CTRL_CR0_MASK, 0); 10288 10316 Log6Func(("VMX_VMCS_CTRL_CR0_MASK: 0\n")); 10289 10317 } … … 10292 10320 { 10293 10321 pVmcsInfo->u64Cr4Mask = 0; 10294 VMX WriteVmcsNw(VMX_VMCS_CTRL_CR4_MASK, 0);10322 VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_CTRL_CR4_MASK, 0); 10295 10323 Log6Func(("VMX_VMCS_CTRL_CR4_MASK: 0\n")); 10296 10324 } … … 10326 10354 if (!(pDbgState->fProcCtlsInitial & VMX_PROC_CTLS_MOV_DR_EXIT) && CPUMIsHyperDebugStateActive(pVCpu)) 10327 10355 pDbgState->fProcCtlsInitial |= VMX_PROC_CTLS_MOV_DR_EXIT; /* Avoid assertion in vmxHCLeave */ 10328 int rc2 = VMX WriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pDbgState->fProcCtlsInitial);10356 int rc2 = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC, pDbgState->fProcCtlsInitial); 10329 10357 AssertRC(rc2); 10330 10358 pVmcsInfo->u32ProcCtls = pDbgState->fProcCtlsInitial; … … 10336 10364 && pVmcsInfo->u32ProcCtls2 != pDbgState->fProcCtls2Initial) 10337 10365 { 10338 int rc2 = VMX WriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, pDbgState->fProcCtls2Initial);10366 int rc2 = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC2, pDbgState->fProcCtls2Initial); 10339 10367 AssertRC(rc2); 10340 10368 pVmcsInfo->u32ProcCtls2 = pDbgState->fProcCtls2Initial; … … 10703 10731 if (VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(pVmxTransient->uExitIntInfo)) 10704 10732 { 10705 vmxHCReadExitIntErrorCodeVmcs(pV mxTransient);10733 vmxHCReadExitIntErrorCodeVmcs(pVCpu, pVmxTransient); 10706 10734 uEventArg = pVmxTransient->uExitIntErrorCode; 10707 10735 } … … 10773 10801 case VMX_EXIT_VMXON: SET_BOTH(VMX_VMXON); break; 10774 10802 case VMX_EXIT_MOV_CRX: 10775 vmxHCReadExitQualVmcs(pV mxTransient);10803 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 10776 10804 if (VMX_EXIT_QUAL_CRX_ACCESS(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_CRX_ACCESS_READ) 10777 10805 SET_BOTH(CRX_READ); … … 10781 10809 break; 10782 10810 case VMX_EXIT_MOV_DRX: 10783 vmxHCReadExitQualVmcs(pV mxTransient);10811 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 10784 10812 if ( VMX_EXIT_QUAL_DRX_DIRECTION(pVmxTransient->uExitQual) 10785 10813 == VMX_EXIT_QUAL_DRX_DIRECTION_READ) … … 10795 10823 case VMX_EXIT_PAUSE: SET_BOTH(PAUSE); break; 10796 10824 case VMX_EXIT_GDTR_IDTR_ACCESS: 10797 vmxHCReadExitInstrInfoVmcs(pV mxTransient);10825 vmxHCReadExitInstrInfoVmcs(pVCpu, pVmxTransient); 10798 10826 switch (RT_BF_GET(pVmxTransient->ExitInstrInfo.u, VMX_BF_XDTR_INSINFO_INSTR_ID)) 10799 10827 { … … 10806 10834 10807 10835 case VMX_EXIT_LDTR_TR_ACCESS: 10808 vmxHCReadExitInstrInfoVmcs(pV mxTransient);10836 vmxHCReadExitInstrInfoVmcs(pVCpu, pVmxTransient); 10809 10837 switch (RT_BF_GET(pVmxTransient->ExitInstrInfo.u, VMX_BF_YYTR_INSINFO_INSTR_ID)) 10810 10838 { … … 10864 10892 if (fDtrace1 || fDtrace2) 10865 10893 { 10866 vmxHCReadExitQualVmcs(pV mxTransient);10894 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 10867 10895 vmxHCImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, HMVMX_CPUMCTX_EXTRN_ALL); 10868 10896 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx; … … 11051 11079 else 11052 11080 { 11053 vmxHCReadExitQualVmcs(pV mxTransient);11081 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 11054 11082 int rc = vmxHCImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, HMVMX_CPUMCTX_EXTRN_ALL); 11055 11083 AssertRC(rc); … … 11064 11092 else 11065 11093 { 11066 vmxHCReadExitIntInfoVmcs(pV mxTransient);11094 vmxHCReadExitIntInfoVmcs(pVCpu, pVmxTransient); 11067 11095 uint32_t const uIntType = VMX_EXIT_INT_INFO_TYPE(pVmxTransient->uExitIntInfo); 11068 11096 if (uIntType == VMX_EXIT_INT_INFO_TYPE_NMI) … … 11725 11753 static int vmxHCAdvanceGuestRip(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient) 11726 11754 { 11727 vmxHCReadExitInstrLenVmcs(pV mxTransient);11755 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 11728 11756 int rc = vmxHCImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS); 11729 11757 AssertRCReturn(rc, rc); … … 12368 12396 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient); 12369 12397 PVMCC pVM = pVCpu->CTX_SUFF(pVM); 12370 vmxHCReadExitQualVmcs(pV mxTransient);12398 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 12371 12399 12372 12400 if (!pVM->hmr0.s.fNestedPaging) … … 12636 12664 * Get the DR6-like values from the Exit qualification and pass it to DBGF for processing. 12637 12665 */ 12638 vmxHCReadExitQualVmcs(pV mxTransient);12666 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 12639 12667 12640 12668 /* Refer Intel spec. Table 27-1. "Exit Qualifications for debug exceptions" for the format. */ … … 12692 12720 pCtx->dr[7] |= X86_DR7_RA1_MASK; 12693 12721 12694 rc = VMX WriteVmcsNw(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);12722 rc = VMX_VMCS_WRITE_NW(pVCpu, VMX_VMCS_GUEST_DR7, pCtx->dr[7]); 12695 12723 AssertRC(rc); 12696 12724 … … 13023 13051 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitXcptNmi, y3); 13024 13052 13025 vmxHCReadExitIntInfoVmcs(pV mxTransient);13053 vmxHCReadExitIntInfoVmcs(pVCpu, pVmxTransient); 13026 13054 13027 13055 uint32_t const uExitIntType = VMX_EXIT_INT_INFO_TYPE(pVmxTransient->uExitIntInfo); … … 13067 13095 { 13068 13096 NOREF(uVector); 13069 vmxHCReadExitIntErrorCodeVmcs(pV mxTransient);13070 vmxHCReadExitInstrLenVmcs(pV mxTransient);13071 vmxHCReadIdtVectoringInfoVmcs(pV mxTransient);13072 vmxHCReadIdtVectoringErrorCodeVmcs(pV mxTransient);13097 vmxHCReadExitIntErrorCodeVmcs(pVCpu, pVmxTransient); 13098 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 13099 vmxHCReadIdtVectoringInfoVmcs(pVCpu, pVmxTransient); 13100 vmxHCReadIdtVectoringErrorCodeVmcs(pVCpu, pVmxTransient); 13073 13101 13074 13102 rcStrict = vmxHCExitXcpt(pVCpu, pVmxTransient); … … 13128 13156 */ 13129 13157 uint32_t fIntrState; 13130 int rc = VMX ReadVmcs32(VMX_VMCS32_GUEST_INT_STATE, &fIntrState);13158 int rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_GUEST_INT_STATE, &fIntrState); 13131 13159 AssertRC(rc); 13132 13160 Assert(!(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)); … … 13137 13165 13138 13166 fIntrState &= ~VMX_VMCS_GUEST_INT_STATE_BLOCK_STI; 13139 rc = VMX WriteVmcs32(VMX_VMCS32_GUEST_INT_STATE, fIntrState);13167 rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_GUEST_INT_STATE, fIntrState); 13140 13168 AssertRC(rc); 13141 13169 } … … 13180 13208 */ 13181 13209 PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo; 13182 vmxHCReadExitInstrLenVmcs(pV mxTransient);13210 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 13183 13211 13184 13212 int rc = vmxHCImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK); … … 13252 13280 13253 13281 PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo; 13254 vmxHCReadExitInstrLenVmcs(pV mxTransient);13282 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 13255 13283 int rc = vmxHCImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_MUST_MASK); 13256 13284 AssertRCReturn(rc, rc); … … 13282 13310 13283 13311 PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo; 13284 vmxHCReadExitInstrLenVmcs(pV mxTransient);13312 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 13285 13313 int rc = vmxHCImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_MUST_MASK | CPUMCTX_EXTRN_TSC_AUX); 13286 13314 AssertRCReturn(rc, rc); … … 13385 13413 13386 13414 PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo; 13387 vmxHCReadExitQualVmcs(pV mxTransient);13388 vmxHCReadExitInstrLenVmcs(pV mxTransient);13415 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 13416 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 13389 13417 int rc = vmxHCImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK); 13390 13418 AssertRCReturn(rc, rc); … … 13414 13442 13415 13443 PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo; 13416 vmxHCReadExitInstrLenVmcs(pV mxTransient);13444 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 13417 13445 int rc = vmxHCImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_DS); 13418 13446 AssertRCReturn(rc, rc); … … 13439 13467 13440 13468 PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo; 13441 vmxHCReadExitInstrLenVmcs(pV mxTransient);13469 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 13442 13470 int rc = vmxHCImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK); 13443 13471 AssertRCReturn(rc, rc); … … 13527 13555 13528 13556 PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo; 13529 vmxHCReadExitInstrLenVmcs(pV mxTransient);13557 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 13530 13558 int rc = vmxHCImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_MUST_MASK | CPUMCTX_EXTRN_CR4); 13531 13559 AssertRCReturn(rc, rc); … … 13558 13586 return VERR_EM_INTERPRETER; 13559 13587 #else 13560 vmxHCReadExitInstrLenVmcs(pV mxTransient);13561 vmxHCReadExitInstrInfoVmcs(pV mxTransient);13562 vmxHCReadExitQualVmcs(pV mxTransient);13588 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 13589 vmxHCReadExitInstrInfoVmcs(pVCpu, pVmxTransient); 13590 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 13563 13591 int rc = vmxHCImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SREG_MASK 13564 13592 | IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK); … … 13610 13638 uint32_t fIntrState; 13611 13639 uint64_t u64Val; 13612 vmxHCReadEntryIntInfoVmcs(pV mxTransient);13613 vmxHCReadEntryXcptErrorCodeVmcs(pV mxTransient);13614 vmxHCReadEntryInstrLenVmcs(pV mxTransient);13640 vmxHCReadEntryIntInfoVmcs(pVCpu, pVmxTransient); 13641 vmxHCReadEntryXcptErrorCodeVmcs(pVCpu, pVmxTransient); 13642 vmxHCReadEntryInstrLenVmcs(pVCpu, pVmxTransient); 13615 13643 13616 13644 Log4(("uInvalidReason %u\n", uInvalidReason)); … … 13619 13647 Log4(("VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH %#RX32\n", pVmxTransient->cbEntryInstr)); 13620 13648 13621 rc = VMX ReadVmcs32(VMX_VMCS32_GUEST_INT_STATE, &fIntrState); AssertRC(rc);13649 rc = VMX_VMCS_READ_32(pVCpu, VMX_VMCS32_GUEST_INT_STATE, &fIntrState); AssertRC(rc); 13622 13650 Log4(("VMX_VMCS32_GUEST_INT_STATE %#RX32\n", fIntrState)); 13623 rc = VMX ReadVmcsNw(VMX_VMCS_GUEST_CR0, &u64Val); AssertRC(rc);13651 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_GUEST_CR0, &u64Val); AssertRC(rc); 13624 13652 Log4(("VMX_VMCS_GUEST_CR0 %#RX64\n", u64Val)); 13625 rc = VMX ReadVmcsNw(VMX_VMCS_CTRL_CR0_MASK, &u64Val); AssertRC(rc);13653 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_CTRL_CR0_MASK, &u64Val); AssertRC(rc); 13626 13654 Log4(("VMX_VMCS_CTRL_CR0_MASK %#RX64\n", u64Val)); 13627 rc = VMX ReadVmcsNw(VMX_VMCS_CTRL_CR0_READ_SHADOW, &u64Val); AssertRC(rc);13655 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_CTRL_CR0_READ_SHADOW, &u64Val); AssertRC(rc); 13628 13656 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RX64\n", u64Val)); 13629 rc = VMX ReadVmcsNw(VMX_VMCS_CTRL_CR4_MASK, &u64Val); AssertRC(rc);13657 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_CTRL_CR4_MASK, &u64Val); AssertRC(rc); 13630 13658 Log4(("VMX_VMCS_CTRL_CR4_MASK %#RX64\n", u64Val)); 13631 rc = VMX ReadVmcsNw(VMX_VMCS_CTRL_CR4_READ_SHADOW, &u64Val); AssertRC(rc);13659 rc = VMX_VMCS_READ_NW(pVCpu, VMX_VMCS_CTRL_CR4_READ_SHADOW, &u64Val); AssertRC(rc); 13632 13660 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RX64\n", u64Val)); 13633 13661 if (pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging) 13634 13662 { 13635 rc = VMX ReadVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, &u64Val); AssertRC(rc);13663 rc = VMX_VMCS_READ_64(pVCpu, VMX_VMCS64_CTRL_EPTP_FULL, &u64Val); AssertRC(rc); 13636 13664 Log4(("VMX_VMCS64_CTRL_EPTP_FULL %#RX64\n", u64Val)); 13637 13665 } … … 13750 13778 } 13751 13779 13752 vmxHCReadExitInstrLenVmcs(pV mxTransient);13780 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 13753 13781 int rc = vmxHCImportGuestState(pVCpu, pVmcsInfo, fImport); 13754 13782 AssertRCReturn(rc, rc); … … 13823 13851 13824 13852 PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo; 13825 vmxHCReadExitInstrLenVmcs(pV mxTransient);13853 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 13826 13854 int rc = vmxHCImportGuestState(pVCpu, pVmcsInfo, fImport); 13827 13855 AssertRCReturn(rc, rc); … … 13992 14020 13993 14021 PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo; 13994 vmxHCReadExitQualVmcs(pV mxTransient);13995 vmxHCReadExitInstrLenVmcs(pV mxTransient);14022 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 14023 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 13996 14024 13997 14025 VBOXSTRICTRC rcStrict; … … 14112 14140 if (fMemOperand) 14113 14141 { 14114 vmxHCReadGuestLinearAddrVmcs(pV mxTransient);14142 vmxHCReadGuestLinearAddrVmcs(pVCpu, pVmxTransient); 14115 14143 GCPtrEffDst = pVmxTransient->uGuestLinearAddr; 14116 14144 } … … 14149 14177 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx; 14150 14178 PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo; 14151 vmxHCReadExitQualVmcs(pV mxTransient);14152 vmxHCReadExitInstrLenVmcs(pV mxTransient);14179 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 14180 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 14153 14181 int rc = vmxHCImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_MUST_MASK | CPUMCTX_EXTRN_SREG_MASK 14154 14182 | CPUMCTX_EXTRN_EFER); … … 14203 14231 if (fInsOutsInfo) 14204 14232 { 14205 vmxHCReadExitInstrInfoVmcs(pV mxTransient);14233 vmxHCReadExitInstrInfoVmcs(pVCpu, pVmxTransient); 14206 14234 AssertReturn(pVmxTransient->ExitInstrInfo.StrIo.u3AddrSize <= 2, VERR_VMX_IPE_3); 14207 14235 AssertCompile(IEMMODE_16BIT == 0 && IEMMODE_32BIT == 1 && IEMMODE_64BIT == 2); … … 14382 14410 14383 14411 /* Check if this task-switch occurred while delivery an event through the guest IDT. */ 14384 vmxHCReadExitQualVmcs(pV mxTransient);14412 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 14385 14413 if (VMX_EXIT_QUAL_TASK_SWITCH_TYPE(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT) 14386 14414 { 14387 vmxHCReadIdtVectoringInfoVmcs(pV mxTransient);14415 vmxHCReadIdtVectoringInfoVmcs(pVCpu, pVmxTransient); 14388 14416 if (VMX_IDT_VECTORING_INFO_IS_VALID(pVmxTransient->uIdtVectoringInfo)) 14389 14417 { … … 14391 14419 if (VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(pVmxTransient->uIdtVectoringInfo)) 14392 14420 { 14393 vmxHCReadIdtVectoringErrorCodeVmcs(pV mxTransient);14421 vmxHCReadIdtVectoringErrorCodeVmcs(pVCpu, pVmxTransient); 14394 14422 uErrCode = pVmxTransient->uIdtVectoringErrorCode; 14395 14423 } … … 14403 14431 GCPtrFaultAddress = 0; 14404 14432 14405 vmxHCReadExitInstrLenVmcs(pV mxTransient);14433 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 14406 14434 14407 14435 vmxHCSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(pVmxTransient->uIdtVectoringInfo), … … 14430 14458 PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo; 14431 14459 pVmcsInfo->u32ProcCtls &= ~VMX_PROC_CTLS_MONITOR_TRAP_FLAG; 14432 int rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls);14460 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls); 14433 14461 AssertRC(rc); 14434 14462 return VINF_EM_DBG_STEPPED; … … 14444 14472 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitApicAccess); 14445 14473 14446 vmxHCReadExitIntInfoVmcs(pV mxTransient);14447 vmxHCReadExitIntErrorCodeVmcs(pV mxTransient);14448 vmxHCReadExitInstrLenVmcs(pV mxTransient);14449 vmxHCReadIdtVectoringInfoVmcs(pV mxTransient);14450 vmxHCReadIdtVectoringErrorCodeVmcs(pV mxTransient);14474 vmxHCReadExitIntInfoVmcs(pVCpu, pVmxTransient); 14475 vmxHCReadExitIntErrorCodeVmcs(pVCpu, pVmxTransient); 14476 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 14477 vmxHCReadIdtVectoringInfoVmcs(pVCpu, pVmxTransient); 14478 vmxHCReadIdtVectoringErrorCodeVmcs(pVCpu, pVmxTransient); 14451 14479 14452 14480 /* … … 14471 14499 /* IOMMIOPhysHandler() below may call into IEM, save the necessary state. */ 14472 14500 PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo; 14473 vmxHCReadExitQualVmcs(pV mxTransient);14501 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 14474 14502 int rc = vmxHCImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_MUST_MASK); 14475 14503 AssertRCReturn(rc, rc); … … 14551 14579 /* Don't intercept MOV DRx any more. */ 14552 14580 pVmcsInfo->u32ProcCtls &= ~VMX_PROC_CTLS_MOV_DR_EXIT; 14553 int rc = VMX WriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls);14581 int rc = VMX_VMCS_WRITE_32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls); 14554 14582 AssertRC(rc); 14555 14583 … … 14566 14594 14567 14595 #ifdef VBOX_WITH_STATISTICS 14568 vmxHCReadExitQualVmcs(pV mxTransient);14596 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 14569 14597 if (VMX_EXIT_QUAL_DRX_DIRECTION(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_DRX_DIRECTION_WRITE) 14570 14598 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite); … … 14583 14611 */ 14584 14612 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx; 14585 vmxHCReadExitQualVmcs(pV mxTransient);14613 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 14586 14614 int rc = vmxHCImportGuestState(pVCpu, pVmcsInfo, CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_DR7); 14587 14615 AssertRCReturn(rc, rc); … … 14626 14654 Assert(pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging); 14627 14655 14628 vmxHCReadExitIntInfoVmcs(pV mxTransient);14629 vmxHCReadExitIntErrorCodeVmcs(pV mxTransient);14630 vmxHCReadExitInstrLenVmcs(pV mxTransient);14631 vmxHCReadIdtVectoringInfoVmcs(pV mxTransient);14632 vmxHCReadIdtVectoringErrorCodeVmcs(pV mxTransient);14656 vmxHCReadExitIntInfoVmcs(pVCpu, pVmxTransient); 14657 vmxHCReadExitIntErrorCodeVmcs(pVCpu, pVmxTransient); 14658 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 14659 vmxHCReadIdtVectoringInfoVmcs(pVCpu, pVmxTransient); 14660 vmxHCReadIdtVectoringErrorCodeVmcs(pVCpu, pVmxTransient); 14633 14661 14634 14662 /* … … 14666 14694 */ 14667 14695 PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo; 14668 vmxHCReadGuestPhysicalAddrVmcs(pV mxTransient);14696 vmxHCReadGuestPhysicalAddrVmcs(pVCpu, pVmxTransient); 14669 14697 int rc = vmxHCImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_MUST_MASK); 14670 14698 AssertRCReturn(rc, rc); … … 14734 14762 Assert(pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging); 14735 14763 14736 vmxHCReadExitQualVmcs(pV mxTransient);14737 vmxHCReadExitIntInfoVmcs(pV mxTransient);14738 vmxHCReadExitIntErrorCodeVmcs(pV mxTransient);14739 vmxHCReadExitInstrLenVmcs(pV mxTransient);14740 vmxHCReadIdtVectoringInfoVmcs(pV mxTransient);14741 vmxHCReadIdtVectoringErrorCodeVmcs(pV mxTransient);14764 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 14765 vmxHCReadExitIntInfoVmcs(pVCpu, pVmxTransient); 14766 vmxHCReadExitIntErrorCodeVmcs(pVCpu, pVmxTransient); 14767 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 14768 vmxHCReadIdtVectoringInfoVmcs(pVCpu, pVmxTransient); 14769 vmxHCReadIdtVectoringErrorCodeVmcs(pVCpu, pVmxTransient); 14742 14770 14743 14771 /* … … 14761 14789 14762 14790 PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo; 14763 vmxHCReadGuestPhysicalAddrVmcs(pV mxTransient);14791 vmxHCReadGuestPhysicalAddrVmcs(pVCpu, pVmxTransient); 14764 14792 int rc = vmxHCImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_MUST_MASK); 14765 14793 AssertRCReturn(rc, rc); … … 14812 14840 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient); 14813 14841 14814 vmxHCReadExitInstrLenVmcs(pV mxTransient);14815 vmxHCReadExitInstrInfoVmcs(pV mxTransient);14816 vmxHCReadExitQualVmcs(pV mxTransient);14842 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 14843 vmxHCReadExitInstrInfoVmcs(pVCpu, pVmxTransient); 14844 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 14817 14845 int rc = vmxHCImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SREG_MASK 14818 14846 | CPUMCTX_EXTRN_HWVIRT … … 14851 14879 /* Import the entire VMCS state for now as we would be switching VMCS on successful VMLAUNCH, 14852 14880 otherwise we could import just IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK. */ 14853 vmxHCReadExitInstrLenVmcs(pV mxTransient);14881 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 14854 14882 int rc = vmxHCImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, HMVMX_CPUMCTX_EXTRN_ALL); 14855 14883 AssertRCReturn(rc, rc); … … 14878 14906 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient); 14879 14907 14880 vmxHCReadExitInstrLenVmcs(pV mxTransient);14881 vmxHCReadExitInstrInfoVmcs(pV mxTransient);14882 vmxHCReadExitQualVmcs(pV mxTransient);14908 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 14909 vmxHCReadExitInstrInfoVmcs(pVCpu, pVmxTransient); 14910 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 14883 14911 int rc = vmxHCImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SREG_MASK 14884 14912 | CPUMCTX_EXTRN_HWVIRT … … 14915 14943 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient); 14916 14944 14917 vmxHCReadExitInstrLenVmcs(pV mxTransient);14918 vmxHCReadExitInstrInfoVmcs(pV mxTransient);14919 vmxHCReadExitQualVmcs(pV mxTransient);14945 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 14946 vmxHCReadExitInstrInfoVmcs(pVCpu, pVmxTransient); 14947 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 14920 14948 int rc = vmxHCImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SREG_MASK 14921 14949 | CPUMCTX_EXTRN_HWVIRT … … 14957 14985 * code elsewhere dares look at unsynced VMCS fields. 14958 14986 */ 14959 vmxHCReadExitInstrLenVmcs(pV mxTransient);14960 vmxHCReadExitInstrInfoVmcs(pV mxTransient);14961 vmxHCReadExitQualVmcs(pV mxTransient);14987 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 14988 vmxHCReadExitInstrInfoVmcs(pVCpu, pVmxTransient); 14989 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 14962 14990 int rc = vmxHCImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SREG_MASK 14963 14991 | CPUMCTX_EXTRN_HWVIRT … … 14997 15025 /* Import the entire VMCS state for now as we would be switching VMCS on successful VMRESUME, 14998 15026 otherwise we could import just IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK. */ 14999 vmxHCReadExitInstrLenVmcs(pV mxTransient);15027 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 15000 15028 int rc = vmxHCImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, HMVMX_CPUMCTX_EXTRN_ALL); 15001 15029 AssertRCReturn(rc, rc); … … 15029 15057 * flags re-loading the entire shadow VMCS, we should save the entire shadow VMCS here. 15030 15058 */ 15031 vmxHCReadExitInstrLenVmcs(pV mxTransient);15032 vmxHCReadExitInstrInfoVmcs(pV mxTransient);15033 vmxHCReadExitQualVmcs(pV mxTransient);15059 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 15060 vmxHCReadExitInstrInfoVmcs(pVCpu, pVmxTransient); 15061 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 15034 15062 int rc = vmxHCImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SREG_MASK 15035 15063 | CPUMCTX_EXTRN_HWVIRT … … 15067 15095 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient); 15068 15096 15069 vmxHCReadExitInstrLenVmcs(pV mxTransient);15097 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 15070 15098 int rc = vmxHCImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_CR4 15071 15099 | CPUMCTX_EXTRN_HWVIRT … … 15094 15122 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient); 15095 15123 15096 vmxHCReadExitInstrLenVmcs(pV mxTransient);15097 vmxHCReadExitInstrInfoVmcs(pV mxTransient);15098 vmxHCReadExitQualVmcs(pV mxTransient);15124 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 15125 vmxHCReadExitInstrInfoVmcs(pVCpu, pVmxTransient); 15126 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 15099 15127 int rc = vmxHCImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SREG_MASK 15100 15128 | CPUMCTX_EXTRN_HWVIRT … … 15131 15159 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient); 15132 15160 15133 vmxHCReadExitInstrLenVmcs(pV mxTransient);15134 vmxHCReadExitInstrInfoVmcs(pV mxTransient);15135 vmxHCReadExitQualVmcs(pV mxTransient);15161 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 15162 vmxHCReadExitInstrInfoVmcs(pVCpu, pVmxTransient); 15163 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 15136 15164 int rc = vmxHCImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SREG_MASK 15137 15165 | IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK); … … 15178 15206 HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient); 15179 15207 15180 vmxHCReadExitIntInfoVmcs(pV mxTransient);15208 vmxHCReadExitIntInfoVmcs(pVCpu, pVmxTransient); 15181 15209 15182 15210 uint64_t const uExitIntInfo = pVmxTransient->uExitIntInfo; … … 15203 15231 case VMX_EXIT_INT_INFO_TYPE_HW_XCPT: 15204 15232 { 15205 vmxHCReadExitIntErrorCodeVmcs(pV mxTransient);15206 vmxHCReadExitInstrLenVmcs(pV mxTransient);15207 vmxHCReadIdtVectoringInfoVmcs(pV mxTransient);15208 vmxHCReadIdtVectoringErrorCodeVmcs(pV mxTransient);15233 vmxHCReadExitIntErrorCodeVmcs(pVCpu, pVmxTransient); 15234 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 15235 vmxHCReadIdtVectoringInfoVmcs(pVCpu, pVmxTransient); 15236 vmxHCReadIdtVectoringErrorCodeVmcs(pVCpu, pVmxTransient); 15209 15237 15210 15238 PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx; … … 15214 15242 { 15215 15243 /* Exit qualification is required for debug and page-fault exceptions. */ 15216 vmxHCReadExitQualVmcs(pV mxTransient);15244 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 15217 15245 15218 15246 /* … … 15319 15347 HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient); 15320 15348 15321 vmxHCReadExitQualVmcs(pV mxTransient);15322 vmxHCReadExitInstrLenVmcs(pV mxTransient);15323 vmxHCReadIdtVectoringInfoVmcs(pV mxTransient);15324 vmxHCReadIdtVectoringErrorCodeVmcs(pV mxTransient);15349 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 15350 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 15351 vmxHCReadIdtVectoringInfoVmcs(pVCpu, pVmxTransient); 15352 vmxHCReadIdtVectoringErrorCodeVmcs(pVCpu, pVmxTransient); 15325 15353 15326 15354 VMXVEXITINFO ExitInfo; … … 15347 15375 if (CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_HLT_EXIT)) 15348 15376 { 15349 vmxHCReadExitInstrLenVmcs(pV mxTransient);15377 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 15350 15378 return IEMExecVmxVmexitInstr(pVCpu, pVmxTransient->uExitReason, pVmxTransient->cbExitInstr); 15351 15379 } … … 15363 15391 if (CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_INVLPG_EXIT)) 15364 15392 { 15365 vmxHCReadExitInstrLenVmcs(pV mxTransient);15366 vmxHCReadExitQualVmcs(pV mxTransient);15393 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 15394 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 15367 15395 15368 15396 VMXVEXITINFO ExitInfo; … … 15386 15414 if (CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_RDPMC_EXIT)) 15387 15415 { 15388 vmxHCReadExitInstrLenVmcs(pV mxTransient);15416 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 15389 15417 return IEMExecVmxVmexitInstr(pVCpu, pVmxTransient->uExitReason, pVmxTransient->cbExitInstr); 15390 15418 } … … 15404 15432 || pVmxTransient->uExitReason == VMX_EXIT_VMWRITE); 15405 15433 15406 vmxHCReadExitInstrInfoVmcs(pV mxTransient);15434 vmxHCReadExitInstrInfoVmcs(pVCpu, pVmxTransient); 15407 15435 15408 15436 uint8_t const iGReg = pVmxTransient->ExitInstrInfo.VmreadVmwrite.iReg2; … … 15416 15444 if (CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, pVmxTransient->uExitReason, u64VmcsField)) 15417 15445 { 15418 vmxHCReadExitInstrLenVmcs(pV mxTransient);15419 vmxHCReadExitQualVmcs(pV mxTransient);15446 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 15447 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 15420 15448 15421 15449 VMXVEXITINFO ExitInfo; … … 15443 15471 if (CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_RDTSC_EXIT)) 15444 15472 { 15445 vmxHCReadExitInstrLenVmcs(pV mxTransient);15473 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 15446 15474 return IEMExecVmxVmexitInstr(pVCpu, pVmxTransient->uExitReason, pVmxTransient->cbExitInstr); 15447 15475 } … … 15459 15487 HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient); 15460 15488 15461 vmxHCReadExitQualVmcs(pV mxTransient);15462 vmxHCReadExitInstrLenVmcs(pV mxTransient);15489 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 15490 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 15463 15491 15464 15492 VBOXSTRICTRC rcStrict; … … 15576 15604 if (fMemOperand) 15577 15605 { 15578 vmxHCReadGuestLinearAddrVmcs(pV mxTransient);15606 vmxHCReadGuestLinearAddrVmcs(pVCpu, pVmxTransient); 15579 15607 GCPtrEffDst = pVmxTransient->uGuestLinearAddr; 15580 15608 } … … 15623 15651 if (CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_MOV_DR_EXIT)) 15624 15652 { 15625 vmxHCReadExitQualVmcs(pV mxTransient);15626 vmxHCReadExitInstrLenVmcs(pV mxTransient);15653 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 15654 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 15627 15655 15628 15656 VMXVEXITINFO ExitInfo; … … 15645 15673 HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient); 15646 15674 15647 vmxHCReadExitQualVmcs(pV mxTransient);15675 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 15648 15676 15649 15677 uint32_t const uIOPort = VMX_EXIT_QUAL_IO_PORT(pVmxTransient->uExitQual); … … 15665 15693 */ 15666 15694 PVMCC pVM = pVCpu->CTX_SUFF(pVM); 15667 vmxHCReadExitInstrLenVmcs(pV mxTransient);15695 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 15668 15696 15669 15697 /* Make sure we don't use stale/uninitialized VMX-transient info. below. */ … … 15675 15703 if (fIOString) 15676 15704 { 15677 vmxHCReadGuestLinearAddrVmcs(pV mxTransient);15705 vmxHCReadGuestLinearAddrVmcs(pVCpu, pVmxTransient); 15678 15706 if (fVmxInsOutsInfo) 15679 15707 { 15680 15708 Assert(RT_BF_GET(g_HmMsrs.u.vmx.u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS)); /* Paranoia. */ 15681 vmxHCReadExitInstrInfoVmcs(pV mxTransient);15709 vmxHCReadExitInstrInfoVmcs(pVCpu, pVmxTransient); 15682 15710 } 15683 15711 } … … 15711 15739 if (fMsrpm & VMXMSRPM_EXIT_RD) 15712 15740 { 15713 vmxHCReadExitInstrLenVmcs(pV mxTransient);15741 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 15714 15742 return IEMExecVmxVmexitInstr(pVCpu, pVmxTransient->uExitReason, pVmxTransient->cbExitInstr); 15715 15743 } … … 15733 15761 if (fMsrpm & VMXMSRPM_EXIT_WR) 15734 15762 { 15735 vmxHCReadExitInstrLenVmcs(pV mxTransient);15763 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 15736 15764 return IEMExecVmxVmexitInstr(pVCpu, pVmxTransient->uExitReason, pVmxTransient->cbExitInstr); 15737 15765 } … … 15749 15777 if (CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_MWAIT_EXIT)) 15750 15778 { 15751 vmxHCReadExitInstrLenVmcs(pV mxTransient);15779 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 15752 15780 return IEMExecVmxVmexitInstr(pVCpu, pVmxTransient->uExitReason, pVmxTransient->cbExitInstr); 15753 15781 } … … 15765 15793 15766 15794 /** @todo NSTVMX: Should consider debugging nested-guests using VM debugger. */ 15767 vmxHCReadGuestPendingDbgXctps(pV mxTransient);15795 vmxHCReadGuestPendingDbgXctps(pVCpu, pVmxTransient); 15768 15796 VMXVEXITINFO ExitInfo; 15769 15797 RT_ZERO(ExitInfo); … … 15783 15811 if (CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_MONITOR_EXIT)) 15784 15812 { 15785 vmxHCReadExitInstrLenVmcs(pV mxTransient);15813 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 15786 15814 return IEMExecVmxVmexitInstr(pVCpu, pVmxTransient->uExitReason, pVmxTransient->cbExitInstr); 15787 15815 } … … 15805 15833 || CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)) 15806 15834 { 15807 vmxHCReadExitInstrLenVmcs(pV mxTransient);15835 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 15808 15836 return IEMExecVmxVmexitInstr(pVCpu, pVmxTransient->uExitReason, pVmxTransient->cbExitInstr); 15809 15837 } … … 15822 15850 if (CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_USE_TPR_SHADOW)) 15823 15851 { 15824 vmxHCReadGuestPendingDbgXctps(pV mxTransient);15852 vmxHCReadGuestPendingDbgXctps(pVCpu, pVmxTransient); 15825 15853 VMXVEXITINFO ExitInfo; 15826 15854 RT_ZERO(ExitInfo); … … 15841 15869 HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient); 15842 15870 15843 vmxHCReadExitInstrLenVmcs(pV mxTransient);15844 vmxHCReadIdtVectoringInfoVmcs(pV mxTransient);15845 vmxHCReadIdtVectoringErrorCodeVmcs(pV mxTransient);15846 vmxHCReadExitQualVmcs(pV mxTransient);15871 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 15872 vmxHCReadIdtVectoringInfoVmcs(pVCpu, pVmxTransient); 15873 vmxHCReadIdtVectoringErrorCodeVmcs(pVCpu, pVmxTransient); 15874 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 15847 15875 15848 15876 Assert(CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS2_VIRT_APIC_ACCESS)); … … 15874 15902 15875 15903 Assert(CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS2_APIC_REG_VIRT)); 15876 vmxHCReadExitQualVmcs(pV mxTransient);15904 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 15877 15905 return IEMExecVmxVmexit(pVCpu, pVmxTransient->uExitReason, pVmxTransient->uExitQual); 15878 15906 } … … 15888 15916 15889 15917 Assert(CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS2_VIRT_INT_DELIVERY)); 15890 vmxHCReadExitQualVmcs(pV mxTransient);15918 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 15891 15919 return IEMExecVmxVmexit(pVCpu, pVmxTransient->uExitReason, pVmxTransient->uExitQual); 15892 15920 } … … 15903 15931 { 15904 15932 Assert(CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS2_RDTSCP)); 15905 vmxHCReadExitInstrLenVmcs(pV mxTransient);15933 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 15906 15934 return IEMExecVmxVmexitInstr(pVCpu, pVmxTransient->uExitReason, pVmxTransient->cbExitInstr); 15907 15935 } … … 15919 15947 if (CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS2_WBINVD_EXIT)) 15920 15948 { 15921 vmxHCReadExitInstrLenVmcs(pV mxTransient);15949 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 15922 15950 return IEMExecVmxVmexitInstr(pVCpu, pVmxTransient->uExitReason, pVmxTransient->cbExitInstr); 15923 15951 } … … 15936 15964 { 15937 15965 Assert(CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS2_INVPCID)); 15938 vmxHCReadExitInstrLenVmcs(p VmxTransient);15939 vmxHCReadExitQualVmcs(pV mxTransient);15940 vmxHCReadExitInstrInfoVmcs(pV mxTransient);15966 vmxHCReadExitInstrLenVmcs(ppVCpu, VmxTransient); 15967 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 15968 vmxHCReadExitInstrInfoVmcs(pVCpu, pVmxTransient); 15941 15969 15942 15970 VMXVEXITINFO ExitInfo; … … 15996 16024 #endif 15997 16025 15998 vmxHCReadExitInstrLenVmcs(pV mxTransient);16026 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 15999 16027 return IEMExecVmxVmexitInstr(pVCpu, pVmxTransient->uExitReason, pVmxTransient->cbExitInstr); 16000 16028 } … … 16046 16074 #endif 16047 16075 16048 vmxHCReadExitInstrLenVmcs(pV mxTransient);16049 vmxHCReadExitQualVmcs(pV mxTransient);16050 vmxHCReadExitInstrInfoVmcs(pV mxTransient);16076 vmxHCReadExitInstrLenVmcs(pVCpu, pVmxTransient); 16077 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 16078 vmxHCReadExitInstrInfoVmcs(pVCpu, pVmxTransient); 16051 16079 16052 16080 VMXVEXITINFO ExitInfo;
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