Changeset 92331 in vbox for trunk/src/VBox/VMM/VMMAll

Timestamp:

Nov 10, 2021 4:55:00 PM (3 years ago)

Author:

vboxsync

Message:

VMM: Nested VMX: bugref:10092 Have R and W as separate bits in PGMPTATTRS now that bit 0 is freed up (still retains 1:1 with regular page-table format).

File:

• trunk/src/VBox/VMM/VMMAll/PGMAllGst.h (modified) (10 diffs)

trunk/src/VBox/VMM/VMMAll/PGMAllGst.h

@@ -149 +149 @@
 # endif
 
-    uint64_t fEffective = X86_PTE_RW | X86_PTE_US | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_A | 1;  /** @todo can this default assignment be removed? */
+    uint64_t fEffective;
     {
 # if PGM_GST_TYPE == PGM_TYPE_AMD64
@@ -170 +170 @@
         else return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 4);
 
-        pWalk->Core.fEffective = fEffective = Pml4e.u & (  X86_PML4E_RW  | X86_PML4E_US | X86_PML4E_PWT
+        pWalk->Core.fEffective = fEffective = Pml4e.u & (  X86_PML4E_P   | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_PWT
                                                          | X86_PML4E_PCD | X86_PML4E_A  | X86_PML4E_NX);
 
@@ -204 +204 @@
 
 # if PGM_GST_TYPE == PGM_TYPE_AMD64
-        pWalk->Core.fEffective = fEffective &= (Pdpe.u & (X86_PDPE_RW | X86_PDPE_US | X86_PDPE_PWT | X86_PDPE_PCD | X86_PDPE_A))
+        pWalk->Core.fEffective = fEffective &= (Pdpe.u & (  X86_PDPE_P   | X86_PDPE_RW  | X86_PDPE_US
+                                                          | X86_PDPE_PWT | X86_PDPE_PCD | X86_PDPE_A))
                                              | (Pdpe.u & X86_PDPE_LM_NX);
 # else
         /* NX in the legacy-mode PAE PDPE is reserved. The valid check above ensures the NX bit is not set. */
-        pWalk->Core.fEffective = fEffective  = X86_PDPE_RW  | X86_PDPE_US | X86_PDPE_A
+        pWalk->Core.fEffective = fEffective  = X86_PDPE_P | X86_PDPE_RW  | X86_PDPE_US | X86_PDPE_A
                                              | (Pdpe.u & (X86_PDPE_PWT | X86_PDPE_PCD));
 # endif
@@ -245 +246 @@
              */
 # if PGM_GST_TYPE == PGM_TYPE_32BIT
-            fEffective &=  Pde.u & (X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_PWT | X86_PDE4M_PCD | X86_PDE4M_A);
+            fEffective  =  Pde.u & (X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_PWT | X86_PDE4M_PCD | X86_PDE4M_A);
 # else
-            fEffective &= (Pde.u & (X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_PWT | X86_PDE4M_PCD | X86_PDE4M_A))
+            fEffective &= (Pde.u & (X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_PWT | X86_PDE4M_PCD | X86_PDE4M_A))
                         | (Pde.u & X86_PDE2M_PAE_NX);
 # endif
@@ -254 +255 @@
             pWalk->Core.fEffective = fEffective;
             Assert(GST_IS_NX_ACTIVE(pVCpu) || !(fEffective & PGM_PTATTRS_NX_MASK));
+            Assert(fEffective & PGM_PTATTRS_R_MASK);
 
             pWalk->Core.fEffectiveRW = !!(fEffective & X86_PTE_RW);
@@ -273 +275 @@
             return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 2);
 # if PGM_GST_TYPE == PGM_TYPE_32BIT
-        pWalk->Core.fEffective = fEffective &= Pde.u & (X86_PDE_RW | X86_PDE_US | X86_PDE_PWT | X86_PDE_PCD | X86_PDE_A);
+        pWalk->Core.fEffective = fEffective  = Pde.u & (  X86_PDE_P   | X86_PDE_RW  | X86_PDE_US
+                                                        | X86_PDE_PWT | X86_PDE_PCD | X86_PDE_A);
 # else
-        pWalk->Core.fEffective = fEffective &= (Pde.u & (X86_PDE_RW | X86_PDE_US | X86_PDE_PWT | X86_PDE_PCD | X86_PDE_A))
+        pWalk->Core.fEffective = fEffective &= (Pde.u & (  X86_PDE_P   | X86_PDE_RW  | X86_PDE_US
+                                                         | X86_PDE_PWT | X86_PDE_PCD | X86_PDE_A))
                                              | (Pde.u & X86_PDE_PAE_NX);
 # endif
@@ -306 +310 @@
          */
 # if PGM_GST_TYPE == PGM_TYPE_32BIT
-        fEffective &= Pte.u & (X86_PTE_RW | X86_PTE_US | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_A);
+        fEffective &=  Pte.u & (X86_PTE_P | X86_PTE_RW | X86_PTE_US | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_A);
 # else
-        fEffective &= (Pte.u & (X86_PTE_RW | X86_PTE_US | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_A))
+        fEffective &= (Pte.u & (X86_PTE_P | X86_PTE_RW | X86_PTE_US | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_A))
                    |  (Pte.u & X86_PTE_PAE_NX);
 # endif
@@ -314 +318 @@
         pWalk->Core.fEffective = fEffective;
         Assert(GST_IS_NX_ACTIVE(pVCpu) || !(fEffective & PGM_PTATTRS_NX_MASK));
+        Assert(fEffective & PGM_PTATTRS_R_MASK);
 
         pWalk->Core.fEffectiveRW = !!(fEffective & X86_PTE_RW);
@@ -376 +381 @@
         if (!Walk.Core.fBigPage)
             *pfFlags = (Walk.Pte.u & ~(GST_PTE_PG_MASK | X86_PTE_RW | X86_PTE_US))                      /* NX not needed */
-                     | (Walk.Core.fEffective & (  PGM_PTATTRS_RW_MASK
+                     | (Walk.Core.fEffective & (  PGM_PTATTRS_W_MASK
                                                 | PGM_PTATTRS_US_MASK))
 # if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
@@ -385 +390 @@
         {
             *pfFlags = (Walk.Pde.u & ~(GST_PTE_PG_MASK | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_PS))   /* NX not needed */
-                     | (Walk.Core.fEffective & (  PGM_PTATTRS_RW_MASK
+                     | (Walk.Core.fEffective & (  PGM_PTATTRS_W_MASK
                                                 | PGM_PTATTRS_US_MASK
                                                 | PGM_PTATTRS_PAT_MASK))