Changeset 92355 in vbox
- Timestamp:
- Nov 11, 2021 10:57:21 AM (3 years ago)
- File:
-
- 1 edited
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- Added
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trunk/src/VBox/VMM/VMMAll/VMXAllTemplate.cpp.h
r92318 r92355 119 119 /** Profiling macro. */ 120 120 #ifdef HM_PROFILE_EXIT_DISPATCH 121 # define HMVMX_START_EXIT_DISPATCH_PROF() STAM_PROFILE_ADV_START(&VCPU_2_VMXSTAT E(pVCpu).StatExitDispatch, ed)122 # define HMVMX_STOP_EXIT_DISPATCH_PROF() STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTAT E(pVCpu).StatExitDispatch, ed)121 # define HMVMX_START_EXIT_DISPATCH_PROF() STAM_PROFILE_ADV_START(&VCPU_2_VMXSTATS(pVCpu).StatExitDispatch, ed) 122 # define HMVMX_STOP_EXIT_DISPATCH_PROF() STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTATS(pVCpu).StatExitDispatch, ed) 123 123 #else 124 124 # define HMVMX_START_EXIT_DISPATCH_PROF() do { } while (0) … … 3873 3873 Assert(CPUMIsGuestDebugStateActive(pVCpu)); 3874 3874 Assert(!CPUMIsHyperDebugStateActive(pVCpu)); 3875 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatDRxArmed);3875 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatDRxArmed); 3876 3876 } 3877 3877 Assert(!fInterceptMovDRx); … … 4207 4207 PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx; 4208 4208 PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo; 4209 #ifdef IN_RING0 4209 4210 PVMXVMCSINFOSHARED pVmcsInfoShared = pVmcsInfo->pShared; 4211 #endif 4210 4212 4211 4213 /* … … 4659 4661 && TMVirtualSyncIsCurrentDeadlineVersion(pVM, pVCpu->hmr0.s.vmx.uTscDeadlineVersion)) 4660 4662 { 4661 STAM_REL_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatVmxPreemptionReusingDeadline);4663 STAM_REL_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatVmxPreemptionReusingDeadline); 4662 4664 fOffsettedTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &uTscOffset, &fParavirtTsc); 4663 4665 cTicksToDeadline = pVCpu->hmr0.s.vmx.uTscDeadline - SUPReadTsc(); … … 4666 4668 else 4667 4669 { 4668 STAM_REL_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatVmxPreemptionReusingDeadlineExpired);4670 STAM_REL_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatVmxPreemptionReusingDeadlineExpired); 4669 4671 cTicksToDeadline = 0; 4670 4672 } … … 4672 4674 else 4673 4675 { 4674 STAM_REL_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatVmxPreemptionRecalcingDeadline);4676 STAM_REL_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatVmxPreemptionRecalcingDeadline); 4675 4677 cTicksToDeadline = TMCpuTickGetDeadlineAndTscOffset(pVM, pVCpu, &uTscOffset, &fOffsettedTsc, &fParavirtTsc, 4676 4678 &pVCpu->hmr0.s.vmx.uTscDeadline, … … 4680 4682 { /* hopefully */ } 4681 4683 else 4682 STAM_REL_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatVmxPreemptionRecalcingDeadlineExpired);4684 STAM_REL_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatVmxPreemptionRecalcingDeadlineExpired); 4683 4685 } 4684 4686 … … 4707 4709 AssertRC(rc); 4708 4710 #endif 4709 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatTscParavirt);4711 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatTscParavirt); 4710 4712 } 4711 4713 … … 5200 5202 # endif 5201 5203 5202 STAM_PROFILE_ADV_START(&VCPU_2_VMXSTAT E(pVCpu).StatImportGuestState, x);5204 STAM_PROFILE_ADV_START(&VCPU_2_VMXSTATS(pVCpu).StatImportGuestState, x); 5203 5205 5204 5206 #ifdef IN_RING0 … … 5544 5546 #endif 5545 5547 5546 STAM_PROFILE_ADV_STOP(& VCPU_2_VMXSTATE(pVCpu).StatImportGuestState, x);5548 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTATS(pVCpu).StatImportGuestState, x); 5547 5549 5548 5550 if (RT_SUCCESS(rc)) … … 5648 5650 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK)) 5649 5651 { 5650 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatSwitchHmToR3FF);5652 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatSwitchHmToR3FF); 5651 5653 int rc = RT_LIKELY(!VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_RAW_TO_R3 : VINF_EM_NO_MEMORY; 5652 5654 Log4Func(("HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc)); … … 5658 5660 || VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_REQUEST)) 5659 5661 { 5660 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatSwitchVmReq);5662 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatSwitchVmReq); 5661 5663 Log4Func(("Pending VM request forcing us back to ring-3\n")); 5662 5664 return VINF_EM_PENDING_REQUEST; … … 5666 5668 if (VM_FF_IS_SET(pVM, VM_FF_PGM_POOL_FLUSH_PENDING)) 5667 5669 { 5668 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatSwitchPgmPoolFlush);5670 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatSwitchPgmPoolFlush); 5669 5671 Log4Func(("PGM pool flush pending forcing us back to ring-3\n")); 5670 5672 return VINF_PGM_POOL_FLUSH_PENDING; … … 5674 5676 if (VM_FF_IS_SET(pVM, VM_FF_PDM_DMA)) 5675 5677 { 5676 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatSwitchDma);5678 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatSwitchDma); 5677 5679 Log4Func(("Pending DMA request forcing us back to ring-3\n")); 5678 5680 return VINF_EM_RAW_TO_R3; … … 5960 5962 pVCpu->hmr0.s.vmx.fUpdatedHostAutoMsrs = false; 5961 5963 5962 STAM_PROFILE_ADV_SET_STOPPED(&VCPU_2_VMXSTAT E(pVCpu).StatEntry);5963 STAM_PROFILE_ADV_SET_STOPPED(&VCPU_2_VMXSTAT E(pVCpu).StatImportGuestState);5964 STAM_PROFILE_ADV_SET_STOPPED(&VCPU_2_VMXSTAT E(pVCpu).StatExportGuestState);5965 STAM_PROFILE_ADV_SET_STOPPED(&VCPU_2_VMXSTAT E(pVCpu).StatPreExit);5966 STAM_PROFILE_ADV_SET_STOPPED(&VCPU_2_VMXSTAT E(pVCpu).StatExitHandling);5967 STAM_PROFILE_ADV_SET_STOPPED(&VCPU_2_VMXSTAT E(pVCpu).StatExitIO);5968 STAM_PROFILE_ADV_SET_STOPPED(&VCPU_2_VMXSTAT E(pVCpu).StatExitMovCRx);5969 STAM_PROFILE_ADV_SET_STOPPED(&VCPU_2_VMXSTAT E(pVCpu).StatExitXcptNmi);5970 STAM_PROFILE_ADV_SET_STOPPED(&VCPU_2_VMXSTAT E(pVCpu).StatExitVmentry);5971 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatSwitchLongJmpToR3);5964 STAM_PROFILE_ADV_SET_STOPPED(&VCPU_2_VMXSTATS(pVCpu).StatEntry); 5965 STAM_PROFILE_ADV_SET_STOPPED(&VCPU_2_VMXSTATS(pVCpu).StatImportGuestState); 5966 STAM_PROFILE_ADV_SET_STOPPED(&VCPU_2_VMXSTATS(pVCpu).StatExportGuestState); 5967 STAM_PROFILE_ADV_SET_STOPPED(&VCPU_2_VMXSTATS(pVCpu).StatPreExit); 5968 STAM_PROFILE_ADV_SET_STOPPED(&VCPU_2_VMXSTATS(pVCpu).StatExitHandling); 5969 STAM_PROFILE_ADV_SET_STOPPED(&VCPU_2_VMXSTATS(pVCpu).StatExitIO); 5970 STAM_PROFILE_ADV_SET_STOPPED(&VCPU_2_VMXSTATS(pVCpu).StatExitMovCRx); 5971 STAM_PROFILE_ADV_SET_STOPPED(&VCPU_2_VMXSTATS(pVCpu).StatExitXcptNmi); 5972 STAM_PROFILE_ADV_SET_STOPPED(&VCPU_2_VMXSTATS(pVCpu).StatExitVmentry); 5973 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatSwitchLongJmpToR3); 5972 5974 5973 5975 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC); … … 6162 6164 int rc = vmxHCLeaveSession(pVCpu); 6163 6165 AssertRCReturn(rc, rc); 6164 STAM_COUNTER_DEC(&VCPU_2_VMXSTAT E(pVCpu).StatSwitchLongJmpToR3);6166 STAM_COUNTER_DEC(&VCPU_2_VMXSTATS(pVCpu).StatSwitchLongJmpToR3); 6165 6167 6166 6168 /* Thread-context hooks are unregistered at this point!!! */ … … 6192 6194 } 6193 6195 6194 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatSwitchExitToR3);6196 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatSwitchExitToR3); 6195 6197 VMMRZCallRing3Enable(pVCpu); 6196 6198 return rc; … … 6301 6303 Assert(uIntType != VMX_EXIT_INT_INFO_TYPE_NMI || uVector == X86_XCPT_NMI); 6302 6304 Assert(uIntType != VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT || uVector == X86_XCPT_DB); 6303 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).aStatInjectedXcpts[uVector]);6305 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).aStatInjectedXcpts[uVector]); 6304 6306 } 6305 6307 else 6306 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).aStatInjectedIrqs[uVector & MASK_INJECT_IRQ_STAT]);6308 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).aStatInjectedIrqs[uVector & MASK_INJECT_IRQ_STAT]); 6307 6309 6308 6310 /* … … 6606 6608 else if (rc == VERR_APIC_INTR_MASKED_BY_TPR) 6607 6609 { 6608 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatSwitchTprMaskedIrq);6610 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatSwitchTprMaskedIrq); 6609 6611 6610 6612 if ( !fIsNestedGuest … … 6620 6622 } 6621 6623 else 6622 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatSwitchGuestIrq);6624 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatSwitchGuestIrq); 6623 6625 6624 6626 /* We've injected the interrupt or taken necessary action, bail. */ … … 6725 6727 6726 6728 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT) 6727 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatInjectInterrupt);6729 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatInjectInterrupt); 6728 6730 else 6729 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatInjectXcpt);6731 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatInjectXcpt); 6730 6732 } 6731 6733 … … 6811 6813 LogFlowFunc(("pVCpu=%p\n", pVCpu)); 6812 6814 6813 STAM_PROFILE_ADV_START(&VCPU_2_VMXSTAT E(pVCpu).StatExportGuestState, x);6815 STAM_PROFILE_ADV_START(&VCPU_2_VMXSTATS(pVCpu).StatExportGuestState, x); 6814 6816 6815 6817 #ifdef IN_RING0 … … 6877 6879 | (HM_CHANGED_KEEPER_STATE_MASK & ~HM_CHANGED_VMX_MASK))); 6878 6880 6879 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTAT E(pVCpu).StatExportGuestState, x);6881 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTATS(pVCpu).StatExportGuestState, x); 6880 6882 return rc; 6881 6883 } … … 6962 6964 vmxHCExportGuestRflags(pVCpu, pVmxTransient); 6963 6965 rcStrict = vmxHCExportGuestHwvirtState(pVCpu, pVmxTransient); 6964 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExportMinimal);6966 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExportMinimal); 6965 6967 } 6966 6968 /* If anything else also changed, go through the full export routine and export as required. */ … … 6979 6981 return rcStrict; 6980 6982 } 6981 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExportFull);6983 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExportFull); 6982 6984 } 6983 6985 /* Nothing changed, nothing to load here. */ … … 7662 7664 if (fDispatched) 7663 7665 { 7664 STAM_REL_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitHostNmiInGC);7666 STAM_REL_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitHostNmiInGC); 7665 7667 return VINF_SUCCESS; 7666 7668 } … … 7671 7673 * (to the target CPU) without dispatching the host NMI above. 7672 7674 */ 7673 STAM_REL_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitHostNmiInGCIpi);7675 STAM_REL_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitHostNmiInGCIpi); 7674 7676 return RTMpOnSpecific(idCpu, &hmR0DispatchHostNmi, NULL /* pvUser1 */, NULL /* pvUser2 */); 7675 7677 } … … 8074 8076 Assert(!HMR0SuspendPending()); 8075 8077 HMVMX_ASSERT_CPU_SAFE(pVCpu); 8076 STAM_PROFILE_ADV_START(&VCPU_2_VMXSTAT E(pVCpu).StatEntry, x);8078 STAM_PROFILE_ADV_START(&VCPU_2_VMXSTATS(pVCpu).StatEntry, x); 8077 8079 8078 8080 /* … … 8099 8101 else 8100 8102 { 8101 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTAT E(pVCpu).StatPreExit, x);8103 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTATS(pVCpu).StatPreExit, x); 8102 8104 vmxHCReportWorldSwitchError(pVCpu, rcRun, &VmxTransient); 8103 8105 return rcRun; … … 8108 8110 */ 8109 8111 AssertMsg(VmxTransient.uExitReason <= VMX_EXIT_MAX, ("%#x\n", VmxTransient.uExitReason)); 8110 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitAll);8111 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).aStatExitReason[VmxTransient.uExitReason & MASK_EXITREASON_STAT]);8112 STAM_PROFILE_ADV_STOP_START(&VCPU_2_VMXSTAT E(pVCpu).StatPreExit, &VCPU_2_VMXSTATE(pVCpu).StatExitHandling, x);8112 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitAll); 8113 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).aStatExitReason[VmxTransient.uExitReason & MASK_EXITREASON_STAT]); 8114 STAM_PROFILE_ADV_STOP_START(&VCPU_2_VMXSTATS(pVCpu).StatPreExit, &VCPU_2_VMXSTATS(pVCpu).StatExitHandling, x); 8113 8115 HMVMX_START_EXIT_DISPATCH_PROF(); 8114 8116 … … 8123 8125 rcStrict = vmxHCHandleExit(pVCpu, &VmxTransient); 8124 8126 #endif 8125 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTAT E(pVCpu).StatExitHandling, x);8127 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTATS(pVCpu).StatExitHandling, x); 8126 8128 if (rcStrict == VINF_SUCCESS) 8127 8129 { 8128 8130 if (++(*pcLoops) <= cMaxResumeLoops) 8129 8131 continue; 8130 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatSwitchMaxResumeLoops);8132 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatSwitchMaxResumeLoops); 8131 8133 rcStrict = VINF_EM_RAW_INTERRUPT; 8132 8134 } … … 8134 8136 } 8135 8137 8136 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTAT E(pVCpu).StatEntry, x);8138 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTATS(pVCpu).StatEntry, x); 8137 8139 return rcStrict; 8138 8140 } … … 8186 8188 Assert(!HMR0SuspendPending()); 8187 8189 HMVMX_ASSERT_CPU_SAFE(pVCpu); 8188 STAM_PROFILE_ADV_START(&VCPU_2_VMXSTAT E(pVCpu).StatEntry, x);8190 STAM_PROFILE_ADV_START(&VCPU_2_VMXSTATS(pVCpu).StatEntry, x); 8189 8191 8190 8192 /* … … 8211 8213 else 8212 8214 { 8213 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTAT E(pVCpu).StatPreExit, x);8215 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTATS(pVCpu).StatPreExit, x); 8214 8216 vmxHCReportWorldSwitchError(pVCpu, rcRun, &VmxTransient); 8215 8217 return rcRun; … … 8220 8222 */ 8221 8223 AssertMsg(VmxTransient.uExitReason <= VMX_EXIT_MAX, ("%#x\n", VmxTransient.uExitReason)); 8222 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitAll);8223 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatNestedExitAll);8224 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).aStatNestedExitReason[VmxTransient.uExitReason & MASK_EXITREASON_STAT]);8225 STAM_PROFILE_ADV_STOP_START(&VCPU_2_VMXSTAT E(pVCpu).StatPreExit, &VCPU_2_VMXSTATE(pVCpu).StatExitHandling, x);8224 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitAll); 8225 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatNestedExitAll); 8226 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).aStatNestedExitReason[VmxTransient.uExitReason & MASK_EXITREASON_STAT]); 8227 STAM_PROFILE_ADV_STOP_START(&VCPU_2_VMXSTATS(pVCpu).StatPreExit, &VCPU_2_VMXSTATS(pVCpu).StatExitHandling, x); 8226 8228 HMVMX_START_EXIT_DISPATCH_PROF(); 8227 8229 … … 8232 8234 */ 8233 8235 rcStrict = vmxHCHandleExitNested(pVCpu, &VmxTransient); 8234 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTAT E(pVCpu).StatExitHandling, x);8236 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTATS(pVCpu).StatExitHandling, x); 8235 8237 if (rcStrict == VINF_SUCCESS) 8236 8238 { 8237 8239 if (!CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.GstCtx)) 8238 8240 { 8239 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatSwitchNstGstVmexit);8241 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatSwitchNstGstVmexit); 8240 8242 rcStrict = VINF_VMX_VMEXIT; 8241 8243 } … … 8244 8246 if (++(*pcLoops) <= cMaxResumeLoops) 8245 8247 continue; 8246 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatSwitchMaxResumeLoops);8248 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatSwitchMaxResumeLoops); 8247 8249 rcStrict = VINF_EM_RAW_INTERRUPT; 8248 8250 } … … 8253 8255 } 8254 8256 8255 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTAT E(pVCpu).StatEntry, x);8257 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTATS(pVCpu).StatEntry, x); 8256 8258 return rcStrict; 8257 8259 } … … 9342 9344 Assert(!HMR0SuspendPending()); 9343 9345 HMVMX_ASSERT_CPU_SAFE(pVCpu); 9344 STAM_PROFILE_ADV_START(&VCPU_2_VMXSTAT E(pVCpu).StatEntry, x);9346 STAM_PROFILE_ADV_START(&VCPU_2_VMXSTATS(pVCpu).StatEntry, x); 9345 9347 bool fStepping = VCPU_2_VMXSTATE(pVCpu).fSingleInstruction; 9346 9348 … … 9377 9379 else 9378 9380 { 9379 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTAT E(pVCpu).StatPreExit, x);9381 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTATS(pVCpu).StatPreExit, x); 9380 9382 vmxHCReportWorldSwitchError(pVCpu, rcRun, &VmxTransient); 9381 9383 return rcRun; … … 9384 9386 /* Profile the VM-exit. */ 9385 9387 AssertMsg(VmxTransient.uExitReason <= VMX_EXIT_MAX, ("%#x\n", VmxTransient.uExitReason)); 9386 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitAll);9387 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).aStatExitReason[VmxTransient.uExitReason & MASK_EXITREASON_STAT]);9388 STAM_PROFILE_ADV_STOP_START(&VCPU_2_VMXSTAT E(pVCpu).StatPreExit, &VCPU_2_VMXSTATE(pVCpu).StatExitHandling, x);9388 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitAll); 9389 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).aStatExitReason[VmxTransient.uExitReason & MASK_EXITREASON_STAT]); 9390 STAM_PROFILE_ADV_STOP_START(&VCPU_2_VMXSTATS(pVCpu).StatPreExit, &VCPU_2_VMXSTATS(pVCpu).StatExitHandling, x); 9389 9391 HMVMX_START_EXIT_DISPATCH_PROF(); 9390 9392 … … 9395 9397 */ 9396 9398 rcStrict = vmxHCRunDebugHandleExit(pVCpu, &VmxTransient, &DbgState); 9397 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTAT E(pVCpu).StatExitHandling, x);9399 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTATS(pVCpu).StatExitHandling, x); 9398 9400 if (rcStrict != VINF_SUCCESS) 9399 9401 break; 9400 9402 if (++(*pcLoops) > cMaxResumeLoops) 9401 9403 { 9402 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatSwitchMaxResumeLoops);9404 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatSwitchMaxResumeLoops); 9403 9405 rcStrict = VINF_EM_RAW_INTERRUPT; 9404 9406 break; … … 9452 9454 VCPU_2_VMXSTATE(pVCpu).fSingleInstruction = fSavedSingleInstruction; 9453 9455 9454 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTAT E(pVCpu).StatEntry, x);9456 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTATS(pVCpu).StatEntry, x); 9455 9457 return rcStrict; 9456 9458 } … … 9988 9990 9989 9991 /* If uExitVector is #PF, CR2 value will be updated from the VMCS if it's a guest #PF, see vmxHCExitXcptPF(). */ 9990 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatInjectReflect);9992 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatInjectReflect); 9991 9993 vmxHCSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(uIdtVectorInfo), 0 /* cbInstr */, 9992 9994 u32ErrCode, pVCpu->cpum.GstCtx.cr2); … … 10017 10019 else 10018 10020 { 10019 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatInjectConvertDF);10021 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatInjectConvertDF); 10020 10022 vmxHCSetPendingXcptDF(pVCpu); 10021 10023 Log4Func(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", VCPU_2_VMXSTATE(pVCpu).Event.u64IntInfo, … … 10367 10369 } 10368 10370 10369 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitLmsw);10371 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitLmsw); 10370 10372 Log4Func(("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); 10371 10373 return rcStrict; … … 10392 10394 } 10393 10395 10394 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitClts);10396 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitClts); 10395 10397 Log4Func(("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); 10396 10398 return rcStrict; … … 10420 10422 switch (iCrReg) 10421 10423 { 10422 case 0: STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitCR0Read); break;10423 case 2: STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitCR2Read); break;10424 case 3: STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitCR3Read); break;10425 case 4: STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitCR4Read); break;10426 case 8: STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitCR8Read); break;10424 case 0: STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitCR0Read); break; 10425 case 2: STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitCR2Read); break; 10426 case 3: STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitCR3Read); break; 10427 case 4: STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitCR4Read); break; 10428 case 8: STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitCR8Read); break; 10427 10429 } 10428 10430 #endif … … 10449 10451 ASMAtomicUoOrU64(&VCPU_2_VMXSTATE(pVCpu).fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_CR0 10450 10452 | HM_CHANGED_GUEST_EFER_MSR | HM_CHANGED_VMX_ENTRY_EXIT_CTLS); 10451 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitCR0Write);10453 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitCR0Write); 10452 10454 Log4Func(("CR0 write. rcStrict=%Rrc CR0=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cr0)); 10453 10455 break; 10454 10456 10455 10457 case 2: 10456 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitCR2Write);10458 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitCR2Write); 10457 10459 /* Nothing to do here, CR2 it's not part of the VMCS. */ 10458 10460 break; … … 10460 10462 case 3: 10461 10463 ASMAtomicUoOrU64(&VCPU_2_VMXSTATE(pVCpu).fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_CR3); 10462 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitCR3Write);10464 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitCR3Write); 10463 10465 Log4Func(("CR3 write. rcStrict=%Rrc CR3=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cr3)); 10464 10466 break; … … 10466 10468 case 4: 10467 10469 ASMAtomicUoOrU64(&VCPU_2_VMXSTATE(pVCpu).fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_CR4); 10468 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitCR4Write);10470 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitCR4Write); 10469 10471 #ifdef IN_RING0 10470 10472 Log4Func(("CR4 write. rc=%Rrc CR4=%#RX64 fLoadSaveGuestXcr0=%u\n", VBOXSTRICTRC_VAL(rcStrict), … … 10478 10480 ASMAtomicUoOrU64(&VCPU_2_VMXSTATE(pVCpu).fCtxChanged, 10479 10481 HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_APIC_TPR); 10480 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitCR8Write);10482 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitCR8Write); 10481 10483 break; 10482 10484 … … 10528 10530 Log4Func(("Pending #DF due to vectoring #PF w/ NestedPaging\n")); 10529 10531 } 10530 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestPF);10532 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestPF); 10531 10533 return VINF_SUCCESS; 10532 10534 } … … 10561 10563 ASMAtomicUoOrU64(&VCPU_2_VMXSTATE(pVCpu).fCtxChanged, HM_CHANGED_ALL_GUEST); 10562 10564 TRPMResetTrap(pVCpu); 10563 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitShadowPF);10565 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitShadowPF); 10564 10566 return rc; 10565 10567 } … … 10585 10587 } 10586 10588 10587 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestPF);10589 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestPF); 10588 10590 return VINF_SUCCESS; 10589 10591 } 10590 10592 10591 10593 TRPMResetTrap(pVCpu); 10592 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitShadowPFEM);10594 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitShadowPFEM); 10593 10595 return rc; 10594 10596 } … … 10603 10605 { 10604 10606 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient); 10605 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestMF);10607 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestMF); 10606 10608 10607 10609 int rc = vmxHCImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_CR0); … … 10635 10637 { 10636 10638 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient); 10637 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestBP);10639 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestBP); 10638 10640 10639 10641 int rc = vmxHCImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, HMVMX_CPUMCTX_EXTRN_ALL); … … 10684 10686 * Check for debug/trace events and import state accordingly. 10685 10687 */ 10686 STAM_REL_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestACSplitLock);10688 STAM_REL_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestACSplitLock); 10687 10689 PVMCC pVM = pVCpu->CTX_SUFF(pVM); 10688 10690 if ( !DBGF_IS_EVENT_ENABLED(pVM, DBGFEVENT_VMX_SPLIT_LOCK) … … 10753 10755 } 10754 10756 10755 STAM_REL_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestAC);10757 STAM_REL_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestAC); 10756 10758 Log8Func(("cs:rip=%#04x:%#RX64 rflags=%#RX64 cr0=%#RX64 cpl=%d -> #AC\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, 10757 10759 pVCpu->cpum.GstCtx.rflags, pVCpu->cpum.GstCtx.cr0, CPUMGetGuestCPL(pVCpu) )); … … 10772 10774 { 10773 10775 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient); 10774 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestDB);10776 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestDB); 10775 10777 10776 10778 /* … … 10943 10945 { 10944 10946 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient); 10945 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestGP);10947 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestGP); 10946 10948 10947 10949 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx; … … 11060 11062 switch (uVector) 11061 11063 { 11062 case X86_XCPT_DE: STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestDE); break;11063 case X86_XCPT_DB: STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestDB); break;11064 case X86_XCPT_BP: STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestBP); break;11065 case X86_XCPT_OF: STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestOF); break;11066 case X86_XCPT_BR: STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestBR); break;11067 case X86_XCPT_UD: STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestUD); break;11068 case X86_XCPT_NM: STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestOF); break;11069 case X86_XCPT_DF: STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestDF); break;11070 case X86_XCPT_TS: STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestTS); break;11071 case X86_XCPT_NP: STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestNP); break;11072 case X86_XCPT_SS: STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestSS); break;11073 case X86_XCPT_GP: STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestGP); break;11074 case X86_XCPT_PF: STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestPF); break;11075 case X86_XCPT_MF: STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestMF); break;11076 case X86_XCPT_AC: STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestAC); break;11077 case X86_XCPT_XF: STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestXF); break;11064 case X86_XCPT_DE: STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestDE); break; 11065 case X86_XCPT_DB: STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestDB); break; 11066 case X86_XCPT_BP: STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestBP); break; 11067 case X86_XCPT_OF: STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestOF); break; 11068 case X86_XCPT_BR: STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestBR); break; 11069 case X86_XCPT_UD: STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestUD); break; 11070 case X86_XCPT_NM: STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestOF); break; 11071 case X86_XCPT_DF: STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestDF); break; 11072 case X86_XCPT_TS: STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestTS); break; 11073 case X86_XCPT_NP: STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestNP); break; 11074 case X86_XCPT_SS: STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestSS); break; 11075 case X86_XCPT_GP: STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestGP); break; 11076 case X86_XCPT_PF: STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestPF); break; 11077 case X86_XCPT_MF: STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestMF); break; 11078 case X86_XCPT_AC: STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestAC); break; 11079 case X86_XCPT_XF: STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestXF); break; 11078 11080 default: 11079 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitGuestXcpUnk);11081 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitGuestXcpUnk); 11080 11082 break; 11081 11083 } … … 11161 11163 { 11162 11164 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient); 11163 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitExtInt);11165 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitExtInt); 11164 11166 11165 11167 #ifdef IN_RING0 … … 11181 11183 { 11182 11184 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient); 11183 STAM_PROFILE_ADV_START(&VCPU_2_VMXSTAT E(pVCpu).StatExitXcptNmi, y3);11185 STAM_PROFILE_ADV_START(&VCPU_2_VMXSTATS(pVCpu).StatExitXcptNmi, y3); 11184 11186 11185 11187 vmxHCReadExitIntInfoVmcs(pVCpu, pVmxTransient); … … 11247 11249 } 11248 11250 11249 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTAT E(pVCpu).StatExitXcptNmi, y3);11251 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTATS(pVCpu).StatExitXcptNmi, y3); 11250 11252 return rcStrict; 11251 11253 } … … 11264 11266 11265 11267 /* Evaluate and deliver pending events and resume guest execution. */ 11266 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitIntWindow);11268 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitIntWindow); 11267 11269 return VINF_SUCCESS; 11268 11270 } … … 11647 11649 11648 11650 if (rc != VINF_SUCCESS) 11649 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatSwitchHltToR3);11651 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatSwitchHltToR3); 11650 11652 return rc; 11651 11653 } … … 11678 11680 PVMCC pVM = pVCpu->CTX_SUFF(pVM); 11679 11681 bool fTimersPending = TMTimerPollBool(pVM, pVCpu); 11680 STAM_REL_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitPreemptTimer);11682 STAM_REL_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitPreemptTimer); 11681 11683 return fTimersPending ? VINF_EM_RAW_TIMER_PENDING : VINF_SUCCESS; 11682 11684 } … … 11951 11953 11952 11954 VBOXSTRICTRC rcStrict = IEMExecDecodedRdmsr(pVCpu, pVmxTransient->cbExitInstr); 11953 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitRdmsr);11955 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitRdmsr); 11954 11956 if (rcStrict == VINF_SUCCESS) 11955 11957 ASMAtomicUoOrU64(&VCPU_2_VMXSTATE(pVCpu).fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS); … … 12001 12003 12002 12004 VBOXSTRICTRC rcStrict = IEMExecDecodedWrmsr(pVCpu, pVmxTransient->cbExitInstr); 12003 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitWrmsr);12005 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitWrmsr); 12004 12006 12005 12007 if (rcStrict == VINF_SUCCESS) … … 12147 12149 * entry so we can just continue execution here. 12148 12150 */ 12149 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitTprBelowThreshold);12151 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitTprBelowThreshold); 12150 12152 return VINF_SUCCESS; 12151 12153 } … … 12164 12166 { 12165 12167 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient); 12166 STAM_PROFILE_ADV_START(&VCPU_2_VMXSTAT E(pVCpu).StatExitMovCRx, y2);12168 STAM_PROFILE_ADV_START(&VCPU_2_VMXSTATS(pVCpu).StatExitMovCRx, y2); 12167 12169 12168 12170 PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo; … … 12322 12324 Assert(rcStrict != VINF_IEM_RAISED_XCPT); 12323 12325 12324 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTAT E(pVCpu).StatExitMovCRx, y2);12326 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTATS(pVCpu).StatExitMovCRx, y2); 12325 12327 NOREF(pVM); 12326 12328 return rcStrict; … … 12335 12337 { 12336 12338 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient); 12337 STAM_PROFILE_ADV_START(&VCPU_2_VMXSTAT E(pVCpu).StatExitIO, y1);12339 STAM_PROFILE_ADV_START(&VCPU_2_VMXSTATS(pVCpu).StatExitIO, y1); 12338 12340 12339 12341 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx; … … 12429 12431 { 12430 12432 rcStrict = IOMIOPortWrite(pVM, pVCpu, uIOPort, pCtx->eax & uAndVal, cbValue); 12431 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitIOWrite);12433 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitIOWrite); 12432 12434 #ifdef IN_RING0 12433 12435 if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE … … 12450 12452 rcStrict = EMRZSetPendingIoPortRead(pVCpu, uIOPort, cbInstr, cbValue); 12451 12453 #endif 12452 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitIORead);12454 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitIORead); 12453 12455 } 12454 12456 } … … 12487 12489 || DBGFBpIsHwIoArmed(pVM))) 12488 12490 { 12489 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatDRxIoCheck);12491 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatDRxIoCheck); 12490 12492 12491 12493 #ifdef IN_RING0 … … 12544 12546 } 12545 12547 #endif 12546 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTAT E(pVCpu).StatExitIO, y1);12548 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTATS(pVCpu).StatExitIO, y1); 12547 12549 } 12548 12550 else … … 12553 12555 int rc2 = vmxHCImportGuestState(pVCpu, pVmcsInfo, HMVMX_CPUMCTX_EXTRN_ALL); 12554 12556 AssertRCReturn(rc2, rc2); 12555 STAM_COUNTER_INC(!fIOString ? fIOWrite ? &VCPU_2_VMXSTAT E(pVCpu).StatExitIOWrite : &VCPU_2_VMXSTATE(pVCpu).StatExitIORead12556 : fIOWrite ? &VCPU_2_VMXSTAT E(pVCpu).StatExitIOStringWrite : &VCPU_2_VMXSTATE(pVCpu).StatExitIOStringRead);12557 STAM_COUNTER_INC(!fIOString ? fIOWrite ? &VCPU_2_VMXSTATS(pVCpu).StatExitIOWrite : &VCPU_2_VMXSTATS(pVCpu).StatExitIORead 12558 : fIOWrite ? &VCPU_2_VMXSTATS(pVCpu).StatExitIOStringWrite : &VCPU_2_VMXSTATS(pVCpu).StatExitIOStringRead); 12557 12559 Log4(("IOExit/%u: %04x:%08RX64: %s%s%s %#x LB %u -> EMHistoryExec\n", 12558 12560 pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, … … 12608 12610 Log4Func(("Pending event. uIntType=%#x uVector=%#x\n", VMX_IDT_VECTORING_INFO_TYPE(pVmxTransient->uIdtVectoringInfo), 12609 12611 VMX_IDT_VECTORING_INFO_VECTOR(pVmxTransient->uIdtVectoringInfo))); 12610 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitTaskSwitch);12612 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitTaskSwitch); 12611 12613 return VINF_EM_RAW_INJECT_TRPM_EVENT; 12612 12614 } … … 12614 12616 12615 12617 /* Fall back to the interpreter to emulate the task-switch. */ 12616 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitTaskSwitch);12618 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitTaskSwitch); 12617 12619 return VERR_EM_INTERPRETER; 12618 12620 } … … 12640 12642 { 12641 12643 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient); 12642 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitApicAccess);12644 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitApicAccess); 12643 12645 12644 12646 vmxHCReadExitIntInfoVmcs(pVCpu, pVmxTransient); … … 12657 12659 if (RT_UNLIKELY(VCPU_2_VMXSTATE(pVCpu).Event.fPending)) 12658 12660 { 12659 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatInjectInterpret);12661 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatInjectInterpret); 12660 12662 return VINF_EM_RAW_INJECT_TRPM_EVENT; 12661 12663 } … … 12717 12719 12718 12720 if (rcStrict != VINF_SUCCESS) 12719 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatSwitchApicAccessToR3);12721 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatSwitchApicAccessToR3); 12720 12722 return rcStrict; 12721 12723 } … … 12774 12776 vmxHCReadExitQualVmcs(pVCpu, pVmxTransient); 12775 12777 if (VMX_EXIT_QUAL_DRX_DIRECTION(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_DRX_DIRECTION_WRITE) 12776 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitDRxWrite);12778 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitDRxWrite); 12777 12779 else 12778 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitDRxRead);12779 #endif 12780 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatDRxContextSwitch);12780 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitDRxRead); 12781 #endif 12782 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatDRxContextSwitch); 12781 12783 return VINF_SUCCESS; 12782 12784 } … … 12802 12804 if (RT_SUCCESS(rc)) 12803 12805 ASMAtomicUoOrU64(&VCPU_2_VMXSTATE(pVCpu).fCtxChanged, HM_CHANGED_GUEST_DR7); 12804 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitDRxWrite);12806 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitDRxWrite); 12805 12807 } 12806 12808 else … … 12809 12811 VMX_EXIT_QUAL_DRX_GENREG(pVmxTransient->uExitQual), 12810 12812 VMX_EXIT_QUAL_DRX_REGISTER(pVmxTransient->uExitQual)); 12811 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitDRxRead);12813 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitDRxRead); 12812 12814 } 12813 12815 … … 12855 12857 else 12856 12858 { 12857 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatInjectInterpret);12859 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatInjectInterpret); 12858 12860 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX 12859 12861 /** @todo NSTVMX: Think about how this should be handled. */ … … 12965 12967 */ 12966 12968 if (VCPU_2_VMXSTATE(pVCpu).Event.fPending) 12967 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatInjectReflectNPF);12969 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatInjectReflectNPF); 12968 12970 } 12969 12971 else … … 13008 13010 { 13009 13011 /* Successfully synced our nested page tables. */ 13010 STAM_COUNTER_INC(&VCPU_2_VMXSTAT E(pVCpu).StatExitReasonNpf);13012 STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitReasonNpf); 13011 13013 ASMAtomicUoOrU64(&VCPU_2_VMXSTATE(pVCpu).fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS); 13012 13014 return VINF_SUCCESS; … … 13144 13146 HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason); 13145 13147 13146 STAM_PROFILE_ADV_START(&VCPU_2_VMXSTAT E(pVCpu).StatExitVmentry, z);13148 STAM_PROFILE_ADV_START(&VCPU_2_VMXSTATS(pVCpu).StatExitVmentry, z); 13147 13149 VBOXSTRICTRC rcStrict = IEMExecDecodedVmlaunchVmresume(pVCpu, pVmxTransient->cbExitInstr, VMXINSTRID_VMLAUNCH); 13148 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTAT E(pVCpu).StatExitVmentry, z);13150 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTATS(pVCpu).StatExitVmentry, z); 13149 13151 if (RT_LIKELY(rcStrict == VINF_SUCCESS)) 13150 13152 { … … 13290 13292 HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason); 13291 13293 13292 STAM_PROFILE_ADV_START(&VCPU_2_VMXSTAT E(pVCpu).StatExitVmentry, z);13294 STAM_PROFILE_ADV_START(&VCPU_2_VMXSTATS(pVCpu).StatExitVmentry, z); 13293 13295 VBOXSTRICTRC rcStrict = IEMExecDecodedVmlaunchVmresume(pVCpu, pVmxTransient->cbExitInstr, VMXINSTRID_VMRESUME); 13294 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTAT E(pVCpu).StatExitVmentry, z);13296 STAM_PROFILE_ADV_STOP(&VCPU_2_VMXSTATS(pVCpu).StatExitVmentry, z); 13295 13297 if (RT_LIKELY(rcStrict == VINF_SUCCESS)) 13296 13298 {
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