VirtualBox

Changeset 92426 in vbox for trunk/src/VBox/VMM/include


Ignore:
Timestamp:
Nov 15, 2021 1:25:47 PM (3 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
148282
Message:

VMM: Nested VMX: bugref:10092 Refactor PGMGstGetPage and related API and functions to pass more info back to callers on page walk failures.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/include/PGMInternal.h

    r92420 r92426  
    3737#include <VBox/vmm/gmm.h>
    3838#include <VBox/vmm/hm.h>
    39 #include <VBox/vmm/hm_vmx.h>
    4039#include <iprt/asm.h>
    4140#include <iprt/assert.h>
    … …  
    23312330
    23322331
    2333 /** @name PGMPTATTRS
    2334  *
    2335  * PGM page-table attributes.
    2336  *
    2337  * This is VirtualBox's combined page table attributes. It combines regular page
    2338  * table and Intel EPT attributes. It's 64-bit in size so there's ample room for
    2339  * bits added in the future to EPT or regular page tables (for e.g. Protection Key).
    2340  *
    2341  * The following bits map 1:1 (shifted by PGM_PTATTRS_EPT_SHIFT) to the Intel EPT
    2342  * attributes as these are unique to EPT and fit within 64-bits despite the shift:
    2343  *   - EPT_R         : Read access.
    2344  *   - EPT_W         : Write access.
    2345  *   - EPT_X_SUPER   : Execute or execute for supervisor-mode linear addr access.
    2346  *   - EPT_MEMTYPE   : EPT memory type.
    2347  *   - EPT_IGNORE_PAT: Ignore PAT memory type.
    2348  *   - EPT_X_USER    : Execute access for user-mode linear addresses.
    2349  *
    2350  * For regular page tables, the R bit is always 1 (same as P bit).
    2351  * For Intel EPT, the EPT_R and EPT_W bits are copied to R and W bits respectively.
    2352  *
    2353  * The following EPT attributes are mapped to the following positions because they
    2354  * exist in the regular page tables at these positions OR are exclusive to EPT and
    2355  * have been mapped to arbitrarily chosen positions:
    2356  *   - EPT_A               : Accessed                (EPT bit  8 maps to bit  5).
    2357  *   - EPT_D               : Dirty                   (EPT bit  9 maps to bit  6).
    2358  *   - EPT_SUPER_SHW_STACK : Supervisor Shadow Stack (EPT bit 60 maps to bit 24).
    2359  *   - EPT_SUPPRESS_VE_XCPT: Suppress \#VE exception (EPT bit 63 maps to bit 25).
    2360  *
    2361  * Bits 12, 11:9 and 43 are deliberately kept unused (correspond to bit PS and bits
    2362  * 11:9 in the regular page-table structures and to bit 11 in the EPT structures
    2363  * respectively) as bit 12 is the page-size bit and bits 11:9 are reserved for
    2364  * use by software and we may want to use/preserve them in the future.
    2365  *
    2366  * @{ */
    2367 typedef uint64_t PGMPTATTRS;
    2368 /** Pointer to a PGMPTATTRS type. */
    2369 typedef PGMPTATTRS *PPGMPTATTRS;
    2370 
    2371 /** Read bit (always 1 for regular PT, copy of EPT_R for EPT). */
    2372 #define PGM_PTATTRS_R_SHIFT                         0
    2373 #define PGM_PTATTRS_R_MASK                          RT_BIT_64(PGM_PTATTRS_R_SHIFT)
    2374 /** Write access bit (aka read/write bit for regular PT). */
    2375 #define PGM_PTATTRS_W_SHIFT                         1
    2376 #define PGM_PTATTRS_W_MASK                          RT_BIT_64(PGM_PTATTRS_W_SHIFT)
    2377 /** User-mode access bit. */
    2378 #define PGM_PTATTRS_US_SHIFT                        2
    2379 #define PGM_PTATTRS_US_MASK                         RT_BIT_64(PGM_PTATTRS_US_SHIFT)
    2380 /** Write through cache bit. */
    2381 #define PGM_PTATTRS_PWT_SHIFT                       3
    2382 #define PGM_PTATTRS_PWT_MASK                        RT_BIT_64(PGM_PTATTRS_PWT_SHIFT)
    2383 /** Cache disabled bit. */
    2384 #define PGM_PTATTRS_PCD_SHIFT                       4
    2385 #define PGM_PTATTRS_PCD_MASK                        RT_BIT_64(PGM_PTATTRS_PCD_SHIFT)
    2386 /** Accessed bit. */
    2387 #define PGM_PTATTRS_A_SHIFT                         5
    2388 #define PGM_PTATTRS_A_MASK                          RT_BIT_64(PGM_PTATTRS_A_SHIFT)
    2389 /** Dirty bit. */
    2390 #define PGM_PTATTRS_D_SHIFT                         6
    2391 #define PGM_PTATTRS_D_MASK                          RT_BIT_64(PGM_PTATTRS_D_SHIFT)
    2392 /** The PAT bit. */
    2393 #define PGM_PTATTRS_PAT_SHIFT                       7
    2394 #define PGM_PTATTRS_PAT_MASK                        RT_BIT_64(PGM_PTATTRS_PAT_SHIFT)
    2395 /** The global bit. */
    2396 #define PGM_PTATTRS_G_SHIFT                         8
    2397 #define PGM_PTATTRS_G_MASK                          RT_BIT_64(PGM_PTATTRS_G_SHIFT)
    2398 /** Reserved (bits 12:9) unused. */
    2399 #define PGM_PTATTRS_RSVD_12_9_SHIFT                 9
    2400 #define PGM_PTATTRS_RSVD_12_9_MASK                  UINT64_C(0x0000000000001e00)
    2401 /** Read access bit - EPT only. */
    2402 #define PGM_PTATTRS_EPT_R_SHIFT                     13
    2403 #define PGM_PTATTRS_EPT_R_MASK                      RT_BIT_64(PGM_PTATTRS_EPT_R_SHIFT)
    2404 /** Write access bit - EPT only. */
    2405 #define PGM_PTATTRS_EPT_W_SHIFT                     14
    2406 #define PGM_PTATTRS_EPT_W_MASK                      RT_BIT_64(PGM_PTATTRS_EPT_W_SHIFT)
    2407 /** Execute or execute access for supervisor-mode linear addresses - EPT only. */
    2408 #define PGM_PTATTRS_EPT_X_SUPER_SHIFT               15
    2409 #define PGM_PTATTRS_EPT_X_SUPER_MASK                RT_BIT_64(PGM_PTATTRS_EPT_X_SUPER_SHIFT)
    2410 /** EPT memory type - EPT only. */
    2411 #define PGM_PTATTRS_EPT_MEMTYPE_SHIFT               16
    2412 #define PGM_PTATTRS_EPT_MEMTYPE_MASK                UINT64_C(0x0000000000070000)
    2413 /** Ignore PAT memory type - EPT only. */
    2414 #define PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT            19
    2415 #define PGM_PTATTRS_EPT_IGNORE_PAT_MASK             RT_BIT_64(PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT)
    2416 /** Reserved (bits 22:20) unused. */
    2417 #define PGM_PTATTRS_RSVD_22_20_SHIFT                20
    2418 #define PGM_PTATTRS_RSVD_22_20_MASK                 UINT64_C(0x0000000000700000)
    2419 /** Execute access for user-mode linear addresses - EPT only. */
    2420 #define PGM_PTATTRS_EPT_X_USER_SHIFT                23
    2421 #define PGM_PTATTRS_EPT_X_USER_MASK                 RT_BIT_64(PGM_PTATTRS_EPT_X_USER_SHIFT)
    2422 /** Reserved (bit 23) - unused. */
    2423 #define PGM_PTATTRS_RSVD_23_SHIFT                   24
    2424 #define PGM_PTATTRS_RSVD_23_MASK                    UINT64_C(0x0000000001000000)
    2425 /** Supervisor shadow stack - EPT only. */
    2426 #define PGM_PTATTRS_EPT_SUPER_SHW_STACK_SHIFT       25
    2427 #define PGM_PTATTRS_EPT_SUPER_SHW_STACK_MASK        RT_BIT_64(PGM_PTATTRS_EPT_SUPER_SHW_STACK_SHIFT)
    2428 /** Suppress \#VE exception - EPT only. */
    2429 #define PGM_PTATTRS_EPT_SUPPRESS_VE_XCPT_SHIFT      26
    2430 #define PGM_PTATTRS_EPT_SUPPRESS_VE_XCPT_MASK       RT_BIT_64(PGM_PTATTRS_EPT_SUPPRESS_VE_XCPT_SHIFT)
    2431 /** Reserved (bits 62:27) - unused. */
    2432 #define PGM_PTATTRS_RSVD_62_27_SHIFT                27
    2433 #define PGM_PTATTRS_RSVD_62_27_MASK                 UINT64_C(0x7ffffffff8000000)
    2434 /** No-execute bit. */
    2435 #define PGM_PTATTRS_NX_SHIFT                        63
    2436 #define PGM_PTATTRS_NX_MASK                         RT_BIT_64(PGM_PTATTRS_NX_SHIFT)
    2437 
    2438 RT_BF_ASSERT_COMPILE_CHECKS(PGM_PTATTRS_, UINT64_C(0), UINT64_MAX,
    2439                             (R, W, US, PWT, PCD, A, D, PAT, G, RSVD_12_9, EPT_R, EPT_W, EPT_X_SUPER, EPT_MEMTYPE, EPT_IGNORE_PAT,
    2440                              RSVD_22_20, EPT_X_USER, RSVD_23, EPT_SUPER_SHW_STACK, EPT_SUPPRESS_VE_XCPT, RSVD_62_27, NX));
    2441 
    2442 /** The bit position where the EPT specific attributes begin. */
    2443 #define PGM_PTATTRS_EPT_SHIFT                       PGM_PTATTRS_EPT_R_SHIFT
    2444 /** The mask of EPT bits (bits 26:ATTR_SHIFT). In the future we might choose to
    2445  *  use higher unused bits for something else, in that case adjust this mask. */
    2446 #define PGM_PTATTRS_EPT_MASK                        UINT64_C(0x0000000007ffe000)
    2447 
    2448 /** The mask of all PGM page attribute bits for regular page-tables. */
    2449 #define PGM_PTATTRS_PT_VALID_MASK                   (  PGM_PTATTRS_R_MASK \
    2450                                                      | PGM_PTATTRS_W_MASK \
    2451                                                      | PGM_PTATTRS_US_MASK \
    2452                                                      | PGM_PTATTRS_PWT_MASK \
    2453                                                      | PGM_PTATTRS_PCD_MASK \
    2454                                                      | PGM_PTATTRS_A_MASK \
    2455                                                      | PGM_PTATTRS_D_MASK \
    2456                                                      | PGM_PTATTRS_PAT_MASK \
    2457                                                      | PGM_PTATTRS_G_MASK \
    2458                                                      | PGM_PTATTRS_NX_MASK)
    2459 
    2460 /** The mask of all PGM page attribute bits for EPT. */
    2461 #define PGM_PTATTRS_EPT_VALID_MASK                  (  PGM_PTATTRS_R_MASK \
    2462                                                      | PGM_PTATTRS_W_MASK \
    2463                                                      | PGM_PTATTRS_A_MASK \
    2464                                                      | PGM_PTATTRS_D_MASK \
    2465                                                      | PGM_PTATTRS_EPT_R_MASK \
    2466                                                      | PGM_PTATTRS_EPT_W_MASK \
    2467                                                      | PGM_PTATTRS_EPT_X_SUPER \
    2468                                                      | PGM_PTATTRS_EPT_MEMTYPE \
    2469                                                      | PGM_PTATTRS_EPT_IGNORE_PAT \
    2470                                                      | PGM_PTATTRS_EPT_X_USER \
    2471                                                      | PGM_PTATTRS_EPT_SUPER_SHW_STACK \
    2472                                                      | PGM_PTATTRS_EPT_SUPPRESS_VE_XCPT)
    2473 
    2474 /* The mask of all PGM page attribute bits (combined). */
    2475 #define PGM_PTATTRS_VALID_MASK                      (PGM_PTATTRS_PT_VALID_MASK | PGM_PTATTRS_PT_VALID_MASK)
    2476 
    2477 /* Verify bits match the regular PT bits. */
    2478 AssertCompile(PGM_PTATTRS_W_SHIFT   == X86_PTE_BIT_RW);
    2479 AssertCompile(PGM_PTATTRS_US_SHIFT  == X86_PTE_BIT_US);
    2480 AssertCompile(PGM_PTATTRS_PWT_SHIFT == X86_PTE_BIT_PWT);
    2481 AssertCompile(PGM_PTATTRS_PCD_SHIFT == X86_PTE_BIT_PCD);
    2482 AssertCompile(PGM_PTATTRS_A_SHIFT   == X86_PTE_BIT_A);
    2483 AssertCompile(PGM_PTATTRS_D_SHIFT   == X86_PTE_BIT_D);
    2484 AssertCompile(PGM_PTATTRS_PAT_SHIFT == X86_PTE_BIT_PAT);
    2485 AssertCompile(PGM_PTATTRS_G_SHIFT   == X86_PTE_BIT_G);
    2486 AssertCompile(PGM_PTATTRS_W_MASK    == X86_PTE_RW);
    2487 AssertCompile(PGM_PTATTRS_US_MASK   == X86_PTE_US);
    2488 AssertCompile(PGM_PTATTRS_PWT_MASK  == X86_PTE_PWT);
    2489 AssertCompile(PGM_PTATTRS_PCD_MASK  == X86_PTE_PCD);
    2490 AssertCompile(PGM_PTATTRS_A_MASK    == X86_PTE_A);
    2491 AssertCompile(PGM_PTATTRS_D_MASK    == X86_PTE_D);
    2492 AssertCompile(PGM_PTATTRS_PAT_MASK  == X86_PTE_PAT);
    2493 AssertCompile(PGM_PTATTRS_G_MASK    == X86_PTE_G);
    2494 
    2495 /* Verify those EPT bits that must map 1:1 (after shifting). */
    2496 AssertCompile(PGM_PTATTRS_EPT_R_SHIFT          - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_READ);
    2497 AssertCompile(PGM_PTATTRS_EPT_W_SHIFT          - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_WRITE);
    2498 AssertCompile(PGM_PTATTRS_EPT_X_SUPER_SHIFT    - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_EXECUTE);
    2499 AssertCompile(PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_IGNORE_PAT);
    2500 AssertCompile(PGM_PTATTRS_EPT_X_USER_SHIFT     - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_USER_EXECUTE);
    2501 /** @} */
    2502 
    2503 
    2504 /**
    2505  * Page fault guest state for the AMD64 paging mode.
    2506  */
    2507 typedef struct PGMPTWALKCORE
    2508 {
    2509     /** The guest virtual address that is being resolved by the walk
    2510      *  (input). */
    2511     RTGCPTR         GCPtr;
    2512 
    2513     /** The nested-guest physical address that is being resolved if this is a
    2514      *  second-level walk (input).
    2515      *  @remarks only valid if fIsSlat is set. */
    2516     RTGCPHYS        GCPhysNested;
    2517 
    2518     /** The guest physical address that is the result of the walk.
    2519      * @remarks only valid if fSucceeded is set. */
    2520     RTGCPHYS        GCPhys;
    2521 
    2522     /** Set if the walk succeeded, i.d. GCPhys is valid. */
    2523     bool            fSucceeded;
    2524     /** Whether this is a second-level translation. */
    2525     bool            fIsSlat;
    2526     /** Whether the linear address (GCPtr) is valid and thus the cause for the
    2527      *  second-level translation. */
    2528     bool            fIsLinearAddrValid;
    2529     /** The level problem arrised at.
    2530      * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
    2531      * level 8.  This is 0 on success. */
    2532     uint8_t         uLevel;
    2533     /** Set if the page isn't present. */
    2534     bool            fNotPresent;
    2535     /** Encountered a bad physical address. */
    2536     bool            fBadPhysAddr;
    2537     /** Set if there was reserved bit violations. */
    2538     bool            fRsvdError;
    2539     /** Set if it involves a big page (2/4 MB). */
    2540     bool            fBigPage;
    2541     /** Set if it involves a gigantic page (1 GB). */
    2542     bool            fGigantPage;
    2543     bool            afPadding[7];
    2544     /** The effective attributes, PGM_PTATTRS_XXX. */
    2545     PGMPTATTRS      fEffective;
    2546 } PGMPTWALKCORE;
    2547 
    25482332/**
    25492333 * Guest page table walk for the AMD64 mode.
    … …  
    25512335typedef struct PGMPTWALKGSTAMD64
    25522336{
    2553     /** The common core. */
    2554     PGMPTWALKCORE   Core;
    2555 
    25562337    PX86PML4        pPml4;
    25572338    PX86PML4E       pPml4e;
    … …  
    25802361typedef struct PGMPTWALKGSTEPT
    25812362{
    2582     /** The common core. */
    2583     PGMPTWALKCORE   Core;
    2584 
    25852363    PEPTPML4        pPml4;
    25862364    PEPTPML4E       pPml4e;
    … …  
    26092387typedef struct PGMPTWALKGSTPAE
    26102388{
    2611     /** The common core. */
    2612     PGMPTWALKCORE   Core;
    2613 
    26142389    PX86PDPT        pPdpt;
    26152390    PX86PDPE        pPdpe;
    … …  
    26342409typedef struct PGMPTWALKGST32BIT
    26352410{
    2636     /** The common core. */
    2637     PGMPTWALKCORE   Core;
    2638 
    26392411    PX86PD          pPd;
    26402412    PX86PDE         pPde;
    … …  
    26762448    union
    26772449    {
    2678         /** The page walker core - always valid. */
    2679         PGMPTWALKCORE       Core;
    26802450        /** The page walker for AMD64. */
    26812451        PGMPTWALKGSTAMD64   Amd64;
    … …  
    28662636    /** The guest mode type. */
    28672637    uint32_t                        uType;
    2868     DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
     2638    DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk));
    28692639    DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
    28702640    DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
    … …  
    39153685int             pgmGstLazyMapEptPml4(PVMCPUCC pVCpu, PEPTPML4 *ppPml4);
    39163686#endif
    3917 int             pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
    3918 int             pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
     3687int             pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
     3688int             pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
    39193689
    39203690# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
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