Changeset 92579 in vbox for trunk/src/VBox/VMM/VMMR3

Timestamp:

Nov 24, 2021 3:04:08 AM (3 years ago)

Author:

vboxsync

Message:

VMM/NEM-linux: Implemented the apic_base synchronization, ubuntu now boots with x2APIC. bugref:9044

File:

• trunk/src/VBox/VMM/VMMR3/NEMR3Native-linux.cpp (modified) (4 diffs)

trunk/src/VBox/VMM/VMMR3/NEMR3Native-linux.cpp

@@ -1236 +1236 @@
 
     /*
-     * Stuff that goes into kvm_run::s.regs.sregs:
-     */
-    /** @todo apic_base   */
-
+     * Stuff that goes into kvm_run::s.regs.sregs.
+     *
+     * Note! The apic_base can be ignored because we gets all MSR writes to it
+     *       and VBox always keeps the correct value.
+     */
     bool fMaybeChangedMode = false;
     bool fUpdateCr3        = false;
@@ -1337 +1338 @@
             }
         }
-
-        /** @todo apic_base   */
 #undef NEM_LNX_IMPORT_SEG
     }
@@ -1643 +1642 @@
     /*
      * Stuff that goes into kvm_run::s.regs.sregs:
-     */
-    /** @todo apic_base   */
-    if (fExtrn & (  CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_TABLE_MASK | CPUMCTX_EXTRN_CR_MASK
-                  | CPUMCTX_EXTRN_EFER      | CPUMCTX_EXTRN_APIC_TPR))
-    {
+     *
+     * The APIC base register updating is a little suboptimal... But at least
+     * VBox always has the right base register value, so it's one directional.
+     */
+    uint64_t const uApicBase = APICGetBaseMsrNoCheck(pVCpu);
+    if (   (fExtrn & (  CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_TABLE_MASK | CPUMCTX_EXTRN_CR_MASK
+                      | CPUMCTX_EXTRN_EFER      | CPUMCTX_EXTRN_APIC_TPR))
+        || uApicBase != pVCpu->nem.s.uKvmApicBase)
+    {
+        if ((pVCpu->nem.s.uKvmApicBase ^ uApicBase) & MSR_IA32_APICBASE_EN)
+            Log(("NEM/%u: APICBASE_EN changed %#010RX64 -> %#010RX64\n", pVCpu->idCpu, pVCpu->nem.s.uKvmApicBase, uApicBase));
+        pRun->s.regs.sregs.apic_base = uApicBase;
+        pVCpu->nem.s.uKvmApicBase    = uApicBase;
+
+        if (fExtrn & CPUMCTX_EXTRN_APIC_TPR)
+            pRun->s.regs.sregs.cr8   = CPUMGetGuestCR8(pVCpu);
+
 #define NEM_LNX_EXPORT_SEG(a_KvmSeg, a_CtxSeg) do { \
             (a_KvmSeg).base     = (a_CtxSeg).u64Base; \
@@ -1713 +1724 @@
                 pRun->s.regs.sregs.cr4   = pCtx->cr4;
         }
-        if (fExtrn & CPUMCTX_EXTRN_APIC_TPR)
-            pRun->s.regs.sregs.cr8    = CPUMGetGuestCR8(pVCpu);
         if (fExtrn & CPUMCTX_EXTRN_EFER)
             pRun->s.regs.sregs.efer   = pCtx->msrEFER;
-
-        /** @todo apic_base   */
 
         RT_ZERO(pRun->s.regs.sregs.interrupt_bitmap); /* this is an alternative interrupt injection interface */