Index: trunk/src/VBox/VMM/VMMAll/PGMAllGstSlatEpt.cpp.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/PGMAllGstSlatEpt.cpp.h	(revision 93458)
+++ trunk/src/VBox/VMM/VMMAll/PGMAllGstSlatEpt.cpp.h	(revision 93459)
@@ -19,12 +19,11 @@
 DECLINLINE(bool) PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(PCVMCPUCC pVCpu, uint64_t uEntry)
 {
-    if (!(uEntry & VMX_BF_EPT_PT_READ_MASK))
-    {
-        if (uEntry & VMX_BF_EPT_PT_WRITE_MASK)
+    if (!(uEntry & EPT_E_READ))
+    {
+        if (uEntry & EPT_E_WRITE)
             return false;
-
         Assert(!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt);
         if (   !RT_BF_GET(pVCpu->pgm.s.uEptVpidCapMsr, VMX_BF_EPT_VPID_CAP_EXEC_ONLY)
-            && (uEntry & VMX_BF_EPT_PT_EXECUTE_MASK))
+            && (uEntry & EPT_E_EXECUTE))
             return false;
     }
@@ -49,9 +48,10 @@
     static PGMWALKFAIL const s_afEptViolations[] = { PGM_WALKFAIL_EPT_VIOLATION, PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE };
     uint8_t const fEptVeSupported  = pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxEptXcptVe;
-    uint8_t const idxViolationType = fEptVeSupported & !RT_BF_GET(uEntry, VMX_BF_EPT_PT_SUPPRESS_VE);
+    uint8_t const fConvertible     = RT_BOOL(uLevel == 1 || (uEntry & EPT_E_BIT_LEAF));
+    uint8_t const idxViolationType = fEptVeSupported & fConvertible & !RT_BF_GET(uEntry, VMX_BF_EPT_PT_SUPPRESS_VE);
 
     pWalk->fNotPresent = true;
     pWalk->uLevel      = uLevel;
-    pWalk->fFailed    |= s_afEptViolations[idxViolationType];
+    pWalk->fFailed     = s_afEptViolations[idxViolationType];
     return VERR_PAGE_TABLE_NOT_PRESENT;
 }
@@ -63,19 +63,15 @@
     pWalk->fBadPhysAddr = true;
     pWalk->uLevel       = uLevel;
-    pWalk->fFailed     |= PGM_WALKFAIL_EPT_VIOLATION;
+    pWalk->fFailed      = PGM_WALKFAIL_EPT_VIOLATION;
     return VERR_PAGE_TABLE_NOT_PRESENT;
 }
 
 
-DECLINLINE(int) PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint64_t uEntry, uint8_t uLevel)
-{
-    static PGMWALKFAIL const s_afEptViolations[] = { PGM_WALKFAIL_EPT_VIOLATION, PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE };
-    uint8_t const fEptVeSupported  = pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxEptXcptVe;
-    uint8_t const fConvertible     = RT_BOOL(uLevel == 1 || (uEntry & EPT_E_BIT_LEAF));
-    uint8_t const idxViolationType = fEptVeSupported & fConvertible & !RT_BF_GET(uEntry, VMX_BF_EPT_PT_SUPPRESS_VE);
-
-    pWalk->fRsvdError  = true;
-    pWalk->uLevel      = uLevel;
-    pWalk->fFailed    |= s_afEptViolations[idxViolationType];
+DECLINLINE(int) PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint8_t uLevel)
+{
+    NOREF(pVCpu);
+    pWalk->fRsvdError = true;
+    pWalk->uLevel     = uLevel;
+    pWalk->fFailed    = PGM_WALKFAIL_EPT_MISCONFIG;
     return VERR_PAGE_TABLE_NOT_PRESENT;
 }
@@ -141,8 +137,8 @@
     {
         /*
-         * Start with reading the EPT PML4E pointer.
+         * EPTP.
          *
-         * We currently only support 4 level EPT paging.
-         * EPT 5 level paging was documented at some point (bit 7 of MSR_IA32_VMX_EPT_VPID_CAP)
+         * We currently only support 4-level EPT paging.
+         * EPT 5-level paging was documented at some point (bit 7 of MSR_IA32_VMX_EPT_VPID_CAP)
          * but for some reason seems to have been removed from subsequent specs.
          */
@@ -165,6 +161,8 @@
         else return PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(pVCpu, pWalk, Pml4e.u, 4);
 
-        if (RT_LIKELY(GST_IS_PML4E_VALID(pVCpu, Pml4e))) { /* likely */ }
-        else return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, Pml4e.u, 4);
+        if (RT_LIKELY(   GST_IS_PML4E_VALID(pVCpu, Pml4e)
+                      && PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pml4e.u)))
+        { /* likely */ }
+        else return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, 4);
 
         Assert(!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt);
@@ -196,6 +194,7 @@
         else return PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(pVCpu, pWalk, Pdpte.u, 3);
 
-        /* The order of the following 2 "if" statements matter. */
-        if (GST_IS_PDPE_VALID(pVCpu, Pdpte))
+        /* The order of the following "if" and "else if" statements matter. */
+        if (   GST_IS_PDPE_VALID(pVCpu, Pdpte)
+            && PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pdpte.u))
         {
             uint64_t const fEptAttrs     = Pdpte.u & EPT_PDPTE_ATTR_MASK;
@@ -211,4 +210,5 @@
         }
         else if (   GST_IS_BIG_PDPE_VALID(pVCpu, Pdpte)
+                 && PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pdpte.u)
                  && PGM_GST_SLAT_NAME_EPT(WalkIsMemTypeValid)(Pdpte.u, 3))
         {
@@ -235,5 +235,5 @@
             return VINF_SUCCESS;
         }
-        else return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, Pdpte.u, 3);
+        else return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, 3);
 
         int const rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pdpte.u & EPT_PDPTE_PG_MASK, &pGstWalk->pPd);
@@ -253,6 +253,7 @@
         else return PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(pVCpu, pWalk, Pde.u, 2);
 
-        /* The order of the following 2 "if" statements matter. */
-        if (GST_IS_PDE_VALID(pVCpu, Pde))
+        /* The order of the following "if" and "else if" statements matter. */
+        if (   GST_IS_PDE_VALID(pVCpu, Pde)
+            && PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pde.u))
         {
             uint64_t const fEptAttrs     = Pde.u & EPT_PDE_ATTR_MASK;
@@ -269,4 +270,5 @@
         }
         else if (   GST_IS_BIG_PDE_VALID(pVCpu, Pde)
+                 && PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pde.u)
                  && PGM_GST_SLAT_NAME_EPT(WalkIsMemTypeValid)(Pde.u, 2))
         {
@@ -293,5 +295,5 @@
             return VINF_SUCCESS;
         }
-        else return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, Pde.u, 2);
+        else return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, 2);
 
         int const rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GST_GET_PDE_GCPHYS(Pde), &pGstWalk->pPt);
@@ -312,8 +314,9 @@
 
         if (   GST_IS_PTE_VALID(pVCpu, Pte)
+            && PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pte.u)
             && PGM_GST_SLAT_NAME_EPT(WalkIsMemTypeValid)(Pte.u, 1))
-        { /* likely*/  }
+        { /* likely*/ }
         else
-            return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, Pte.u, 1);
+            return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, 1);
 
         uint64_t const fEptAttrs     = Pte.u & EPT_PTE_ATTR_MASK;
