- Timestamp:
- Jun 3, 2008 11:56:19 AM (17 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/VMM/VMMAll/EMAll.cpp
r9345 r9349 55 55 typedef DECLCALLBACK(uint32_t) PFN_EMULATE_PARAM2(uint32_t *pu32Param1, size_t val2); 56 56 typedef DECLCALLBACK(uint32_t) PFN_EMULATE_PARAM3(uint32_t *pu32Param1, uint32_t val2, size_t val3); 57 typedef DECLCALLBACK(int) FNEMULATELOCKPARAM2(RT GCPTR GCPtrParam1, RTGCUINTREGVal2, RTGCUINTREG32 *pf);57 typedef DECLCALLBACK(int) FNEMULATELOCKPARAM2(RTRCPTR GCPtrParam1, RTGCUINTREG32 Val2, RTGCUINTREG32 *pf); 58 58 typedef FNEMULATELOCKPARAM2 *PFNEMULATELOCKPARAM2; 59 typedef DECLCALLBACK(int) FNEMULATELOCKPARAM3(RT GCPTR GCPtrParam1, RTGCUINTREGVal2, size_t cb, RTGCUINTREG32 *pf);59 typedef DECLCALLBACK(int) FNEMULATELOCKPARAM3(RTRCPTR GCPtrParam1, RTGCUINTREG32 Val2, size_t cb, RTGCUINTREG32 *pf); 60 60 typedef FNEMULATELOCKPARAM3 *PFNEMULATELOCKPARAM3; 61 61 … … 367 367 switch (pCpu->pCurInstr->opcode) 368 368 { 369 case OP_XOR: return "Xor"; 369 case OP_XCHG: return "Xchg"; 370 case OP_DEC: return "Dec"; 371 case OP_INC: return "Inc"; 372 case OP_POP: return "Pop"; 370 373 case OP_OR: return "Or"; 371 374 case OP_AND: return "And"; 375 case OP_MOV: return "Mov"; 376 case OP_INVLPG: return "InvlPg"; 377 case OP_CPUID: return "CpuId"; 378 case OP_MOV_CR: return "MovCRx"; 379 case OP_MOV_DR: return "MovDRx"; 380 case OP_LLDT: return "LLdt"; 381 case OP_CLTS: return "Clts"; 382 case OP_MONITOR: return "Monitor"; 383 case OP_MWAIT: return "MWait"; 384 case OP_RDMSR: return "Rdmsr"; 385 case OP_WRMSR: return "Wrmsr"; 386 case OP_ADC: return "Adc"; 387 case OP_BTC: return "Btc"; 388 case OP_RDTSC: return "Rdtsc"; 389 case OP_STI: return "Sti"; 390 case OP_XADD: return "XAdd"; 391 case OP_HLT: return "Hlt"; 392 case OP_IRET: return "Iret"; 393 case OP_CMPXCHG: return "CmpXchg"; 394 case OP_CMPXCHG8B: return "CmpXchg8b"; 395 case OP_MOVNTPS: return "MovNTPS"; 396 case OP_STOSWD: return "StosWD"; 397 case OP_WBINVD: return "WbInvd"; 398 case OP_XOR: return "Xor"; 372 399 case OP_BTR: return "Btr"; 373 400 case OP_BTS: return "Bts"; 374 401 default: 375 AssertMsgFailed(("%d\n", pCpu->pCurInstr->opcode));402 Log(("Unknown opcode %d\n", pCpu->pCurInstr->opcode)); 376 403 return "???"; 377 404 } … … 813 840 /* Register and immediate data == PARMTYPE_IMMEDIATE */ 814 841 AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER); 815 RTGCUINTREG ValPar2 = param2.val.val32;842 RTGCUINTREG32 ValPar2 = param2.val.val32; 816 843 817 844 /* Try emulate it with a one-shot #PF handler in place. */ … … 820 847 RTGCUINTREG32 eflags = 0; 821 848 MMGCRamRegisterTrapHandler(pVM); 822 rc = pfnEmulate( GCPtrPar1, ValPar2, pCpu->param2.size, &eflags);849 rc = pfnEmulate((RTRCPTR)GCPtrPar1, ValPar2, pCpu->param2.size, &eflags); 823 850 MMGCRamDeregisterTrapHandler(pVM); 824 851 … … 1059 1086 uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate) 1060 1087 { 1088 return VERR_EM_INTERPRETER; 1061 1089 OP_PARAMVAL param1, param2; 1062 1090 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, ¶m1, PARAM_DEST); … … 1077 1105 /* Register and immediate data == PARMTYPE_IMMEDIATE */ 1078 1106 AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER); 1079 RTGCUINTREG ValPar2 = param2.val.val32;1107 RTGCUINTREG32 ValPar2 = param2.val.val32; 1080 1108 1081 1109 Log2(("emInterpretLockBitTest %s: pvFault=%VGv GCPtrPar1=%RGv imm=%RGr\n", emGetMnemonic(pCpu), pvFault, GCPtrPar1, ValPar2)); … … 1094 1122 RTGCUINTREG32 eflags = 0; 1095 1123 MMGCRamRegisterTrapHandler(pVM); 1096 rc = pfnEmulate( GCPtrPar1, ValPar2, &eflags);1124 rc = pfnEmulate((RTRCPTR)GCPtrPar1, ValPar2, &eflags); 1097 1125 MMGCRamDeregisterTrapHandler(pVM); 1098 1126 … … 2289 2317 2290 2318 int rc; 2319 #if defined(IN_GC) && (defined(VBOX_STRICT) || defined(LOG_ENABLED)) 2320 LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pCpu))); 2321 #endif 2291 2322 switch (pCpu->pCurInstr->opcode) 2292 2323 {
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