- Timestamp:
- Jan 31, 2022 10:17:19 PM (3 years ago)
- Location:
- trunk/src/VBox
- Files:
-
- 16 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/HostDrivers/Support/SUPDrv.cpp
r93387 r93515 4301 4301 uint32_t uMaxLeaf, uVendorEbx, uVendorEcx, uVendorEdx; 4302 4302 ASMCpuId(0, &uMaxLeaf, &uVendorEbx, &uVendorEcx, &uVendorEdx); 4303 if ( ASMIsValidStdRange(uMaxLeaf))4303 if (RTX86IsValidStdRange(uMaxLeaf)) 4304 4304 { 4305 4305 /* Query the standard CPUID leaf. */ … … 4308 4308 4309 4309 /* Check if the vendor is Intel (or compatible). */ 4310 if ( ASMIsIntelCpuEx(uVendorEbx, uVendorEcx, uVendorEdx)4311 || ASMIsViaCentaurCpuEx(uVendorEbx, uVendorEcx, uVendorEdx)4312 || ASMIsShanghaiCpuEx(uVendorEbx, uVendorEcx, uVendorEdx))4310 if ( RTX86IsIntelCpu(uVendorEbx, uVendorEcx, uVendorEdx) 4311 || RTX86IsViaCentaurCpu(uVendorEbx, uVendorEcx, uVendorEdx) 4312 || RTX86IsShanghaiCpu(uVendorEbx, uVendorEcx, uVendorEdx)) 4313 4313 { 4314 4314 /* Check VT-x support. In addition, VirtualBox requires MSR and FXSAVE/FXRSTOR to function. */ … … 4324 4324 4325 4325 /* Check if the vendor is AMD (or compatible). */ 4326 if ( ASMIsAmdCpuEx(uVendorEbx, uVendorEcx, uVendorEdx)4327 || ASMIsHygonCpuEx(uVendorEbx, uVendorEcx, uVendorEdx))4326 if ( RTX86IsAmdCpu(uVendorEbx, uVendorEcx, uVendorEdx) 4327 || RTX86IsHygonCpu(uVendorEbx, uVendorEcx, uVendorEdx)) 4328 4328 { 4329 4329 uint32_t fExtFeatEcx, uExtMaxId; … … 4332 4332 4333 4333 /* Check AMD-V support. In addition, VirtualBox requires MSR and FXSAVE/FXRSTOR to function. */ 4334 if ( ASMIsValidExtRange(uExtMaxId)4334 if ( RTX86IsValidExtRange(uExtMaxId) 4335 4335 && uExtMaxId >= 0x8000000a 4336 4336 && (fExtFeatEcx & X86_CPUID_AMD_FEATURE_ECX_SVM) … … 4428 4428 uint32_t uMaxId, uVendorEBX, uVendorECX, uVendorEDX; 4429 4429 ASMCpuId(0, &uMaxId, &uVendorEBX, &uVendorECX, &uVendorEDX); 4430 Assert( ASMIsValidStdRange(uMaxId));4431 Assert( ASMIsIntelCpuEx( uVendorEBX, uVendorECX, uVendorEDX)4432 || ASMIsViaCentaurCpuEx(uVendorEBX, uVendorECX, uVendorEDX)4433 || ASMIsShanghaiCpuEx( uVendorEBX, uVendorECX, uVendorEDX));4430 Assert(RTX86IsValidStdRange(uMaxId)); 4431 Assert( RTX86IsIntelCpu( uVendorEBX, uVendorECX, uVendorEDX) 4432 || RTX86IsViaCentaurCpu(uVendorEBX, uVendorECX, uVendorEDX) 4433 || RTX86IsShanghaiCpu( uVendorEBX, uVendorECX, uVendorEDX)); 4434 4434 #endif 4435 4435 ASMCpuId(1, &uDummy, &uDummy, &fFeaturesECX, &uDummy); … … 4679 4679 ASMCpuId(1, &uTFMSEAX, &uDummy, &uDummy, &uDummy); 4680 4680 4681 if ( ASMIsValidStdRange(uMaxId))4681 if (RTX86IsValidStdRange(uMaxId)) 4682 4682 { 4683 4683 uint64_t uRevMsr; 4684 if ( ASMIsIntelCpuEx(uVendorEBX, uVendorECX, uVendorEDX))4684 if (RTX86IsIntelCpu(uVendorEBX, uVendorECX, uVendorEDX)) 4685 4685 { 4686 4686 /* Architectural MSR available on Pentium Pro and later. */ 4687 if ( ASMGetCpuFamily(uTFMSEAX) >= 6)4687 if (RTX86GetCpuFamily(uTFMSEAX) >= 6) 4688 4688 { 4689 4689 /* Revision is in the high dword. */ … … 4693 4693 } 4694 4694 } 4695 else if ( ASMIsAmdCpuEx(uVendorEBX, uVendorECX, uVendorEDX)4696 || ASMIsHygonCpuEx(uVendorEBX, uVendorECX, uVendorEDX))4695 else if ( RTX86IsAmdCpu(uVendorEBX, uVendorECX, uVendorEDX) 4696 || RTX86IsHygonCpu(uVendorEBX, uVendorECX, uVendorEDX)) 4697 4697 { 4698 4698 /* Not well documented, but at least all AMD64 CPUs support this. */ 4699 if ( ASMGetCpuFamily(uTFMSEAX) >= 15)4699 if (RTX86GetCpuFamily(uTFMSEAX) >= 15) 4700 4700 { 4701 4701 /* Revision is in the low dword. */ -
trunk/src/VBox/HostDrivers/Support/SUPDrvGip.cpp
r93115 r93515 199 199 /* The Intel CPU topology leaf: */ 200 200 uint32_t uOther = ASMCpuId_EAX(0); 201 if (uOther >= UINT32_C(0xb) && ASMIsValidStdRange(uOther))201 if (uOther >= UINT32_C(0xb) && RTX86IsValidStdRange(uOther)) 202 202 { 203 203 uint32_t uEax = 0; … … 220 220 /* The AMD leaf: */ 221 221 uOther = ASMCpuId_EAX(UINT32_C(0x80000000)); 222 if (uOther >= UINT32_C(0x8000001e) && ASMIsValidExtRange(uOther))222 if (uOther >= UINT32_C(0x8000001e) && RTX86IsValidExtRange(uOther)) 223 223 { 224 224 uOther = ASMGetApicIdExt8000001E(); … … 371 371 if (ASMHasCpuId()) 372 372 { 373 if ( ASMIsValidExtRange(ASMCpuId_EAX(UINT32_C(0x80000000)))373 if ( RTX86IsValidExtRange(ASMCpuId_EAX(UINT32_C(0x80000000))) 374 374 && (ASMCpuId_EDX(UINT32_C(0x80000001)) & X86_CPUID_EXT_FEATURE_EDX_RDTSCP) ) 375 375 { … … 406 406 idApic = UINT32_MAX; 407 407 uEax = ASMCpuId_EAX(0); 408 if (uEax >= UINT32_C(0xb) && ASMIsValidStdRange(uEax))408 if (uEax >= UINT32_C(0xb) && RTX86IsValidStdRange(uEax)) 409 409 { 410 410 #if defined(RT_OS_LINUX) || defined(RT_OS_FREEBSD) … … 430 430 431 431 uEax = ASMCpuId_EAX(UINT32_C(0x80000000)); 432 if (uEax >= UINT32_C(0x8000001e) && ASMIsValidExtRange(uEax))432 if (uEax >= UINT32_C(0x8000001e) && RTX86IsValidExtRange(uEax)) 433 433 { 434 434 #if defined(RT_OS_LINUX) || defined(RT_OS_FREEBSD) … … 1768 1768 { 1769 1769 uEAX = ASMCpuId_EAX(0x80000000); 1770 if ( ASMIsValidExtRange(uEAX) && uEAX >= 0x80000007)1770 if (RTX86IsValidExtRange(uEAX) && uEAX >= 0x80000007) 1771 1771 { 1772 1772 uEDX = ASMCpuId_EDX(0x80000007); … … 1814 1814 /* (2) If it's an AMD CPU with power management, we won't trust its TSC. */ 1815 1815 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX); 1816 if ( ASMIsValidStdRange(uEAX)1817 && ( ASMIsAmdCpuEx(uEBX, uECX, uEDX) || ASMIsHygonCpuEx(uEBX, uECX, uEDX)) )1816 if ( RTX86IsValidStdRange(uEAX) 1817 && (RTX86IsAmdCpu(uEBX, uECX, uEDX) || RTX86IsHygonCpu(uEBX, uECX, uEDX)) ) 1818 1818 { 1819 1819 /* Check for APM support. */ 1820 1820 uEAX = ASMCpuId_EAX(0x80000000); 1821 if ( ASMIsValidExtRange(uEAX) && uEAX >= 0x80000007)1821 if (RTX86IsValidExtRange(uEAX) && uEAX >= 0x80000007) 1822 1822 { 1823 1823 uEDX = ASMCpuId_EDX(0x80000007); … … 4033 4033 && pGip->cOnlineCpus > 2 4034 4034 && ASMHasCpuId() 4035 && ASMIsValidStdRange(ASMCpuId_EAX(0))4035 && RTX86IsValidStdRange(ASMCpuId_EAX(0)) 4036 4036 && (ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_HTT) 4037 4037 && ( !ASMIsAmdCpu() 4038 || ASMGetCpuFamily(u32Tmp = ASMCpuId_EAX(1)) > 0x154039 || ( ASMGetCpuFamily(u32Tmp) == 0x15 /* Piledriver+, not bulldozer (FX-4150 didn't like it). */4040 && ASMGetCpuModelAMD(u32Tmp) >= 0x02) ) )4038 || RTX86GetCpuFamily(u32Tmp = ASMCpuId_EAX(1)) > 0x15 4039 || ( RTX86GetCpuFamily(u32Tmp) == 0x15 /* Piledriver+, not bulldozer (FX-4150 didn't like it). */ 4040 && RTX86GetCpuModelAMD(u32Tmp) >= 0x02) ) ) 4041 4041 || !RTMpIsCpuOnline(idMaster) ) 4042 4042 { -
trunk/src/VBox/HostDrivers/Support/darwin/SUPDrv-darwin.cpp
r93115 r93515 2008 2008 uint32_t uMaxId, uEAX, uEBX, uECX, uEDX; 2009 2009 ASMCpuId(0, &uMaxId, &uEBX, &uECX, &uEDX); 2010 if ( ASMIsValidStdRange(uMaxId)2010 if ( RTX86IsValidStdRange(uMaxId) 2011 2011 && uMaxId >= 0x00000007) 2012 2012 { -
trunk/src/VBox/HostDrivers/Support/win/SUPLib-win.cpp
r93239 r93515 840 840 if (!ASMHasCpuId()) 841 841 return false; 842 if (! ASMIsValidStdRange(ASMCpuId_EAX(0)))842 if (!RTX86IsValidStdRange(ASMCpuId_EAX(0))) 843 843 return false; 844 844 if (!(ASMCpuId_ECX(1) & X86_CPUID_FEATURE_ECX_HVP)) -
trunk/src/VBox/Main/src-server/HostImpl.cpp
r93209 r93515 337 337 uint32_t uMaxId, uVendorEBX, uVendorECX, uVendorEDX; 338 338 ASMCpuId(0, &uMaxId, &uVendorEBX, &uVendorECX, &uVendorEDX); 339 if ( ASMIsValidStdRange(uMaxId))339 if (RTX86IsValidStdRange(uMaxId)) 340 340 { 341 341 /* PAE? */ … … 348 348 ASMCpuId(0x80000000, &uExtMaxId, &uDummy, &uDummy, &uDummy); 349 349 ASMCpuId(0x80000001, &uDummy, &uDummy, &fExtFeaturesEcx, &fExtFeaturesEdx); 350 m->fLongModeSupported = ASMIsValidExtRange(uExtMaxId)350 m->fLongModeSupported = RTX86IsValidExtRange(uExtMaxId) 351 351 && (fExtFeaturesEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE); 352 352 … … 359 359 360 360 /* VT-x? */ 361 if ( ASMIsIntelCpuEx(uVendorEBX, uVendorECX, uVendorEDX)362 || ASMIsViaCentaurCpuEx(uVendorEBX, uVendorECX, uVendorEDX)363 || ASMIsShanghaiCpuEx(uVendorEBX, uVendorECX, uVendorEDX))361 if ( RTX86IsIntelCpu(uVendorEBX, uVendorECX, uVendorEDX) 362 || RTX86IsViaCentaurCpu(uVendorEBX, uVendorECX, uVendorEDX) 363 || RTX86IsShanghaiCpu(uVendorEBX, uVendorECX, uVendorEDX)) 364 364 { 365 365 if ( (fFeaturesEcx & X86_CPUID_FEATURE_ECX_VMX) … … 375 375 } 376 376 /* AMD-V */ 377 else if ( ASMIsAmdCpuEx(uVendorEBX, uVendorECX, uVendorEDX)378 || ASMIsHygonCpuEx(uVendorEBX, uVendorECX, uVendorEDX))377 else if ( RTX86IsAmdCpu(uVendorEBX, uVendorECX, uVendorEDX) 378 || RTX86IsHygonCpu(uVendorEBX, uVendorECX, uVendorEDX)) 379 379 { 380 380 if ( (fExtFeaturesEcx & X86_CPUID_AMD_FEATURE_ECX_SVM) 381 381 && (fFeaturesEdx & X86_CPUID_FEATURE_EDX_MSR) 382 382 && (fFeaturesEdx & X86_CPUID_FEATURE_EDX_FXSR) 383 && ASMIsValidExtRange(uExtMaxId)383 && RTX86IsValidExtRange(uExtMaxId) 384 384 ) 385 385 { -
trunk/src/VBox/Runtime/testcase/tstRTInlineAsm.cpp
r93115 r93515 409 409 "Support: 0-%u\n", 410 410 &s.uEBX, &s.uEDX, &s.uECX, s.uEAX); 411 bool const fIntel = ASMIsIntelCpuEx(s.uEBX, s.uECX, s.uEDX);411 bool const fIntel = RTX86IsIntelCpu(s.uEBX, s.uECX, s.uEDX); 412 412 413 413 /* … … 427 427 "CLFLUSH Size: %d\n" 428 428 "Brand ID: %#04x\n", 429 (s.uEAX >> 8) & 0xf, (s.uEAX >> 20) & 0x7f, ASMGetCpuFamily(s.uEAX),430 (s.uEAX >> 4) & 0xf, (s.uEAX >> 16) & 0x0f, ASMGetCpuModel(s.uEAX, fIntel),431 ASMGetCpuStepping(s.uEAX),429 (s.uEAX >> 8) & 0xf, (s.uEAX >> 20) & 0x7f, RTX86GetCpuFamily(s.uEAX), 430 (s.uEAX >> 4) & 0xf, (s.uEAX >> 16) & 0x0f, RTX86GetCpuModel(s.uEAX, fIntel), 431 RTX86GetCpuStepping(s.uEAX), 432 432 (s.uEAX >> 12) & 0x3, s_apszTypes[(s.uEAX >> 12) & 0x3], 433 433 (s.uEBX >> 24) & 0xff, … … 558 558 "Stepping: %d\n" 559 559 "Brand ID: %#05x\n", 560 (s.uEAX >> 8) & 0xf, (s.uEAX >> 20) & 0x7f, ASMGetCpuFamily(s.uEAX),561 (s.uEAX >> 4) & 0xf, (s.uEAX >> 16) & 0x0f, ASMGetCpuModel(s.uEAX, fIntel),562 ASMGetCpuStepping(s.uEAX),560 (s.uEAX >> 8) & 0xf, (s.uEAX >> 20) & 0x7f, RTX86GetCpuFamily(s.uEAX), 561 (s.uEAX >> 4) & 0xf, (s.uEAX >> 16) & 0x0f, RTX86GetCpuModel(s.uEAX, fIntel), 562 RTX86GetCpuStepping(s.uEAX), 563 563 s.uEBX & 0xfff); 564 564 … … 2893 2893 uint32_t uAux; 2894 2894 if ( ASMHasCpuId() 2895 && ASMIsValidExtRange(ASMCpuId_EAX(0x80000000))2895 && RTX86IsValidExtRange(ASMCpuId_EAX(0x80000000)) 2896 2896 && (ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_RDTSCP) ) 2897 2897 { -
trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp
r93115 r93515 249 249 uint32_t cExt = 0; 250 250 ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy); 251 if ( ASMIsValidExtRange(cExt))251 if (RTX86IsValidExtRange(cExt)) 252 252 { 253 253 uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001); … … 279 279 pVM->cpum.s.HostFeatures.fArchMdsNo = 0; 280 280 uint32_t const cStdRange = ASMCpuId_EAX(0); 281 if ( ASMIsValidStdRange(cStdRange)281 if ( RTX86IsValidStdRange(cStdRange) 282 282 && cStdRange >= 7) 283 283 { … … 728 728 uint32_t uMaxLeaf, u32EBX, u32ECX, u32EDX; 729 729 ASMCpuId(0, &uMaxLeaf, &u32EBX, &u32ECX, &u32EDX); 730 if ( ( ASMIsIntelCpuEx(u32EBX, u32ECX, u32EDX)731 || ASMIsAmdCpuEx(u32EBX, u32ECX, u32EDX)732 || ASMIsViaCentaurCpuEx(u32EBX, u32ECX, u32EDX)733 || ASMIsShanghaiCpuEx(u32EBX, u32ECX, u32EDX)734 || ASMIsHygonCpuEx(u32EBX, u32ECX, u32EDX))735 && ASMIsValidStdRange(uMaxLeaf))730 if ( ( RTX86IsIntelCpu(u32EBX, u32ECX, u32EDX) 731 || RTX86IsAmdCpu(u32EBX, u32ECX, u32EDX) 732 || RTX86IsViaCentaurCpu(u32EBX, u32ECX, u32EDX) 733 || RTX86IsShanghaiCpu(u32EBX, u32ECX, u32EDX) 734 || RTX86IsHygonCpu(u32EBX, u32ECX, u32EDX)) 735 && RTX86IsValidStdRange(uMaxLeaf)) 736 736 { 737 737 uint32_t uDummy; … … 750 750 ASMCpuId(0x80000000, &uMaxExtLeaf, &u32EBX, &u32ECX, &u32EDX); 751 751 if ( uMaxExtLeaf >= UINT32_C(0x80000008) 752 && ASMIsValidExtRange(uMaxExtLeaf))752 && RTX86IsValidExtRange(uMaxExtLeaf)) 753 753 { 754 754 uint32_t u32PhysBits; -
trunk/src/VBox/VMM/VMMR0/HMR0.cpp
r93115 r93515 1253 1253 uint32_t fWorldSwitcher = 0; 1254 1254 uint32_t cLastStdLeaf = ASMCpuId_EAX(0); 1255 if (cLastStdLeaf >= 0x00000007 && ASMIsValidStdRange(cLastStdLeaf))1255 if (cLastStdLeaf >= 0x00000007 && RTX86IsValidStdRange(cLastStdLeaf)) 1256 1256 { 1257 1257 uint32_t uEdx = 0; -
trunk/src/VBox/VMM/VMMR3/CPUM.cpp
r93337 r93515 127 127 #include <VBox/err.h> 128 128 #include <VBox/log.h> 129 #include <iprt/asm-amd64-x86.h> 129 #if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64) 130 # include <iprt/asm-amd64-x86.h> 131 #endif 130 132 #include <iprt/assert.h> 131 133 #include <iprt/cpuset.h> … … 972 974 973 975 976 #if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64) 974 977 /** 975 978 * Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs. … … 993 996 { 994 997 uint32_t cExt = ASMCpuId_EAX(0x80000000); 995 if ( ASMIsValidExtRange(cExt))998 if (RTX86IsValidExtRange(cExt)) 996 999 { 997 1000 uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001); … … 1008 1011 } 1009 1012 } 1013 #endif 1010 1014 1011 1015 … … 2010 2014 * Gather info about the host CPU. 2011 2015 */ 2016 #if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64) 2012 2017 if (!ASMHasCpuId()) 2013 2018 { … … 2015 2020 return VERR_UNSUPPORTED_CPU; 2016 2021 } 2022 #endif 2017 2023 2018 2024 pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask(); … … 2054 2060 uint64_t fXcr0Host = 0; 2055 2061 uint64_t fXStateHostMask = 0; 2062 #if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64) 2056 2063 if ( pVM->cpum.s.HostFeatures.fXSaveRstor 2057 2064 && pVM->cpum.s.HostFeatures.fOpSysXSaveRstor) … … 2062 2069 ("%#llx\n", fXStateHostMask), fXStateHostMask = 0); 2063 2070 } 2071 #endif 2064 2072 pVM->cpum.s.fXStateHostMask = fXStateHostMask; 2065 2073 LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n", … … 2117 2125 return rc; 2118 2126 2127 #if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64) 2119 2128 /* 2120 2129 * Check if we need to workaround partial/leaky FPU handling. 2121 2130 */ 2122 2131 cpumR3CheckLeakyFpu(pVM); 2132 #endif 2123 2133 2124 2134 /* -
trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp
r93268 r93515 31 31 32 32 #include <VBox/err.h> 33 #include <iprt/asm-amd64-x86.h> 33 #if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64) 34 # include <iprt/asm-amd64-x86.h> 35 #endif 34 36 #include <iprt/ctype.h> 35 37 #include <iprt/mem.h> … … 690 692 VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void) 691 693 { 694 #if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64) 692 695 if ( ASMHasCpuId() 693 && ASMIsValidStdRange(ASMCpuId_EAX(0))696 && RTX86IsValidStdRange(ASMCpuId_EAX(0)) 694 697 && ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR) 695 698 { … … 702 705 return pState->MXCSR_MASK; 703 706 } 707 #endif 704 708 return 0; 705 709 } … … 1087 1091 1088 1092 1093 #if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64) 1089 1094 /** 1090 1095 * Checks if ECX make a difference when reading a given CPUID leaf. … … 1177 1182 if (uSubLeaf >= 128) 1178 1183 { 1179 # ifndef IN_VBOX_CPU_REPORT1184 # ifndef IN_VBOX_CPU_REPORT 1180 1185 /* Ok, limit it according to the documentation if possible just to 1181 1186 avoid annoying users with these detection issues. */ … … 1195 1200 return true; 1196 1201 } 1197 # endif1202 # endif 1198 1203 *pcSubLeaves = UINT32_MAX; 1199 1204 return true; … … 1212 1217 return true; 1213 1218 } 1219 #endif /* RT_ARCH_X86 || RT_ARCH_AMD64 */ 1214 1220 1215 1221 … … 1287 1293 } 1288 1294 1295 #if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64) 1289 1296 1290 1297 /** … … 1358 1365 || uEbx 1359 1366 || uEdx 1360 || ASMIsAmdCpuEx((*ppaLeaves)[0].uEbx, (*ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)1361 || ASMIsHygonCpuEx((*ppaLeaves)[0].uEbx, (*ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )1367 || RTX86IsAmdCpu((*ppaLeaves)[0].uEbx, (*ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx) 1368 || RTX86IsHygonCpu((*ppaLeaves)[0].uEbx, (*ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) ) 1362 1369 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID; 1363 1370 … … 1367 1374 else if ( uLeaf == UINT32_C(0x80000001) 1368 1375 && ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC) 1369 || ASMIsAmdCpuEx((*ppaLeaves)[0].uEbx, (*ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)1370 || ASMIsHygonCpuEx((*ppaLeaves)[0].uEbx, (*ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )1376 || RTX86IsAmdCpu((*ppaLeaves)[0].uEbx, (*ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx) 1377 || RTX86IsHygonCpu((*ppaLeaves)[0].uEbx, (*ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) ) 1371 1378 fFlags |= CPUMCPUIDLEAF_F_CONTAINS_APIC; 1372 1379 … … 1480 1487 uint32_t uLastStd = ASMCpuId_EAX(0); 1481 1488 uint32_t uLastExt = ASMCpuId_EAX(0x80000000); 1482 if (! ASMIsValidExtRange(uLastExt))1489 if (!RTX86IsValidExtRange(uLastExt)) 1483 1490 uLastExt = 0x80000000; 1484 1491 … … 1624 1631 } 1625 1632 1633 #endif /* RT_ARCH_X86 || RT_ARCH_AMD64 */ 1626 1634 1627 1635 /** … … 1649 1657 1650 1658 1659 #if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64) 1651 1660 /** 1652 1661 * Detect the CPU vendor give n the … … 1660 1669 VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX) 1661 1670 { 1662 if ( ASMIsValidStdRange(uEAX))1663 { 1664 if ( ASMIsAmdCpuEx(uEBX, uECX, uEDX))1671 if (RTX86IsValidStdRange(uEAX)) 1672 { 1673 if (RTX86IsAmdCpu(uEBX, uECX, uEDX)) 1665 1674 return CPUMCPUVENDOR_AMD; 1666 1675 1667 if ( ASMIsIntelCpuEx(uEBX, uECX, uEDX))1676 if (RTX86IsIntelCpu(uEBX, uECX, uEDX)) 1668 1677 return CPUMCPUVENDOR_INTEL; 1669 1678 1670 if ( ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))1679 if (RTX86IsViaCentaurCpu(uEBX, uECX, uEDX)) 1671 1680 return CPUMCPUVENDOR_VIA; 1672 1681 1673 if ( ASMIsShanghaiCpuEx(uEBX, uECX, uEDX))1682 if (RTX86IsShanghaiCpu(uEBX, uECX, uEDX)) 1674 1683 return CPUMCPUVENDOR_SHANGHAI; 1675 1684 … … 1679 1688 return CPUMCPUVENDOR_CYRIX; 1680 1689 1681 if ( ASMIsHygonCpuEx(uEBX, uECX, uEDX))1690 if (RTX86IsHygonCpu(uEBX, uECX, uEDX)) 1682 1691 return CPUMCPUVENDOR_HYGON; 1683 1692 … … 1689 1698 return CPUMCPUVENDOR_UNKNOWN; 1690 1699 } 1700 #endif /* RT_ARCH_X86 || RT_ARCH_AMD64 */ 1691 1701 1692 1702 … … 1892 1902 pStd0Leaf->uEcx, 1893 1903 pStd0Leaf->uEdx); 1894 pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);1895 pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);1896 pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);1904 pFeatures->uFamily = RTX86GetCpuFamily(pStd1Leaf->uEax); 1905 pFeatures->uModel = RTX86GetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL); 1906 pFeatures->uStepping = RTX86GetCpuStepping(pStd1Leaf->uEax); 1897 1907 pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor, 1898 1908 pFeatures->uFamily, … … 2595 2605 { 2596 2606 PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); 2597 uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8( ASMGetCpuStepping(pStdFeatureLeaf->uEax),2598 ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),2599 ASMGetCpuFamily(pStdFeatureLeaf->uEax),2607 uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(RTX86GetCpuStepping(pStdFeatureLeaf->uEax), 2608 RTX86GetCpuModelIntel(pStdFeatureLeaf->uEax), 2609 RTX86GetCpuFamily(pStdFeatureLeaf->uEax), 2600 2610 0); 2601 2611 uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep; … … 5397 5407 PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(*ppaLeaves, *pcLeaves, 0, 0); 5398 5408 if ( pLeaf 5399 && ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))5409 && RTX86IsIntelCpu(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx)) 5400 5410 { 5401 5411 CPUMCPUIDLEAF Leaf; … … 5772 5782 { 5773 5783 /** @todo deal with no 0x80000001 on the host. */ 5774 bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx)5775 || ASMIsHygonCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);5776 bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx)5777 || ASMIsHygonCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);5784 bool const fHostAmd = RTX86IsAmdCpu(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx) 5785 || RTX86IsHygonCpu(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx); 5786 bool const fGuestAmd = RTX86IsAmdCpu(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx) 5787 || RTX86IsHygonCpu(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx); 5778 5788 5779 5789 /* CPUID(0x80000001).ecx */ … … 6610 6620 "%36s %#04x\n" 6611 6621 , 6612 "Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),6613 "Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),6614 "Stepping:", ASMGetCpuStepping(uEAX),6622 "Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, RTX86GetCpuFamily(uEAX), 6623 "Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, RTX86GetCpuModel(uEAX, fIntel), 6624 "Stepping:", RTX86GetCpuStepping(uEAX), 6615 6625 "Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3], 6616 6626 "APIC ID:", (uEBX >> 24) & 0xff, … … 6843 6853 PCCPUMCPUIDLEAF pCurLeaf; 6844 6854 PCCPUMCPUIDLEAF pNextLeaf; 6845 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,6846 pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,6847 pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);6855 bool const fIntel = RTX86IsIntelCpu(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx, 6856 pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx, 6857 pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx); 6848 6858 6849 6859 /* … … 6952 6962 6953 6963 ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx); 6954 cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;6964 cHstMax = RTX86IsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0; 6955 6965 cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000) 6956 6966 ? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0; … … 7017 7027 "Stepping: %d\n" 7018 7028 "Brand ID: %#05x\n", 7019 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),7020 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),7021 ASMGetCpuStepping(uEAX),7029 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, RTX86GetCpuFamily(uEAX), 7030 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, RTX86GetCpuModel(uEAX, fIntel), 7031 RTX86GetCpuStepping(uEAX), 7022 7032 pCurLeaf->uEbx & 0xfff); 7023 7033 -
trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp
r93115 r93515 897 897 pInfo->paCpuIdLeavesR3[0].uEdx); 898 898 uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax; 899 uint8_t const uFamily = ASMGetCpuFamily(uStd1Eax);900 uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);901 uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);899 uint8_t const uFamily = RTX86GetCpuFamily(uStd1Eax); 900 uint8_t const uModel = RTX86GetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL); 901 uint8_t const uStepping = RTX86GetCpuStepping(uStd1Eax); 902 902 CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping); 903 903 -
trunk/src/VBox/VMM/VMMR3/NEMR3Native-win.cpp
r93355 r93515 467 467 if (!ASMHasCpuId()) 468 468 return RTErrInfoSet(pErrInfo, VERR_NEM_NOT_AVAILABLE, "No CPUID support"); 469 if (! ASMIsValidStdRange(ASMCpuId_EAX(0)))469 if (!RTX86IsValidStdRange(ASMCpuId_EAX(0))) 470 470 return RTErrInfoSet(pErrInfo, VERR_NEM_NOT_AVAILABLE, "No CPUID leaf #1"); 471 471 if (!(ASMCpuId_ECX(1) & X86_CPUID_FEATURE_ECX_HVP)) … … 477 477 uint32_t uEdx = 0; 478 478 ASMCpuIdExSlow(0x40000000, 0, 0, 0, &cMaxHyperLeaf, &uEbx, &uEcx, &uEdx); 479 if (! ASMIsValidHypervisorRange(cMaxHyperLeaf))479 if (!RTX86IsValidHypervisorRange(cMaxHyperLeaf)) 480 480 return RTErrInfoSetF(pErrInfo, VERR_NEM_NOT_AVAILABLE, "Invalid hypervisor CPUID range (%#x %#x %#x %#x)", 481 481 cMaxHyperLeaf, uEbx, uEcx, uEdx); -
trunk/src/VBox/VMM/VMMR3/TM.cpp
r93308 r93515 887 887 */ 888 888 ASMCpuId(0x80000000, &uEAX, &uEBX, &uECX, &uEDX); 889 if (uEAX >= 0x80000007 && ASMIsValidExtRange(uEAX))889 if (uEAX >= 0x80000007 && RTX86IsValidExtRange(uEAX)) 890 890 { 891 891 ASMCpuId(0x80000007, &uEAX, &uEBX, &uECX, &uEDX); … … 927 927 * as the AMD test above. 928 928 */ 929 /** @todo use ASMGetCpuFamily() and ASMGetCpuModel() here. */929 /** @todo use RTX86GetCpuFamily() and RTX86GetCpuModel() here. */ 930 930 ASMCpuId(1, &uEAX, &uEBX, &uECX, &uEDX); 931 931 unsigned uModel = (uEAX >> 4) & 0x0f; … … 947 947 * Eden X2 and QuadCore. 948 948 */ 949 /** @todo use ASMGetCpuFamily() and ASMGetCpuModel() here. */949 /** @todo use RTX86GetCpuFamily() and RTX86GetCpuModel() here. */ 950 950 ASMCpuId(1, &uEAX, &uEBX, &uECX, &uEDX); 951 951 unsigned uStepping = (uEAX & 0x0f); … … 963 963 * Shanghai - Check the model, family and stepping. 964 964 */ 965 /** @todo use ASMGetCpuFamily() and ASMGetCpuModel() here. */965 /** @todo use RTX86GetCpuFamily() and RTX86GetCpuModel() here. */ 966 966 ASMCpuId(1, &uEAX, &uEBX, &uECX, &uEDX); 967 967 unsigned uFamily = (uEAX >> 8) & 0x0f; -
trunk/src/VBox/VMM/tools/VBoxCpuReport.cpp
r93115 r93515 176 176 { 177 177 uint32_t cMaxExt = ASMCpuId_EAX(0x80000000); 178 if ( ASMIsValidExtRange(cMaxExt)&& cMaxExt >= 0x80000008)178 if (RTX86IsValidExtRange(cMaxExt)&& cMaxExt >= 0x80000008) 179 179 cMaxWidth = ASMCpuId_EAX(0x80000008) & 0xff; 180 else if ( ASMIsValidStdRange(ASMCpuId_EAX(0))180 else if ( RTX86IsValidStdRange(ASMCpuId_EAX(0)) 181 181 && (ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PSE36)) 182 182 cMaxWidth = 36; … … 191 191 { 192 192 return ASMHasCpuId() 193 && ASMIsValidStdRange(ASMCpuId_EAX(0))193 && RTX86IsValidStdRange(ASMCpuId_EAX(0)) 194 194 && (ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE); 195 195 } … … 199 199 { 200 200 return ASMHasCpuId() 201 && ASMIsValidExtRange(ASMCpuId_EAX(0x80000000))201 && RTX86IsValidExtRange(ASMCpuId_EAX(0x80000000)) 202 202 && (ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE); 203 203 } … … 207 207 { 208 208 return ASMHasCpuId() 209 && ASMIsValidExtRange(ASMCpuId_EAX(0x80000000))209 && RTX86IsValidExtRange(ASMCpuId_EAX(0x80000000)) 210 210 && (ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX); 211 211 } … … 215 215 { 216 216 return ASMHasCpuId() 217 && ASMIsValidStdRange(ASMCpuId_EAX(0))217 && RTX86IsValidStdRange(ASMCpuId_EAX(0)) 218 218 && (ASMCpuId_ECX(1) & X86_CPUID_FEATURE_ECX_X2APIC); 219 219 } … … 4412 4412 * Are MSRs supported by the CPU? 4413 4413 */ 4414 if ( ! ASMIsValidStdRange(ASMCpuId_EAX(0))4414 if ( !RTX86IsValidStdRange(ASMCpuId_EAX(0)) 4415 4415 || !(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_MSR) ) 4416 4416 { … … 4458 4458 uint32_t uEax, uEbx, uEcx, uEdx; 4459 4459 ASMCpuIdExSlow(0, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx); 4460 if (! ASMIsValidStdRange(uEax))4460 if (!RTX86IsValidStdRange(uEax)) 4461 4461 return RTMsgErrorRc(VERR_NOT_SUPPORTED, "Invalid std CPUID range: %#x\n", uEax); 4462 4462 g_enmVendor = CPUMR3CpuIdDetectVendorEx(uEax, uEbx, uEcx, uEdx); … … 4464 4464 ASMCpuIdExSlow(1, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx); 4465 4465 g_enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(g_enmVendor, 4466 ASMGetCpuFamily(uEax),4467 ASMGetCpuModel(uEax, g_enmVendor == CPUMCPUVENDOR_INTEL),4468 ASMGetCpuStepping(uEax));4466 RTX86GetCpuFamily(uEax), 4467 RTX86GetCpuModel(uEax, g_enmVendor == CPUMCPUVENDOR_INTEL), 4468 RTX86GetCpuStepping(uEax)); 4469 4469 g_fIntelNetBurst = CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch); 4470 4470 … … 4637 4637 uint32_t uEax, uEbx, uEcx, uEdx; 4638 4638 ASMCpuIdExSlow(0, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx); 4639 if (! ASMIsValidStdRange(uEax))4639 if (!RTX86IsValidStdRange(uEax)) 4640 4640 return RTMsgErrorRc(VERR_NOT_SUPPORTED, "Invalid std CPUID range: %#x\n", uEax); 4641 4641 … … 4650 4650 ASMCpuIdExSlow(1, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx); 4651 4651 CPUMMICROARCH enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, 4652 ASMGetCpuFamily(uEax),4653 ASMGetCpuModel(uEax, enmVendor == CPUMCPUVENDOR_INTEL),4654 ASMGetCpuStepping(uEax));4652 RTX86GetCpuFamily(uEax), 4653 RTX86GetCpuModel(uEax, enmVendor == CPUMCPUVENDOR_INTEL), 4654 RTX86GetCpuStepping(uEax)); 4655 4655 4656 4656 /* … … 4664 4664 4665 4665 ASMCpuIdExSlow(0x80000000, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx); 4666 if ( ASMIsValidExtRange(uEax) && uEax >= UINT32_C(0x80000004))4666 if (RTX86IsValidExtRange(uEax) && uEax >= UINT32_C(0x80000004)) 4667 4667 { 4668 4668 /* Get the raw name and strip leading spaces. */ … … 4737 4737 { 4738 4738 ASMCpuIdExSlow(1, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx); 4739 RTStrPrintf(szNameC, sizeof(szNameC), "%s_%u_%u_%u", cpuVendorToString(enmVendor), ASMGetCpuFamily(uEax),4740 ASMGetCpuModel(uEax, enmVendor == CPUMCPUVENDOR_INTEL), ASMGetCpuStepping(uEax));4739 RTStrPrintf(szNameC, sizeof(szNameC), "%s_%u_%u_%u", cpuVendorToString(enmVendor), RTX86GetCpuFamily(uEax), 4740 RTX86GetCpuModel(uEax, enmVendor == CPUMCPUVENDOR_INTEL), RTX86GetCpuStepping(uEax)); 4741 4741 pszCpuDesc = pszName = szNameC; 4742 4742 vbCpuRepDebug("Name/NameC: %s\n", szNameC); … … 4843 4843 pszCpuDesc, 4844 4844 CPUMR3CpuVendorName(enmVendor), 4845 ASMGetCpuFamily(uEax),4846 ASMGetCpuModel(uEax, enmVendor == CPUMCPUVENDOR_INTEL),4847 ASMGetCpuStepping(uEax),4845 RTX86GetCpuFamily(uEax), 4846 RTX86GetCpuModel(uEax, enmVendor == CPUMCPUVENDOR_INTEL), 4847 RTX86GetCpuStepping(uEax), 4848 4848 CPUMR3MicroarchName(enmMicroarch), 4849 4849 vbCpuRepGuessScalableBusFrequencyName(), -
trunk/src/VBox/ValidationKit/bootsectors/bs3kit/bs3-cmn-GetCpuVendor.c
r93115 r93515 37 37 uint32_t uEbx, uEcx, uEdx; 38 38 ASMCpuIdExSlow(0, 0, 0, 0, NULL, &uEbx, &uEcx, &uEdx); 39 if ( ASMIsIntelCpuEx(uEbx, uEcx, uEdx))39 if (RTX86IsIntelCpu(uEbx, uEcx, uEdx)) 40 40 return BS3CPUVENDOR_INTEL; 41 if ( ASMIsAmdCpuEx(uEbx, uEcx, uEdx))41 if (RTX86IsAmdCpu(uEbx, uEcx, uEdx)) 42 42 return BS3CPUVENDOR_AMD; 43 if ( ASMIsViaCentaurCpuEx(uEbx, uEcx, uEdx))43 if (RTX86IsViaCentaurCpu(uEbx, uEcx, uEdx)) 44 44 return BS3CPUVENDOR_VIA; 45 if ( ASMIsShanghaiCpuEx(uEbx, uEcx, uEdx))45 if (RTX86IsShanghaiCpu(uEbx, uEcx, uEdx)) 46 46 return BS3CPUVENDOR_SHANGHAI; 47 if ( ASMIsHygonCpuEx(uEbx, uEcx, uEdx))47 if (RTX86IsHygonCpu(uEbx, uEcx, uEdx)) 48 48 return BS3CPUVENDOR_HYGON; 49 49 return BS3CPUVENDOR_UNKNOWN; -
trunk/src/VBox/ValidationKit/testboxscript/TestBoxHelper.cpp
r93302 r93515 467 467 /* VT-x */ 468 468 ASMCpuId(0x00000000, &uEax, &uEbx, &uEcx, &uEdx); 469 if ( ASMIsValidStdRange(uEax))469 if (RTX86IsValidStdRange(uEax)) 470 470 { 471 471 ASMCpuId(0x00000001, &uEax, &uEbx, &uEcx, &uEdx); … … 476 476 /* AMD-V */ 477 477 ASMCpuId(0x80000000, &uEax, &uEbx, &uEcx, &uEdx); 478 if ( ASMIsValidExtRange(uEax))478 if (RTX86IsValidExtRange(uEax)) 479 479 { 480 480 ASMCpuId(0x80000001, &uEax, &uEbx, &uEcx, &uEdx); … … 509 509 uint32_t uEax, uEbx, uEcx, uEdx; 510 510 ASMCpuId(0x80000000, &uEax, &uEbx, &uEcx, &uEdx); 511 if ( ASMIsValidExtRange(uEax) && uEax >= 0x8000000a)511 if (RTX86IsValidExtRange(uEax) && uEax >= 0x8000000a) 512 512 { 513 513 ASMCpuId(0x8000000a, &uEax, &uEbx, &uEcx, &uEdx); … … 617 617 uint32_t uEax, uEbx, uEcx, uEdx; 618 618 ASMCpuId(0x00000000, &uEax, &uEbx, &uEcx, &uEdx); 619 if ( ASMIsValidStdRange(uEax))619 if (RTX86IsValidStdRange(uEax)) 620 620 { 621 621 ASMCpuId(0x00000001, &uEax, &uEbx, &uEcx, &uEdx); … … 625 625 won't necessarily do so. */ 626 626 ASMCpuId(0x80000000, &uEax, &uEbx, &uEcx, &uEdx); 627 if ( ASMIsValidExtRange(uEax))627 if (RTX86IsValidExtRange(uEax)) 628 628 { 629 629 ASMCpuId(0x80000001, &uEax, &uEbx, &uEcx, &uEdx); … … 652 652 uint32_t uEax, uEbx, uEcx, uEdx; 653 653 ASMCpuId(0, &uEax, &uEbx, &uEcx, &uEdx); 654 if ( ASMIsValidStdRange(uEax) && uEax >= 1)654 if (RTX86IsValidStdRange(uEax) && uEax >= 1) 655 655 { 656 656 uint32_t uEax1 = ASMCpuId_EAX(1); 657 uint32_t uVersion = ( ASMGetCpuFamily(uEax1) << 24)658 | ( ASMGetCpuModel(uEax1, ASMIsIntelCpuEx(uEbx, uEcx, uEdx)) << 8)659 | ASMGetCpuStepping(uEax1);657 uint32_t uVersion = (RTX86GetCpuFamily(uEax1) << 24) 658 | (RTX86GetCpuModel(uEax1, RTX86IsIntelCpu(uEbx, uEcx, uEdx)) << 8) 659 | RTX86GetCpuStepping(uEax1); 660 660 int cch = RTPrintf("%#x\n", uVersion); 661 661 return cch > 0 ? RTEXITCODE_SUCCESS : RTEXITCODE_FAILURE;
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