Changeset 93573 in vbox for trunk/src/VBox/VMM/VMMAll
- Timestamp:
- Feb 3, 2022 11:22:36 AM (3 years ago)
- svn:sync-xref-src-repo-rev:
- 149708
- File:
-
- 1 edited
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- Added
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trunk/src/VBox/VMM/VMMAll/PGMAll.cpp
r93554 r93573 2480 2480 RTGCPHYS GCPhysCR3 = pgmGetGuestMaskedCr3(pVCpu, cr3); 2481 2481 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT 2482 if (pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT) 2482 if ( pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT 2483 && PGMMODE_WITH_PAGING(pVCpu->pgm.s.enmGuestMode)) 2483 2484 { 2484 2485 LogFlowFunc(("nested_cr3=%RX64 old=%RX64\n", GCPhysCR3, pVCpu->pgm.s.GCPhysNstGstCR3)); … … 3373 3374 * - Indicate that the CR3 is nested-guest physical address. 3374 3375 */ 3375 if ( CPUMIsGuestVmxEptPagingEnabled(pVCpu) 3376 && PGMMODE_WITH_PAGING(enmGuestMode)) 3377 { 3378 /* 3379 * Translate CR3 to its guest-physical address. 3380 * We don't use pgmGstSlatTranslateCr3() here as we want to update GCPhysNstGstCR3 -after- 3381 * switching modes to keep it consistent with how GCPhysCR3 is updated. 3382 */ 3383 PGMPTWALK Walk; 3384 PGMPTWALKGST GstWalk; 3385 int const rc = pgmGstSlatWalkPhys(pVCpu, PGMSLAT_EPT, GCPhysCR3, &Walk, &GstWalk); 3386 if (RT_SUCCESS(rc)) 3387 { /* likely */ } 3388 else 3376 if (CPUMIsGuestVmxEptPagingEnabled(pVCpu)) 3377 { 3378 if (PGMMODE_WITH_PAGING(enmGuestMode)) 3389 3379 { 3390 3380 /* 3391 * SLAT failed but we avoid reporting this to the caller because the caller 3392 * is not supposed to fail. The only time the caller needs to indicate a 3393 * failure to software is when PAE paging is used by the nested-guest, but 3394 * we handle the PAE case separately (e.g., see VMX transition in IEM). 3395 * In all other cases, the failure will be indicated when CR3 tries to be 3396 * translated on the next linear-address memory access. 3397 * See Intel spec. 27.2.1 "EPT Overview". 3381 * Translate CR3 to its guest-physical address. 3382 * We don't use pgmGstSlatTranslateCr3() here as we want to update GCPhysNstGstCR3 -after- 3383 * switching modes to keep it consistent with how GCPhysCR3 is updated. 3398 3384 */ 3399 AssertMsgFailed(("SLAT failed for CR3 %#RX64 rc=%Rrc\n", GCPhysCR3, rc)); 3400 3401 /* Trying to coax PGM to succeed for the time being... */ 3402 Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS); 3385 PGMPTWALK Walk; 3386 PGMPTWALKGST GstWalk; 3387 int const rc = pgmGstSlatWalkPhys(pVCpu, PGMSLAT_EPT, GCPhysCR3, &Walk, &GstWalk); 3388 if (RT_SUCCESS(rc)) 3389 { /* likely */ } 3390 else 3391 { 3392 /* 3393 * SLAT failed but we avoid reporting this to the caller because the caller 3394 * is not supposed to fail. The only time the caller needs to indicate a 3395 * failure to software is when PAE paging is used by the nested-guest, but 3396 * we handle the PAE case separately (e.g., see VMX transition in IEM). 3397 * In all other cases, the failure will be indicated when CR3 tries to be 3398 * translated on the next linear-address memory access. 3399 * See Intel spec. 27.2.1 "EPT Overview". 3400 */ 3401 AssertMsgFailed(("SLAT failed for CR3 %#RX64 rc=%Rrc\n", GCPhysCR3, rc)); 3402 3403 /* Trying to coax PGM to succeed for the time being... */ 3404 Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS); 3405 pVCpu->pgm.s.GCPhysNstGstCR3 = GCPhysCR3; 3406 pVCpu->pgm.s.enmGuestSlatMode = PGMSLAT_EPT; 3407 pVCpu->pgm.s.enmGuestMode = enmGuestMode; 3408 HMHCChangedPagingMode(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode); 3409 return VINF_SUCCESS; 3410 } 3403 3411 pVCpu->pgm.s.GCPhysNstGstCR3 = GCPhysCR3; 3404 pVCpu->pgm.s.enmGuestSlatMode = PGMSLAT_EPT; 3405 pVCpu->pgm.s.enmGuestMode = enmGuestMode; 3406 HMHCChangedPagingMode(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode); 3407 return VINF_SUCCESS; 3408 } 3409 3410 pVCpu->pgm.s.GCPhysNstGstCR3 = GCPhysCR3; 3412 GCPhysCR3 = Walk.GCPhys; 3413 } 3411 3414 pVCpu->pgm.s.enmGuestSlatMode = PGMSLAT_EPT; 3412 GCPhysCR3 = Walk.GCPhys;3413 3415 } 3414 3416 else
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