- Timestamp:
- Jun 4, 2008 11:44:45 AM (17 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/VMM/CPUM.cpp
r9354 r9380 1 1 /* $Id$ */ 2 2 /** @file 3 * CPUM - CPU Monitor (/Manager)3 * CPUM - CPU Monitor / Manager. 4 4 */ 5 5 … … 20 20 */ 21 21 22 /** @page pg_cpum 23 * The CPU Monitor / Manager keeps track of all the CPU registers. It is 24 * also responsible for lazy FPU handling and some of the context loading 25 * in raw mode. 26 * 27 * There are three CPU contexts, the most important one is the guest one (GC). 28 * When running in raw-mode (RC) there is a special hyper context for the VMM 29 * that floats around inside the guest address space. When running in raw-mode 30 * or when using 64-bit guests on a 32-bit host, CPUM also maintains a host 31 * context for saving and restoring registers accross world switches. This latter 32 * is done in cooperation with the world switcher (@see pg_vmm). 33 */ 22 34 23 35 /******************************************************************************* … … 58 70 59 71 /** 60 * What kind of cpu info dump to perform e.72 * What kind of cpu info dump to perform. 61 73 */ 62 74 typedef enum CPUMDUMPTYPE … … 66 78 CPUMDUMPTYPE_VERBOSE 67 79 68 } CPUMDUMPTYPE, *PCPUMDUMPTYPE; 80 } CPUMDUMPTYPE; 81 /** Pointer to a cpu info dump type. */ 82 typedef CPUMDUMPTYPE *PCPUMDUMPTYPE; 69 83 70 84 … … 73 87 *******************************************************************************/ 74 88 static int cpumR3CpuIdInit(PVM pVM); 75 static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);76 static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);89 static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM); 90 static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version); 77 91 static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs); 78 92 static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs); … … 147 161 /* Bogus on AMD? */ 148 162 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP) 149 {150 163 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n")); 151 }152 164 153 165 /* … … 171 183 && uECX == X86_CPUID_VENDOR_AMD_ECX 172 184 && uEDX == X86_CPUID_VENDOR_AMD_EDX) 173 {174 185 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD; 175 }176 186 else if ( uEAX >= 1 177 && uEBX == X86_CPUID_VENDOR_INTEL_EBX 178 && uECX == X86_CPUID_VENDOR_INTEL_ECX 179 && uEDX == X86_CPUID_VENDOR_INTEL_EDX) 180 { 187 && uEBX == X86_CPUID_VENDOR_INTEL_EBX 188 && uECX == X86_CPUID_VENDOR_INTEL_ECX 189 && uEDX == X86_CPUID_VENDOR_INTEL_EDX) 181 190 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL; 182 } 183 else /* @todo Via */ 191 else /** @todo Via */ 184 192 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN; 185 193 … … 502 510 CPUMR3DECL(int) CPUMR3Term(PVM pVM) 503 511 { 504 /** @todo */512 /** @todo ? */ 505 513 return 0; 506 514 } … … 530 538 531 539 pCtx->cs = 0xf000; 532 pCtx->csHid.u32Base = 0xffff0000;540 pCtx->csHid.u32Base = UINT32_C(0xffff0000); 533 541 pCtx->csHid.u32Limit = 0x0000ffff; 534 542 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */ … … 572 580 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY; 573 581 574 pCtx->dr6 = 0xFFFF0FF0;582 pCtx->dr6 = UINT32_C(0xFFFF0FF0); 575 583 pCtx->dr7 = 0x400; 576 584 … … 579 587 580 588 /* Init PAT MSR */ 581 pCtx->msrPAT = 0x0007040600070406ULL; /* @todo correct? */ 582 } 583 589 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */ 590 } 584 591 585 592 … … 1034 1041 #endif 1035 1042 } 1043 1036 1044 1037 1045 /** … … 1869 1877 } 1870 1878 1871 1872 1879 #ifdef DEBUG 1880 1873 1881 /** 1874 1882 * Disassemble an instruction and dump it to the log … … 1911 1919 } 1912 1920 1913 #endif 1921 #endif /* DEBUG */ 1914 1922 1915 1923 #ifdef DEBUG … … 1923 1931 pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest; 1924 1932 } 1925 #endif 1933 #endif /* DEBUG */ 1926 1934 1927 1935
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