- Timestamp:
- Jun 4, 2008 12:22:45 PM (17 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/HWACCM.cpp
r9375 r9383 46 46 #include <iprt/string.h> 47 47 #include <iprt/thread.h> 48 49 /* Uncomment to enable experimental nested paging. */50 //#define VBOX_WITH_NESTED_PAGING51 /* Uncomment to enable 64 bits guest support. */52 //#define VBOX_ENABLE_64_BITS_GUESTS53 48 54 49 /******************************************************************************* -
trunk/src/VBox/VMM/HWACCMInternal.h
r9116 r9383 34 34 #include <iprt/mp.h> 35 35 36 /* Uncomment to enable experimental nested paging. */ 37 //#define VBOX_WITH_NESTED_PAGING 38 /* Uncomment to enable 64 bits guest support. */ 39 //#define VBOX_ENABLE_64_BITS_GUESTS 40 36 41 __BEGIN_DECLS 37 42 … … 105 110 */ 106 111 #ifdef VBOX_STRICT 107 #define HWACCM_VMX_TRAP_MASK RT_BIT( 0) | RT_BIT(7) | RT_BIT(14) | RT_BIT(6) | RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(16)112 #define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF) | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_MF) 108 113 #define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK 109 114 #else 110 #define HWACCM_VMX_TRAP_MASK RT_BIT( 7) | RT_BIT(14)115 #define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF) 111 116 #define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK 112 117 #endif -
trunk/src/VBox/VMM/PGM.cpp
r9148 r9383 3149 3149 //case PGMMODE_AMD64_NX: 3150 3150 case PGMMODE_AMD64: 3151 GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask and make CR3 64-bit in this case! */3151 GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask! */ 3152 3152 rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3); 3153 3153 switch (pVM->pgm.s.enmShadowMode) -
trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp
r9212 r9383 644 644 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */ 645 645 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */ 646 #ifdef VBOX_ENABLE_64_BITS_GUESTS 647 break; 648 #else 646 649 AssertFailed(); 647 650 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE; 651 #endif 648 652 649 653 default: /* shut up gcc */ … … 671 675 672 676 /* EIP, ESP and EFLAGS */ 673 pVMCB->guest.u64RIP = pCtx-> eip;674 pVMCB->guest.u64RSP = pCtx-> esp;675 pVMCB->guest.u64RFlags = pCtx-> eflags.u32;677 pVMCB->guest.u64RIP = pCtx->rip; 678 pVMCB->guest.u64RSP = pCtx->rsp; 679 pVMCB->guest.u64RFlags = pCtx->rflags.u64; 676 680 677 681 /* Set CPL */ … … 679 683 680 684 /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */ 681 pVMCB->guest.u64RAX = pCtx-> eax;685 pVMCB->guest.u64RAX = pCtx->rax; 682 686 683 687 /* vmrun will fail without MSR_K6_EFER_SVME. */ … … 1031 1035 1032 1036 /* Let's first sync back eip, esp, and eflags. */ 1033 pCtx-> eip = pVMCB->guest.u64RIP;1034 pCtx-> esp = pVMCB->guest.u64RSP;1035 pCtx-> eflags.u32= pVMCB->guest.u64RFlags;1037 pCtx->rip = pVMCB->guest.u64RIP; 1038 pCtx->rsp = pVMCB->guest.u64RSP; 1039 pCtx->rflags.u64 = pVMCB->guest.u64RFlags; 1036 1040 /* eax is saved/restore across the vmrun instruction */ 1037 pCtx-> eax = pVMCB->guest.u64RAX;1041 pCtx->rax = pVMCB->guest.u64RAX; 1038 1042 1039 1043 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */ -
trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp
r9212 r9383 784 784 if (!pVM->hwaccm.s.fFPUOldStyleOverride) 785 785 { 786 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK | RT_BIT( 16));786 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK | RT_BIT(X86_XCPT_MF)); 787 787 AssertRC(rc); 788 788 pVM->hwaccm.s.fFPUOldStyleOverride = true; … … 837 837 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */ 838 838 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */ 839 #ifdef VBOX_ENABLE_64_BITS_GUESTS 840 break; 841 #else 839 842 AssertFailed(); 840 843 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE; 841 844 #endif 842 845 default: /* shut up gcc */ 843 846 AssertFailed(); … … 896 899 897 900 /* EIP, ESP and EFLAGS */ 898 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx-> eip);899 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx-> esp);901 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->rip); 902 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->rsp); 900 903 AssertRC(rc); 901 904 … … 978 981 { 979 982 int rc = VINF_SUCCESS; 980 RTCCUINTREGval, valShadow;981 RTCCUINTREGexitReason, instrError, cbInstr;982 RTGCUINTPTRexitQualification;983 RTGCUINTPTRintInfo = 0; /* shut up buggy gcc 4 */984 RTGCUINTPTRerrCode, instrInfo, uInterruptState;983 uint64_t val, valShadow; 984 uint64_t exitReason, instrError, cbInstr; 985 uint64_t exitQualification; 986 uint64_t intInfo = 0; /* shut up buggy gcc 4 */ 987 uint64_t errCode, instrInfo, uInterruptState; 985 988 bool fGuestStateSynced = false; 986 989 unsigned cResume = 0; … … 1350 1353 rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val); 1351 1354 AssertRC(rc); 1352 pCtx-> eip = val;1355 pCtx->rip = val; 1353 1356 rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val); 1354 1357 AssertRC(rc); 1355 pCtx-> esp = val;1358 pCtx->rsp = val; 1356 1359 rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val); 1357 1360 AssertRC(rc); 1358 pCtx-> eflags.u32= val;1361 pCtx->rflags.u64 = val; 1359 1362 1360 1363 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
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