Changeset 93860 in vbox for trunk/src

Timestamp:

Feb 20, 2022 9:53:58 AM (3 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

150075

Message:

VMM/IEM: Stubbed the C versions x87 FPU functions in IEMAllAImpl.asm. bugref:9898

File:

• trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp ¶

@@ -2655 +2655 @@
 
 
+/*********************************************************************************************************************************
+*   x87 FPU                                                                                                                      *
+*********************************************************************************************************************************/
+#if defined(IEM_WITHOUT_ASSEMBLY)
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_f2xm1_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fabs_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fadd_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                  PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fadd_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                  PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fadd_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                  PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fchs_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r32,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
+                                                  PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
+{
+    RT_NOREF(pFpuState, pFSW, pr80Val1, pr32Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r64,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
+                                                  PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
+{
+    RT_NOREF(pFpuState, pFSW, pr80Val1, pr64Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r80,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
+                                                  PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
+{
+    RT_NOREF(pFpuState, pFSW, pr80Val1, pr80Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_fcomi_r80_by_r80,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
+                                                       PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
+{
+    RT_NOREF(pFpuState, pFSW, pr80Val1, pr80Val2);
+    AssertReleaseFailed();
+    return 0;
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fcos_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fdiv_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                  PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fdiv_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                  PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fdiv_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                  PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fdivr_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                   PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fdivr_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                   PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fdivr_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                   PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fiadd_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                   PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fiadd_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                   PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
+                                                   PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
+{
+    RT_NOREF(pFpuState, pu16Fsw, pr80Val1, pi16Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
+                                                   PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
+{
+    RT_NOREF(pFpuState, pu16Fsw, pr80Val1, pi32Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fidiv_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                   PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fidiv_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                   PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fidivr_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                    PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fidivr_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                    PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i16_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val))
+{
+    RT_NOREF(pFpuState, pFpuRes, pi16Val);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val))
+{
+    RT_NOREF(pFpuState, pFpuRes, pi32Val);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val))
+{
+    RT_NOREF(pFpuState, pFpuRes, pi64Val);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fimul_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                   PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fimul_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                   PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
+                                                  int16_t *pi16Val, PCRTFLOAT80U pr80Val))
+{
+    RT_NOREF(pFpuState, pu16FSW, pi16Val, pr80Val);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
+                                                  int32_t *pi32Val, PCRTFLOAT80U pr80Val))
+{
+    RT_NOREF(pFpuState, pu16FSW, pi32Val, pr80Val);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
+                                                  int64_t *pi64Val, PCRTFLOAT80U pr80Val))
+{
+    RT_NOREF(pFpuState, pu16FSW, pi64Val, pr80Val);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
+                                                   int16_t *pi16Val, PCRTFLOAT80U pr80Val))
+{
+    RT_NOREF(pFpuState, pu16FSW, pi16Val, pr80Val);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
+                                                   int32_t *pi32Val, PCRTFLOAT80U pr80Val))
+{
+    RT_NOREF(pFpuState, pu16FSW, pi32Val, pr80Val);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
+                                                   int64_t *pi64Val, PCRTFLOAT80U pr80Val))
+{
+    RT_NOREF(pFpuState, pu16FSW, pi64Val, pr80Val);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fisub_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                   PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fisub_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                   PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fisubr_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                    PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fisubr_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                    PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr32Val);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr64Val);
+    AssertReleaseFailed();
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fld1,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
+{
+    RT_NOREF(pFpuState, pFpuRes);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fldl2e,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
+{
+    RT_NOREF(pFpuState, pFpuRes);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fldl2t,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
+{
+    RT_NOREF(pFpuState, pFpuRes);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fldlg2,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
+{
+    RT_NOREF(pFpuState, pFpuRes);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fldln2,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
+{
+    RT_NOREF(pFpuState, pFpuRes);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fldpi,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
+{
+    RT_NOREF(pFpuState, pFpuRes);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fldz,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
+{
+    RT_NOREF(pFpuState, pFpuRes);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fmul_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                  PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fmul_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                  PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fmul_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                  PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fpatan_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                    PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fprem_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                   PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fprem1_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                    PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fptan_r80_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo, PCRTFLOAT80U pr80Val))
+{
+    RT_NOREF(pFpuState, pFpuResTwo, pr80Val);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_frndint_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fscale_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                    PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fsin_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fsincos_r80_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo, PCRTFLOAT80U pr80Val))
+{
+    RT_NOREF(pFpuState, pFpuResTwo, pr80Val);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fsqrt_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
+                                                 PRTFLOAT32U pr32Dst, PCRTFLOAT80U pr80Src))
+{
+    RT_NOREF(pFpuState, pu16FSW, pr32Dst, pr80Src);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
+                                                 PRTFLOAT64U pr64Dst, PCRTFLOAT80U pr80Src))
+{
+    RT_NOREF(pFpuState, pu16FSW, pr64Dst, pr80Src);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
+                                                 PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src))
+{
+    RT_NOREF(pFpuState, pu16FSW, pr80Dst, pr80Src);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fsub_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                  PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fsub_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                  PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fsub_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                  PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fsubr_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                   PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fsubr_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                   PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fsubr_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                   PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_ftst_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val))
+{
+    RT_NOREF(pFpuState, pu16Fsw, pr80Val);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fucom_r80_by_r80,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
+                                                   PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
+{
+    RT_NOREF(pFpuState, pFSW, pr80Val1, pr80Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_fucomi_r80_by_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
+                                                        PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
+{
+    RT_NOREF(pFpuState, pu16Fsw, pr80Val1, pr80Val2);
+    AssertReleaseFailed();
+    return 0;
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fxam_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val))
+{
+    RT_NOREF(pFpuState, pu16Fsw, pr80Val);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fxtract_r80_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo, PCRTFLOAT80U pr80Val))
+{
+    RT_NOREF(pFpuState, pFpuResTwo, pr80Val);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fyl2x_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                   PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
+    AssertReleaseFailed();
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_fyl2xp1_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
+                                                     PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
+{
+    RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
+    AssertReleaseFailed();
+}
+
+#endif /* IEM_WITHOUT_ASSEMBLY */
+
+
+/*********************************************************************************************************************************
+*   SSE & VEX                                                                                                                    *
+*********************************************************************************************************************************/
+
 IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc))
 {