Changeset 93931 in vbox for trunk/src/VBox/VMM
- Timestamp:
- Feb 24, 2022 4:02:00 PM (3 years ago)
- svn:sync-xref-src-repo-rev:
- 150159
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 8 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/PGMAll.cpp
r93922 r93931 1137 1137 Assert(!(fOpFlags & ~(PGM_MK_PG_IS_MMIO2 | PGM_MK_PG_IS_WRITE_FAULT))); 1138 1138 1139 GCPtr &= PAGE_BASE_GC_MASK; /** @todo this ain't necessary, right... */1139 GCPtr &= ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK; /** @todo this ain't necessary, right... */ 1140 1140 1141 1141 PVMCC pVM = pVCpu->CTX_SUFF(pVM); … … 2070 2070 cb += GCPtr & GUEST_PAGE_OFFSET_MASK; 2071 2071 cb = RT_ALIGN_Z(cb, GUEST_PAGE_SIZE); 2072 GCPtr = (GCPtr & PAGE_BASE_GC_MASK);2072 GCPtr &= ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK; 2073 2073 2074 2074 /* -
trunk/src/VBox/VMM/VMMAll/PGMAllGst.h
r93922 r93931 390 390 pWalk->fSucceeded = true; 391 391 pWalk->GCPtr = GCPtr; 392 pWalk->GCPhys = GCPtr & PAGE_BASE_GC_MASK;392 pWalk->GCPhys = GCPtr & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK; 393 393 pWalk->fEffective = X86_PTE_P | X86_PTE_RW | X86_PTE_US; 394 394 NOREF(pVCpu); -
trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp
r93725 r93931 1190 1190 1191 1191 /* Temporarily allow write access to the page table again. */ 1192 rc = PGMHandlerPhysicalPageTempOff(pVM, pPage->GCPhys & PAGE_BASE_GC_MASK, pPage->GCPhys & PAGE_BASE_GC_MASK); 1192 rc = PGMHandlerPhysicalPageTempOff(pVM, 1193 pPage->GCPhys & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK, 1194 pPage->GCPhys & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK); 1193 1195 if (rc == VINF_SUCCESS) 1194 1196 { … … 1641 1643 1642 1644 /* First write protect the page again to catch all write accesses. (before checking for changes -> SMP) */ 1643 int rc = PGMHandlerPhysicalReset(pVM, pPage->GCPhys & PAGE_BASE_GC_MASK);1645 int rc = PGMHandlerPhysicalReset(pVM, pPage->GCPhys & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK); 1644 1646 Assert(rc == VINF_SUCCESS); 1645 1647 pPage->fDirty = false; -
trunk/src/VBox/VMM/VMMAll/VMXAllTemplate.cpp.h
r93930 r93931 8520 8520 8521 8521 RTGCPHYS GCPhys = VCPU_2_VMXSTATE(pVCpu).vmx.u64GstMsrApicBase; /* Always up-to-date, as it is not part of the VMCS. */ 8522 GCPhys &= PAGE_BASE_GC_MASK;8522 GCPhys &= ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK; 8523 8523 GCPhys += VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(pVmxTransient->uExitQual); 8524 8524 Log4Func(("Linear access uAccessType=%#x GCPhys=%#RGp Off=%#x\n", uAccessType, GCPhys, -
trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
r93574 r93931 7926 7926 { 7927 7927 RTGCPHYS GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu); 7928 GCPhysApicBase &= PAGE_BASE_GC_MASK;7928 GCPhysApicBase &= ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK; 7929 7929 7930 7930 if (GCPhysFaultAddr == GCPhysApicBase + XAPIC_OFF_TPR) … … 8281 8281 RTGCPHYS GCPhysApicBase; 8282 8282 GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu); 8283 GCPhysApicBase &= PAGE_BASE_GC_MASK;8283 GCPhysApicBase &= ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK; 8284 8284 8285 8285 /* Check if the page at the fault-address is the APIC base. */ -
trunk/src/VBox/VMM/VMMR3/CPUM.cpp
r93905 r93931 4186 4186 { 4187 4187 /* translate the address */ 4188 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;4188 pState->pvPageGC = GCPtr & ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK; 4189 4189 4190 4190 /* Release mapping lock previously acquired. */ -
trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp
r93554 r93931 221 221 222 222 /* translate the address */ 223 pState->GCPtrPage = GCPtr & PAGE_BASE_GC_MASK;223 pState->GCPtrPage = GCPtr & ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK; 224 224 if (pState->fLocked) 225 225 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock); -
trunk/src/VBox/VMM/VMMR3/PGMPool.cpp
r93716 r93931 703 703 704 704 /* First write protect the page again to catch all write accesses. (before checking for changes -> SMP) */ 705 int rc = PGMHandlerPhysicalReset(pVM, pPage->GCPhys & PAGE_BASE_GC_MASK);705 int rc = PGMHandlerPhysicalReset(pVM, pPage->GCPhys & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK); 706 706 AssertRCSuccess(rc); 707 707 pPage->fDirty = false;
Note:
See TracChangeset
for help on using the changeset viewer.