Changeset 9411 in vbox for trunk/src/VBox/VMM

Timestamp:

Jun 5, 2008 11:41:38 AM (17 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

31649

Message:

Use a union for esp & rsp, so they are in-sync.

Location:

trunk/src/VBox/VMM

Files:

• CPUMInternal.mac (modified) (2 diffs)
• VMMR0/HWACCMR0.cpp (modified) (1 diff)
• VMMR0/HWSVMR0.cpp (modified) (3 diffs)
• VMMR0/HWVMXR0.cpp (modified) (5 diffs)
• VMMSwitcher/AMD64ToPAE.asm (modified) (1 diff)
• VMMSwitcher/PAEand32Bit.mac (modified) (1 diff)

trunk/src/VBox/VMM/CPUMInternal.mac

@@ -181 +181 @@
     .Hyper.edx            resq    1
     .Hyper.ecx            resq    1
-    .Hyper.esp            resd    1
+    .Hyper.esp            resq    1
+    .Hyper.lss_esp        resd    1
     .Hyper.ss             resw    1
     .Hyper.ssPadding      resw    1
-    .Hyper.rsp            resq    1
     .Hyper.gs             resw    1
     .Hyper.gsPadding      resw    1
@@ -297 +297 @@
     .Guest.edx            resq    1
     .Guest.ecx            resq    1
-    .Guest.esp            resd    1
+    .Guest.esp            resq    1
+    .Guest.lss_esp        resd    1
     .Guest.ss             resw    1
     .Guest.ssPadding      resw    1
-    .Guest.rsp            resq    1
     .Guest.gs             resw    1
     .Guest.gsPadding      resw    1

trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp

@@ -738 +738 @@
     /* Setup the register and mask according to the current execution mode. */
     if (pCtx->msrEFER & MSR_K6_EFER_LMA)
-        pVM->hwaccm.s.u64RegisterMask = 0xFFFFFFFFFFFFFFFFULL;
+        pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFFFFFFFFFF);
     else
-        pVM->hwaccm.s.u64RegisterMask = 0xFFFFFFFFULL;
+        pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF);
 
     rc  = HWACCMR0Globals.pfnEnterSession(pVM, &HWACCMR0Globals.aCpuInfo[idCpu]);

trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

@@ -686 +686 @@
 
     /* EIP, ESP and EFLAGS */
-    pVMCB->guest.u64RIP    = pCtx->eip;
-    pVMCB->guest.u64RSP    = pCtx->esp;
+    pVMCB->guest.u64RIP    = pCtx->rip;
+    pVMCB->guest.u64RSP    = pCtx->rsp;
     pVMCB->guest.u64RFlags = pCtx->eflags.u32;
 
@@ -694 +694 @@
 
     /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
-    pVMCB->guest.u64RAX    = pCtx->eax;
+    pVMCB->guest.u64RAX    = pCtx->rax;
 
     /* vmrun will fail without MSR_K6_EFER_SVME. */
@@ -1046 +1046 @@
 
     /* Let's first sync back eip, esp, and eflags. */
-    pCtx->eip        = pVMCB->guest.u64RIP;
-    pCtx->esp        = pVMCB->guest.u64RSP;
+    pCtx->rip        = pVMCB->guest.u64RIP;
+    pCtx->rsp        = pVMCB->guest.u64RSP;
     pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
     /* eax is saved/restore across the vmrun instruction */
-    pCtx->eax        = pVMCB->guest.u64RAX;
+    pCtx->rax        = pVMCB->guest.u64RAX;
 
     /* Guest CPU context: ES, CS, SS, DS, FS, GS. */

trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

@@ -899 +899 @@
 
     /* EIP, ESP and EFLAGS */
-    rc  = VMXWriteVMCS(VMX_VMCS_GUEST_RIP,              pCtx->eip);
-    rc |= VMXWriteVMCS(VMX_VMCS_GUEST_RSP,              pCtx->esp);
+    rc  = VMXWriteVMCS(VMX_VMCS_GUEST_RIP,              pCtx->rip);
+    rc |= VMXWriteVMCS(VMX_VMCS_GUEST_RSP,              pCtx->rsp);
     AssertRC(rc);
 
@@ -951 +951 @@
     val = (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF);
 
-    /* 64 bits guest mode? */
-    if (pCtx->msrEFER & MSR_K6_EFER_LMA)
-        val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
-
     /* Mask away the bits that the CPU doesn't support */
     /** @todo make sure they don't conflict with the above requirements. */
@@ -961 +957 @@
     rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
     AssertRC(rc);
+
+    /* 64 bits guest mode? */
+    if (pCtx->msrEFER & MSR_K6_EFER_LMA)
+        val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
 
     /* Done. */
@@ -1338 +1338 @@
     AssertRC(rc);
 
+    /* Let's first sync back eip, esp, and eflags. */
+    rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP,              &val);
+    AssertRC(rc);
+    pCtx->rip               = val;
+    rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP,              &val);
+    AssertRC(rc);
+    pCtx->rsp               = val;
+    rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS,           &val);
+    AssertRC(rc);
+    pCtx->eflags.u32        = val;
+
     /* Take care of instruction fusing (sti, mov ss) */
     rc |= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
@@ -1349 +1360 @@
     else
         VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
-
-    /* Let's first sync back eip, esp, and eflags. */
-    rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP,              &val);
-    AssertRC(rc);
-    pCtx->eip               = val;
-    rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP,              &val);
-    AssertRC(rc);
-    pCtx->esp               = val;
-    rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS,           &val);
-    AssertRC(rc);
-    pCtx->eflags.u32        = val;
 
     /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */

trunk/src/VBox/VMM/VMMSwitcher/AMD64ToPAE.asm

@@ -453 +453 @@
     lidt    [edx + CPUM.Hyper.idtr]
 
-    ; Setup stack
+    ; Setup stack; use the lss_esp, ss pair for lss
     DEBUG_CHAR('3')
-    lss     esp, [edx + CPUM.Hyper.esp]
+    mov     eax, [edx + CPUM.Hyper.esp]
+    mov     [edx + CPUM.Hyper.lss_esp], eax
+    lss     esp, [edx + CPUM.Hyper.lss_esp]
 
     ; Restore TSS selector; must mark it as not busy before using ltr (!)

trunk/src/VBox/VMM/VMMSwitcher/PAEand32Bit.mac

@@ -289 +289 @@
     mov     fs, eax
 
-    ; Setup stack
+    ; Setup stack; use the lss_esp, ss pair for lss
     DEBUG_CHAR('3')
+    mov     eax, [edx + CPUM.Hyper.esp]
+    mov     [edx + CPUM.Hyper.lss_esp], eax
     lss     esp, [edx + CPUM.Hyper.esp]