VirtualBox

Changeset 94190 in vbox for trunk/src/VBox/VMM


Ignore:
Timestamp:
Mar 11, 2022 9:30:23 PM (3 years ago)
Author:
vboxsync
Message:

VMM/IEM: Use the C implementation for the Intel and AMD EFLAGS variants of the other shift instructions too. bugref:9898

Location:
trunk/src/VBox/VMM/VMMAll
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm

    r94178 r94190  
    13951395; Makes ASSUMPTIONS about A0, A1 and A2 assignments.
    13961396;
     1397; @note the _intel and _amd variants are implemented in C.
     1398;
    13971399%macro IEMIMPL_SHIFT_OP 3
    13981400BEGINCODE
    1399 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u8_intel, 12
    1400 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u8_amd, 12
    14011401BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u8, 12
    14021402        PROLOGUE_3_ARGS
    … …  
    14131413ENDPROC iemAImpl_ %+ %1 %+ _u8
    14141414
    1415 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16_intel, 12
    1416 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16_amd, 12
    14171415BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 12
    14181416        PROLOGUE_3_ARGS
    … …  
    14291427ENDPROC iemAImpl_ %+ %1 %+ _u16
    14301428
    1431 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32_intel, 12
    1432 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32_amd, 12
    14331429BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 12
    14341430        PROLOGUE_3_ARGS
    … …  
    14461442
    14471443 %ifdef RT_ARCH_AMD64
    1448 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64_intel, 12
    1449 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64_amd, 12
    14501444BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 12
    14511445        PROLOGUE_3_ARGS

  • trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp

    r94178 r94190  
    22022202# endif
    22032203
     2204#endif /* !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY) */
     2205
    22042206
    22052207/*********************************************************************************************************************************
    … …  
    22362238    } \
    22372239}
     2240
     2241#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
    22382242EMIT_ROL(64, RT_NOTHING, 1, ASMRotateLeftU64)
     2243#endif
    22392244EMIT_ROL(64, _intel,     1, ASMRotateLeftU64)
    22402245EMIT_ROL(64, _amd,       0, ASMRotateLeftU64)
    2241 # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
     2246
     2247#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
    22422248EMIT_ROL(32, RT_NOTHING, 1, ASMRotateLeftU32)
     2249#endif
    22432250EMIT_ROL(32, _intel,     1, ASMRotateLeftU32)
    22442251EMIT_ROL(32, _amd,       0, ASMRotateLeftU32)
    … …  
    22482255    return (uValue << cShift) | (uValue >> (16 - cShift));
    22492256}
     2257#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
    22502258EMIT_ROL(16, RT_NOTHING, 1, iemAImpl_rol_u16_hlp)
     2259#endif
    22512260EMIT_ROL(16, _intel,     1, iemAImpl_rol_u16_hlp)
    22522261EMIT_ROL(16, _amd,       0, iemAImpl_rol_u16_hlp)
    … …  
    22562265    return (uValue << cShift) | (uValue >> (8 - cShift));
    22572266}
     2267#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
    22582268EMIT_ROL(8, RT_NOTHING, 1, iemAImpl_rol_u8_hlp)
     2269#endif
    22592270EMIT_ROL(8, _intel,     1, iemAImpl_rol_u8_hlp)
    22602271EMIT_ROL(8, _amd,       0, iemAImpl_rol_u8_hlp)
    2261 # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
    22622272
    22632273
    … …  
    22892299    } \
    22902300}
     2301
     2302#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
    22912303EMIT_ROR(64, RT_NOTHING, 1, ASMRotateRightU64)
     2304#endif
    22922305EMIT_ROR(64, _intel,     1, ASMRotateRightU64)
    22932306EMIT_ROR(64, _amd,       0, ASMRotateRightU64)
    2294 # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
     2307
     2308#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
    22952309EMIT_ROR(32, RT_NOTHING, 1, ASMRotateRightU32)
     2310#endif
    22962311EMIT_ROR(32, _intel,     1, ASMRotateRightU32)
    22972312EMIT_ROR(32, _amd,       0, ASMRotateRightU32)
    … …  
    23012316    return (uValue >> cShift) | (uValue << (16 - cShift));
    23022317}
     2318#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
    23032319EMIT_ROR(16, RT_NOTHING, 1, iemAImpl_ror_u16_hlp)
     2320#endif
    23042321EMIT_ROR(16, _intel,     1, iemAImpl_ror_u16_hlp)
    23052322EMIT_ROR(16, _amd,       0, iemAImpl_ror_u16_hlp)
    … …  
    23092326    return (uValue >> cShift) | (uValue << (8 - cShift));
    23102327}
     2328#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
    23112329EMIT_ROR(8, RT_NOTHING, 1, iemAImpl_ror_u8_hlp)
     2330#endif
    23122331EMIT_ROR(8, _intel,     1, iemAImpl_ror_u8_hlp)
    23132332EMIT_ROR(8, _amd,       0, iemAImpl_ror_u8_hlp)
    2314 # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
    23152333
    23162334
    … …  
    23482366    } \
    23492367}
     2368
     2369#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
    23502370EMIT_RCL(64, RT_NOTHING, 1)
     2371#endif
    23512372EMIT_RCL(64, _intel,     1)
    23522373EMIT_RCL(64, _amd,       0)
    2353 # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
     2374
     2375#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
    23542376EMIT_RCL(32, RT_NOTHING, 1)
     2377#endif
    23552378EMIT_RCL(32, _intel,     1)
    23562379EMIT_RCL(32, _amd,       0)
     2380
     2381#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
    23572382EMIT_RCL(16, RT_NOTHING, 1)
     2383#endif
    23582384EMIT_RCL(16, _intel,     1)
    23592385EMIT_RCL(16, _amd,       0)
     2386
     2387#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
    23602388EMIT_RCL(8,  RT_NOTHING, 1)
     2389#endif
    23612390EMIT_RCL(8,  _intel,     1)
    23622391EMIT_RCL(8,  _amd,       0)
    2363 # endif
    23642392
    23652393
    … …  
    23972425    } \
    23982426}
     2427
     2428#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
    23992429EMIT_RCR(64, RT_NOTHING, 1)
     2430#endif
    24002431EMIT_RCR(64, _intel,     1)
    24012432EMIT_RCR(64, _amd,       0)
    2402 # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
     2433
     2434#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
    24032435EMIT_RCR(32, RT_NOTHING, 1)
     2436#endif
    24042437EMIT_RCR(32, _intel,     1)
    24052438EMIT_RCR(32, _amd,       0)
     2439
     2440#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
    24062441EMIT_RCR(16, RT_NOTHING, 1)
     2442#endif
    24072443EMIT_RCR(16, _intel,     1)
    24082444EMIT_RCR(16, _amd,       0)
     2445
     2446#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
    24092447EMIT_RCR(8,  RT_NOTHING, 1)
     2448#endif
    24102449EMIT_RCR(8,  _intel,     1)
    24112450EMIT_RCR(8,  _amd,       0)
    2412 # endif
    24132451
    24142452
    … …  
    24442482    } \
    24452483}
     2484
     2485#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
    24462486EMIT_SHL(64, RT_NOTHING, 1)
     2487#endif
    24472488EMIT_SHL(64, _intel,     1)
    24482489EMIT_SHL(64, _amd,       0)
    2449 # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
     2490
     2491#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
    24502492EMIT_SHL(32, RT_NOTHING, 1)
     2493#endif
    24512494EMIT_SHL(32, _intel,     1)
    24522495EMIT_SHL(32, _amd,       0)
     2496
     2497#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
    24532498EMIT_SHL(16, RT_NOTHING, 1)
     2499#endif
    24542500EMIT_SHL(16, _intel,     1)
    24552501EMIT_SHL(16, _amd,       0)
     2502
     2503#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
    24562504EMIT_SHL(8,  RT_NOTHING, 1)
     2505#endif
    24572506EMIT_SHL(8,  _intel,     1)
    24582507EMIT_SHL(8,  _amd,       0)
    2459 # endif
    24602508
    24612509
    … …  
    24882536    } \
    24892537}
     2538
     2539#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
    24902540EMIT_SHR(64, RT_NOTHING, 1)
     2541#endif
    24912542EMIT_SHR(64, _intel,     1)
    24922543EMIT_SHR(64, _amd,       0)
    2493 # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
     2544
     2545#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
    24942546EMIT_SHR(32, RT_NOTHING, 1)
     2547#endif
    24952548EMIT_SHR(32, _intel,     1)
    24962549EMIT_SHR(32, _amd,       0)
     2550
     2551#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
    24972552EMIT_SHR(16, RT_NOTHING, 1)
     2553#endif
    24982554EMIT_SHR(16, _intel,     1)
    24992555EMIT_SHR(16, _amd,       0)
     2556
     2557#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
    25002558EMIT_SHR(8,  RT_NOTHING, 1)
     2559#endif
    25012560EMIT_SHR(8,  _intel,     1)
    25022561EMIT_SHR(8,  _amd,       0)
    2503 # endif
    25042562
    25052563
    … …  
    25312589    } \
    25322590}
     2591
     2592#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
    25332593EMIT_SAR(64, RT_NOTHING, 1)
     2594#endif
    25342595EMIT_SAR(64, _intel,     1)
    25352596EMIT_SAR(64, _amd,       0)
    2536 # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
     2597
     2598#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
    25372599EMIT_SAR(32, RT_NOTHING, 1)
     2600#endif
    25382601EMIT_SAR(32, _intel,     1)
    25392602EMIT_SAR(32, _amd,       0)
     2603
     2604#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
    25402605EMIT_SAR(16, RT_NOTHING, 1)
     2606#endif
    25412607EMIT_SAR(16, _intel,     1)
    25422608EMIT_SAR(16, _amd,       0)
     2609
     2610#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
    25432611EMIT_SAR(8,  RT_NOTHING, 1)
     2612#endif
    25442613EMIT_SAR(8,  _intel,     1)
    25452614EMIT_SAR(8,  _amd,       0)
    2546 # endif
    2547 
    2548 #endif /* !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY) */
    25492615
    25502616
    … …  
    25912657    } \
    25922658}
     2659
    25932660#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
    25942661EMIT_SHLD(64, uint64_t, RT_NOTHING, 1)
    2595 #endif /* !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY) */
     2662#endif
    25962663EMIT_SHLD(64, uint64_t, _intel,     1)
    25972664EMIT_SHLD(64, uint64_t, _amd,       0)
     2665
    25982666#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
    25992667EMIT_SHLD(32, uint32_t, RT_NOTHING, 1)
    … …  
    26012669EMIT_SHLD(32, uint32_t, _intel,     1)
    26022670EMIT_SHLD(32, uint32_t, _amd,       0)
     2671
    26032672#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
    26042673EMIT_SHLD(16, uint16_t, RT_NOTHING, 1)
    … …  
    26522721    } \
    26532722}
     2723
    26542724#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
    26552725EMIT_SHRD(64, uint64_t, RT_NOTHING, 1)
    2656 #endif /* !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY) */
     2726#endif
    26572727EMIT_SHRD(64, uint64_t, _intel,     1)
    26582728EMIT_SHRD(64, uint64_t, _amd,       0)
     2729
    26592730#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
    26602731EMIT_SHRD(32, uint32_t, RT_NOTHING, 1)
    … …  
    26622733EMIT_SHRD(32, uint32_t, _intel,     1)
    26632734EMIT_SHRD(32, uint32_t, _amd,       0)
     2735
    26642736#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
    26652737EMIT_SHRD(16, uint16_t, RT_NOTHING, 1)
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