Index: /trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm	(revision 94190)
+++ /trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm	(revision 94191)
@@ -1445,11 +1445,11 @@
         PROLOGUE_3_ARGS
         IEM_MAYBE_LOAD_FLAGS A2, %2, %3
- %ifdef ASM_CALL64_GCC
+  %ifdef ASM_CALL64_GCC
         mov     cl, A1_8
         %1      qword [A0], cl
- %else
+  %else
         xchg    A1, A0
         %1      qword [A1], cl
- %endif
+  %endif
         IEM_SAVE_FLAGS       A2, %2, %3
         EPILOGUE_3_ARGS
Index: /trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp	(revision 94190)
+++ /trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp	(revision 94191)
@@ -2212,14 +2212,14 @@
  * ROL
  */
-
-#define EMIT_ROL(a_cBitsWidth, a_Suffix, a_fIntelFlags, a_fnHlp) \
-IEM_DECL_IMPL_DEF(void, RT_CONCAT3(iemAImpl_rol_u,a_cBitsWidth,a_Suffix),(uint ## a_cBitsWidth ## _t *puDst, \
-                                                                          uint8_t cShift, uint32_t *pfEFlags)) \
+#define EMIT_ROL(a_cBitsWidth, a_uType, a_Suffix, a_fIntelFlags, a_fnHlp) \
+IEM_DECL_IMPL_DEF(void, RT_CONCAT3(iemAImpl_rol_u,a_cBitsWidth,a_Suffix),(a_uType *puDst, uint8_t cShift, uint32_t *pfEFlags)) \
 { \
-    cShift &= a_cBitsWidth - 1; \
+    cShift &= a_cBitsWidth >= 32 ? a_cBitsWidth - 1 : 31; \
     if (cShift) \
     { \
-        uint ## a_cBitsWidth ## _t const uDst    = *puDst; \
-        uint ## a_cBitsWidth ## _t const uResult = a_fnHlp(uDst, cShift); \
+        if (a_cBitsWidth < 32) \
+            cShift &= a_cBitsWidth - 1; \
+        a_uType const uDst    = *puDst; \
+        a_uType const uResult = a_fnHlp(uDst, cShift); \
         *puDst = uResult; \
         \
@@ -2240,14 +2240,14 @@
 
 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_ROL(64, RT_NOTHING, 1, ASMRotateLeftU64)
-#endif
-EMIT_ROL(64, _intel,     1, ASMRotateLeftU64)
-EMIT_ROL(64, _amd,       0, ASMRotateLeftU64)
+EMIT_ROL(64, uint64_t, RT_NOTHING, 1, ASMRotateLeftU64)
+#endif
+EMIT_ROL(64, uint64_t, _intel,     1, ASMRotateLeftU64)
+EMIT_ROL(64, uint64_t, _amd,       0, ASMRotateLeftU64)
 
 #if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_ROL(32, RT_NOTHING, 1, ASMRotateLeftU32)
-#endif
-EMIT_ROL(32, _intel,     1, ASMRotateLeftU32)
-EMIT_ROL(32, _amd,       0, ASMRotateLeftU32)
+EMIT_ROL(32, uint32_t, RT_NOTHING, 1, ASMRotateLeftU32)
+#endif
+EMIT_ROL(32, uint32_t, _intel,     1, ASMRotateLeftU32)
+EMIT_ROL(32, uint32_t, _amd,       0, ASMRotateLeftU32)
 
 DECL_FORCE_INLINE(uint16_t) iemAImpl_rol_u16_hlp(uint16_t uValue, uint8_t cShift)
@@ -2256,8 +2256,8 @@
 }
 #if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_ROL(16, RT_NOTHING, 1, iemAImpl_rol_u16_hlp)
-#endif
-EMIT_ROL(16, _intel,     1, iemAImpl_rol_u16_hlp)
-EMIT_ROL(16, _amd,       0, iemAImpl_rol_u16_hlp)
+EMIT_ROL(16, uint16_t, RT_NOTHING, 1, iemAImpl_rol_u16_hlp)
+#endif
+EMIT_ROL(16, uint16_t, _intel,     1, iemAImpl_rol_u16_hlp)
+EMIT_ROL(16, uint16_t, _amd,       0, iemAImpl_rol_u16_hlp)
 
 DECL_FORCE_INLINE(uint8_t) iemAImpl_rol_u8_hlp(uint8_t uValue, uint8_t cShift)
@@ -2266,8 +2266,8 @@
 }
 #if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_ROL(8, RT_NOTHING, 1, iemAImpl_rol_u8_hlp)
-#endif
-EMIT_ROL(8, _intel,     1, iemAImpl_rol_u8_hlp)
-EMIT_ROL(8, _amd,       0, iemAImpl_rol_u8_hlp)
+EMIT_ROL(8,  uint8_t,  RT_NOTHING, 1, iemAImpl_rol_u8_hlp)
+#endif
+EMIT_ROL(8,  uint8_t,  _intel,     1, iemAImpl_rol_u8_hlp)
+EMIT_ROL(8,  uint8_t,  _amd,       0, iemAImpl_rol_u8_hlp)
 
 
@@ -2275,13 +2275,14 @@
  * ROR
  */
-#define EMIT_ROR(a_cBitsWidth, a_Suffix, a_fIntelFlags, a_fnHlp) \
-IEM_DECL_IMPL_DEF(void, RT_CONCAT3(iemAImpl_ror_u,a_cBitsWidth,a_Suffix),(uint ## a_cBitsWidth ## _t *puDst, \
-                                                                          uint8_t cShift, uint32_t *pfEFlags)) \
+#define EMIT_ROR(a_cBitsWidth, a_uType, a_Suffix, a_fIntelFlags, a_fnHlp) \
+IEM_DECL_IMPL_DEF(void, RT_CONCAT3(iemAImpl_ror_u,a_cBitsWidth,a_Suffix),(a_uType *puDst, uint8_t cShift, uint32_t *pfEFlags)) \
 { \
-    cShift &= a_cBitsWidth - 1; \
+    cShift &= a_cBitsWidth >= 32 ? a_cBitsWidth - 1 : 31; \
     if (cShift) \
     { \
-        uint ## a_cBitsWidth ## _t const uDst    = *puDst; \
-        uint ## a_cBitsWidth ## _t const uResult = a_fnHlp(uDst, cShift); \
+        if (a_cBitsWidth < 32) \
+            cShift &= a_cBitsWidth - 1; \
+        a_uType const uDst    = *puDst; \
+        a_uType const uResult = a_fnHlp(uDst, cShift); \
         *puDst = uResult; \
         \
@@ -2301,14 +2302,14 @@
 
 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_ROR(64, RT_NOTHING, 1, ASMRotateRightU64)
-#endif
-EMIT_ROR(64, _intel,     1, ASMRotateRightU64)
-EMIT_ROR(64, _amd,       0, ASMRotateRightU64)
+EMIT_ROR(64, uint64_t, RT_NOTHING, 1, ASMRotateRightU64)
+#endif
+EMIT_ROR(64, uint64_t, _intel,     1, ASMRotateRightU64)
+EMIT_ROR(64, uint64_t, _amd,       0, ASMRotateRightU64)
 
 #if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_ROR(32, RT_NOTHING, 1, ASMRotateRightU32)
-#endif
-EMIT_ROR(32, _intel,     1, ASMRotateRightU32)
-EMIT_ROR(32, _amd,       0, ASMRotateRightU32)
+EMIT_ROR(32, uint32_t, RT_NOTHING, 1, ASMRotateRightU32)
+#endif
+EMIT_ROR(32, uint32_t, _intel,     1, ASMRotateRightU32)
+EMIT_ROR(32, uint32_t, _amd,       0, ASMRotateRightU32)
 
 DECL_FORCE_INLINE(uint16_t) iemAImpl_ror_u16_hlp(uint16_t uValue, uint8_t cShift)
@@ -2317,8 +2318,8 @@
 }
 #if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_ROR(16, RT_NOTHING, 1, iemAImpl_ror_u16_hlp)
-#endif
-EMIT_ROR(16, _intel,     1, iemAImpl_ror_u16_hlp)
-EMIT_ROR(16, _amd,       0, iemAImpl_ror_u16_hlp)
+EMIT_ROR(16, uint16_t, RT_NOTHING, 1, iemAImpl_ror_u16_hlp)
+#endif
+EMIT_ROR(16, uint16_t, _intel,     1, iemAImpl_ror_u16_hlp)
+EMIT_ROR(16, uint16_t, _amd,       0, iemAImpl_ror_u16_hlp)
 
 DECL_FORCE_INLINE(uint8_t) iemAImpl_ror_u8_hlp(uint8_t uValue, uint8_t cShift)
@@ -2327,8 +2328,8 @@
 }
 #if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_ROR(8, RT_NOTHING, 1, iemAImpl_ror_u8_hlp)
-#endif
-EMIT_ROR(8, _intel,     1, iemAImpl_ror_u8_hlp)
-EMIT_ROR(8, _amd,       0, iemAImpl_ror_u8_hlp)
+EMIT_ROR(8,  uint8_t,  RT_NOTHING, 1, iemAImpl_ror_u8_hlp)
+#endif
+EMIT_ROR(8,  uint8_t,  _intel,     1, iemAImpl_ror_u8_hlp)
+EMIT_ROR(8,  uint8_t,  _amd,       0, iemAImpl_ror_u8_hlp)
 
 
@@ -2336,13 +2337,14 @@
  * RCL
  */
-#define EMIT_RCL(a_cBitsWidth, a_Suffix, a_fIntelFlags) \
-IEM_DECL_IMPL_DEF(void, RT_CONCAT3(iemAImpl_rcl_u,a_cBitsWidth,a_Suffix),(uint ## a_cBitsWidth ## _t *puDst, \
-                                                                          uint8_t cShift, uint32_t *pfEFlags)) \
+#define EMIT_RCL(a_cBitsWidth, a_uType, a_Suffix, a_fIntelFlags) \
+IEM_DECL_IMPL_DEF(void, RT_CONCAT3(iemAImpl_rcl_u,a_cBitsWidth,a_Suffix),(a_uType *puDst, uint8_t cShift, uint32_t *pfEFlags)) \
 { \
-    cShift &= a_cBitsWidth - 1; \
+    cShift &= a_cBitsWidth >= 32 ? a_cBitsWidth - 1 : 31; \
     if (cShift) \
     { \
-        uint ## a_cBitsWidth ## _t const uDst    = *puDst; \
-        uint ## a_cBitsWidth ## _t       uResult = uDst << cShift; \
+        if (a_cBitsWidth < 32) \
+            cShift %= a_cBitsWidth + 1; \
+        a_uType const uDst    = *puDst; \
+        a_uType       uResult = uDst << cShift; \
         if (cShift > 1) \
             uResult |= uDst >> (a_cBitsWidth + 1 - cShift); \
@@ -2351,5 +2353,5 @@
         uint32_t fEfl     = *pfEFlags; \
         uint32_t fInCarry = fEfl & X86_EFL_CF; \
-        uResult |= (uint ## a_cBitsWidth ## _t)fInCarry << (cShift - 1); \
+        uResult |= (a_uType)fInCarry << (cShift - 1); \
         \
         *puDst = uResult; \
@@ -2357,5 +2359,6 @@
         /* Calc EFLAGS. */ \
         fEfl &= ~(X86_EFL_CF | X86_EFL_OF); \
-        uint32_t const fOutCarry = (uDst >> (a_cBitsWidth - cShift)) & X86_EFL_CF; \
+        uint32_t const fOutCarry = a_cBitsWidth >= 32 || cShift \
+                                 ? (uDst >> (a_cBitsWidth - cShift)) & X86_EFL_CF : fInCarry; \
         fEfl |= fOutCarry; \
         if (!a_fIntelFlags) /* AMD 3990X: According to the last sub-shift: */ \
@@ -2368,26 +2371,26 @@
 
 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_RCL(64, RT_NOTHING, 1)
-#endif
-EMIT_RCL(64, _intel,     1)
-EMIT_RCL(64, _amd,       0)
+EMIT_RCL(64, uint64_t, RT_NOTHING, 1)
+#endif
+EMIT_RCL(64, uint64_t, _intel,     1)
+EMIT_RCL(64, uint64_t, _amd,       0)
 
 #if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_RCL(32, RT_NOTHING, 1)
-#endif
-EMIT_RCL(32, _intel,     1)
-EMIT_RCL(32, _amd,       0)
+EMIT_RCL(32, uint32_t, RT_NOTHING, 1)
+#endif
+EMIT_RCL(32, uint32_t, _intel,     1)
+EMIT_RCL(32, uint32_t, _amd,       0)
 
 #if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_RCL(16, RT_NOTHING, 1)
-#endif
-EMIT_RCL(16, _intel,     1)
-EMIT_RCL(16, _amd,       0)
+EMIT_RCL(16, uint16_t, RT_NOTHING, 1)
+#endif
+EMIT_RCL(16, uint16_t, _intel,     1)
+EMIT_RCL(16, uint16_t, _amd,       0)
 
 #if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_RCL(8,  RT_NOTHING, 1)
-#endif
-EMIT_RCL(8,  _intel,     1)
-EMIT_RCL(8,  _amd,       0)
+EMIT_RCL(8,  uint8_t,  RT_NOTHING, 1)
+#endif
+EMIT_RCL(8,  uint8_t,  _intel,     1)
+EMIT_RCL(8,  uint8_t,  _amd,       0)
 
 
@@ -2395,13 +2398,14 @@
  * RCR
  */
-#define EMIT_RCR(a_cBitsWidth, a_Suffix, a_fIntelFlags) \
-IEM_DECL_IMPL_DEF(void, RT_CONCAT3(iemAImpl_rcr_u,a_cBitsWidth,a_Suffix),(uint ## a_cBitsWidth ##_t *puDst, \
-                                                                          uint8_t cShift, uint32_t *pfEFlags)) \
+#define EMIT_RCR(a_cBitsWidth, a_uType, a_Suffix, a_fIntelFlags) \
+IEM_DECL_IMPL_DEF(void, RT_CONCAT3(iemAImpl_rcr_u,a_cBitsWidth,a_Suffix),(a_uType *puDst, uint8_t cShift, uint32_t *pfEFlags)) \
 { \
-    cShift &= a_cBitsWidth - 1; \
+    cShift &= a_cBitsWidth >= 32 ? a_cBitsWidth - 1 : 31; \
     if (cShift) \
     { \
-        uint ## a_cBitsWidth ## _t const uDst    = *puDst; \
-        uint ## a_cBitsWidth ## _t       uResult = uDst >> cShift; \
+        if (a_cBitsWidth < 32) \
+            cShift %= a_cBitsWidth + 1; \
+        a_uType const uDst    = *puDst; \
+        a_uType       uResult = uDst >> cShift; \
         if (cShift > 1) \
             uResult |= uDst << (a_cBitsWidth + 1 - cShift); \
@@ -2410,5 +2414,5 @@
         uint32_t fEfl     = *pfEFlags; \
         uint32_t fInCarry = fEfl & X86_EFL_CF; \
-        uResult |= (uint ## a_cBitsWidth ## _t)fInCarry << (a_cBitsWidth - cShift); \
+        uResult |= (a_uType)fInCarry << (a_cBitsWidth - cShift); \
         *puDst = uResult; \
         \
@@ -2427,26 +2431,26 @@
 
 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_RCR(64, RT_NOTHING, 1)
-#endif
-EMIT_RCR(64, _intel,     1)
-EMIT_RCR(64, _amd,       0)
+EMIT_RCR(64, uint64_t, RT_NOTHING, 1)
+#endif
+EMIT_RCR(64, uint64_t, _intel,     1)
+EMIT_RCR(64, uint64_t, _amd,       0)
 
 #if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_RCR(32, RT_NOTHING, 1)
-#endif
-EMIT_RCR(32, _intel,     1)
-EMIT_RCR(32, _amd,       0)
+EMIT_RCR(32, uint32_t, RT_NOTHING, 1)
+#endif
+EMIT_RCR(32, uint32_t, _intel,     1)
+EMIT_RCR(32, uint32_t, _amd,       0)
 
 #if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_RCR(16, RT_NOTHING, 1)
-#endif
-EMIT_RCR(16, _intel,     1)
-EMIT_RCR(16, _amd,       0)
+EMIT_RCR(16, uint16_t, RT_NOTHING, 1)
+#endif
+EMIT_RCR(16, uint16_t, _intel,     1)
+EMIT_RCR(16, uint16_t, _amd,       0)
 
 #if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_RCR(8,  RT_NOTHING, 1)
-#endif
-EMIT_RCR(8,  _intel,     1)
-EMIT_RCR(8,  _amd,       0)
+EMIT_RCR(8,  uint8_t,  RT_NOTHING, 1)
+#endif
+EMIT_RCR(8,  uint8_t,  _intel,     1)
+EMIT_RCR(8,  uint8_t,  _amd,       0)
 
 
@@ -2454,13 +2458,12 @@
  * SHL
  */
-#define EMIT_SHL(a_cBitsWidth, a_Suffix, a_fIntelFlags) \
-IEM_DECL_IMPL_DEF(void, RT_CONCAT3(iemAImpl_shl_u,a_cBitsWidth,a_Suffix),(uint ## a_cBitsWidth ## _t *puDst, \
-                                                                          uint8_t cShift, uint32_t *pfEFlags)) \
+#define EMIT_SHL(a_cBitsWidth, a_uType, a_Suffix, a_fIntelFlags) \
+IEM_DECL_IMPL_DEF(void, RT_CONCAT3(iemAImpl_shl_u,a_cBitsWidth,a_Suffix),(a_uType *puDst, uint8_t cShift, uint32_t *pfEFlags)) \
 { \
-    cShift &= a_cBitsWidth - 1; \
+    cShift &= a_cBitsWidth >= 32 ? a_cBitsWidth - 1 : 31; \
     if (cShift) \
     { \
-        uint ## a_cBitsWidth ##_t const uDst  = *puDst; \
-        uint ## a_cBitsWidth ##_t       uResult = uDst << cShift; \
+        a_uType const uDst  = *puDst; \
+        a_uType       uResult = uDst << cShift; \
         *puDst = uResult; \
         \
@@ -2484,26 +2487,26 @@
 
 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_SHL(64, RT_NOTHING, 1)
-#endif
-EMIT_SHL(64, _intel,     1)
-EMIT_SHL(64, _amd,       0)
+EMIT_SHL(64, uint64_t, RT_NOTHING, 1)
+#endif
+EMIT_SHL(64, uint64_t, _intel,     1)
+EMIT_SHL(64, uint64_t, _amd,       0)
 
 #if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_SHL(32, RT_NOTHING, 1)
-#endif
-EMIT_SHL(32, _intel,     1)
-EMIT_SHL(32, _amd,       0)
+EMIT_SHL(32, uint32_t, RT_NOTHING, 1)
+#endif
+EMIT_SHL(32, uint32_t, _intel,     1)
+EMIT_SHL(32, uint32_t, _amd,       0)
 
 #if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_SHL(16, RT_NOTHING, 1)
-#endif
-EMIT_SHL(16, _intel,     1)
-EMIT_SHL(16, _amd,       0)
+EMIT_SHL(16, uint16_t, RT_NOTHING, 1)
+#endif
+EMIT_SHL(16, uint16_t, _intel,     1)
+EMIT_SHL(16, uint16_t, _amd,       0)
 
 #if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_SHL(8,  RT_NOTHING, 1)
-#endif
-EMIT_SHL(8,  _intel,     1)
-EMIT_SHL(8,  _amd,       0)
+EMIT_SHL(8,  uint8_t,  RT_NOTHING, 1)
+#endif
+EMIT_SHL(8,  uint8_t,  _intel,     1)
+EMIT_SHL(8,  uint8_t,  _amd,       0)
 
 
@@ -2511,13 +2514,12 @@
  * SHR
  */
-#define EMIT_SHR(a_cBitsWidth, a_Suffix, a_fIntelFlags) \
-IEM_DECL_IMPL_DEF(void, RT_CONCAT3(iemAImpl_shr_u,a_cBitsWidth,a_Suffix),(uint ## a_cBitsWidth ## _t *puDst, \
-                                                                          uint8_t cShift, uint32_t *pfEFlags)) \
+#define EMIT_SHR(a_cBitsWidth, a_uType, a_Suffix, a_fIntelFlags) \
+IEM_DECL_IMPL_DEF(void, RT_CONCAT3(iemAImpl_shr_u,a_cBitsWidth,a_Suffix),(a_uType *puDst, uint8_t cShift, uint32_t *pfEFlags)) \
 { \
-    cShift &= a_cBitsWidth - 1; \
+    cShift &= a_cBitsWidth >= 32 ? a_cBitsWidth - 1 : 31; \
     if (cShift) \
     { \
-        uint ## a_cBitsWidth ## _t const uDst    = *puDst; \
-        uint ## a_cBitsWidth ## _t       uResult = uDst >> cShift; \
+        a_uType const uDst    = *puDst; \
+        a_uType       uResult = uDst >> cShift; \
         *puDst = uResult; \
         \
@@ -2538,26 +2540,26 @@
 
 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_SHR(64, RT_NOTHING, 1)
-#endif
-EMIT_SHR(64, _intel,     1)
-EMIT_SHR(64, _amd,       0)
+EMIT_SHR(64, uint64_t, RT_NOTHING, 1)
+#endif
+EMIT_SHR(64, uint64_t, _intel,     1)
+EMIT_SHR(64, uint64_t, _amd,       0)
 
 #if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_SHR(32, RT_NOTHING, 1)
-#endif
-EMIT_SHR(32, _intel,     1)
-EMIT_SHR(32, _amd,       0)
+EMIT_SHR(32, uint32_t, RT_NOTHING, 1)
+#endif
+EMIT_SHR(32, uint32_t, _intel,     1)
+EMIT_SHR(32, uint32_t, _amd,       0)
 
 #if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_SHR(16, RT_NOTHING, 1)
-#endif
-EMIT_SHR(16, _intel,     1)
-EMIT_SHR(16, _amd,       0)
+EMIT_SHR(16, uint16_t, RT_NOTHING, 1)
+#endif
+EMIT_SHR(16, uint16_t, _intel,     1)
+EMIT_SHR(16, uint16_t, _amd,       0)
 
 #if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_SHR(8,  RT_NOTHING, 1)
-#endif
-EMIT_SHR(8,  _intel,     1)
-EMIT_SHR(8,  _amd,       0)
+EMIT_SHR(8,  uint8_t,  RT_NOTHING, 1)
+#endif
+EMIT_SHR(8,  uint8_t,  _intel,     1)
+EMIT_SHR(8,  uint8_t,  _amd,       0)
 
 
@@ -2565,13 +2567,12 @@
  * SAR
  */
-#define EMIT_SAR(a_cBitsWidth, a_Suffix, a_fIntelFlags) \
-IEM_DECL_IMPL_DEF(void, RT_CONCAT3(iemAImpl_sar_u,a_cBitsWidth,a_Suffix),(uint ## a_cBitsWidth ## _t *puDst, \
-                                                                          uint8_t cShift, uint32_t *pfEFlags)) \
+#define EMIT_SAR(a_cBitsWidth, a_uType, a_iType, a_Suffix, a_fIntelFlags) \
+IEM_DECL_IMPL_DEF(void, RT_CONCAT3(iemAImpl_sar_u,a_cBitsWidth,a_Suffix),(a_uType *puDst, uint8_t cShift, uint32_t *pfEFlags)) \
 { \
-    cShift &= a_cBitsWidth - 1; \
+    cShift &= a_cBitsWidth >= 32 ? a_cBitsWidth - 1 : 31; \
     if (cShift) \
     { \
-        uint ## a_cBitsWidth ## _t const uDst    = *puDst; \
-        uint ## a_cBitsWidth ## _t       uResult = (int ## a_cBitsWidth ## _t)uDst >> cShift; \
+        a_iType const iDst    = (a_iType)*puDst; \
+        a_uType       uResult = iDst >> cShift; \
         *puDst = uResult; \
         \
@@ -2580,5 +2581,5 @@
         AssertCompile(X86_EFL_CF_BIT == 0); \
         uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
-        fEfl |= (uDst >> (cShift - 1)) & X86_EFL_CF; \
+        fEfl |= (iDst >> (cShift - 1)) & X86_EFL_CF; \
         fEfl |= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
         fEfl |= X86_EFL_CALC_ZF(uResult); \
@@ -2591,26 +2592,26 @@
 
 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_SAR(64, RT_NOTHING, 1)
-#endif
-EMIT_SAR(64, _intel,     1)
-EMIT_SAR(64, _amd,       0)
+EMIT_SAR(64, uint64_t, int64_t, RT_NOTHING, 1)
+#endif
+EMIT_SAR(64, uint64_t, int64_t, _intel,     1)
+EMIT_SAR(64, uint64_t, int64_t, _amd,       0)
 
 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_SAR(32, RT_NOTHING, 1)
-#endif
-EMIT_SAR(32, _intel,     1)
-EMIT_SAR(32, _amd,       0)
+EMIT_SAR(32, uint32_t, int32_t, RT_NOTHING, 1)
+#endif
+EMIT_SAR(32, uint32_t, int32_t, _intel,     1)
+EMIT_SAR(32, uint32_t, int32_t, _amd,       0)
 
 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_SAR(16, RT_NOTHING, 1)
-#endif
-EMIT_SAR(16, _intel,     1)
-EMIT_SAR(16, _amd,       0)
+EMIT_SAR(16, uint16_t, int16_t, RT_NOTHING, 1)
+#endif
+EMIT_SAR(16, uint16_t, int16_t, _intel,     1)
+EMIT_SAR(16, uint16_t, int16_t, _amd,       0)
 
 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_SAR(8,  RT_NOTHING, 1)
-#endif
-EMIT_SAR(8,  _intel,     1)
-EMIT_SAR(8,  _amd,       0)
+EMIT_SAR(8,  uint8_t,  int8_t,  RT_NOTHING, 1)
+#endif
+EMIT_SAR(8,  uint8_t,  int8_t,  _intel,     1)
+EMIT_SAR(8,  uint8_t,  int8_t,  _amd,       0)
 
 
