- Timestamp:
- Apr 11, 2022 8:25:51 PM (3 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp
r94560 r94565 4460 4460 #else /* !IEM_WITH_FLOAT128_FOR_FPU - SoftFloat */ 4461 4461 4462 /** Initializer for the SoftFloat state structure. */ 4463 # define IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_FCW(a_fFcw) \ 4464 { \ 4465 softfloat_tininess_afterRounding, \ 4466 ((a_fFcw) & X86_FCW_RC_MASK) == X86_FCW_RC_NEAREST ? (uint8_t)softfloat_round_near_even \ 4467 : ((a_fFcw) & X86_FCW_RC_MASK) == X86_FCW_RC_UP ? (uint8_t)softfloat_round_max \ 4468 : ((a_fFcw) & X86_FCW_RC_MASK) == X86_FCW_RC_DOWN ? (uint8_t)softfloat_round_min \ 4469 : (uint8_t)softfloat_round_minMag, \ 4470 0, \ 4471 ((a_fFcw) & X86_FCW_PC_MASK) == X86_FCW_PC_53 ? (uint8_t)64 \ 4472 : ((a_fFcw) & X86_FCW_PC_MASK) == X86_FCW_PC_24 ? (uint8_t)32 : (uint8_t)80 \ 4473 } 4474 4475 /** Returns updated FSW from a SoftFloat state and exception mask (FCW). */ 4476 # define IEM_SOFTFLOAT_STATE_TO_FSW(a_fFsw, a_pSoftState, a_fFcw) \ 4477 ( (a_fFsw) \ 4478 | (uint16_t)((a_pSoftState)->exceptionFlags & softfloat_flag_c1) << (2) \ 4479 | ((a_pSoftState)->exceptionFlags & X86_FSW_XCPT_MASK) \ 4480 | ( ((a_pSoftState)->exceptionFlags & X86_FSW_XCPT_MASK) & (~(a_fFcw) & X86_FSW_XCPT_MASK) \ 4481 ? X86_FSW_ES | X86_FSW_B : 0) ) 4482 4462 4483 4463 4484 DECLINLINE(float128_t) iemFpuSoftF128Precision(float128_t r128, unsigned cBits, uint16_t fFcw = X86_FCW_RC_NEAREST) … … 4527 4548 4528 4549 4550 /** 4551 * Converts from the packed IPRT 80-bit floating point (RTFLOAT80U) format to 4552 * the SoftFloat extended 80-bit floating point format (extFloat80_t). 4553 * 4554 * This is only a structure format conversion, nothing else. 4555 */ 4529 4556 DECLINLINE(extFloat80_t) iemFpuSoftF80FromIprt(PCRTFLOAT80U pr80Val) 4530 4557 { … … 4533 4560 Tmp.signif = pr80Val->s2.uMantissa; 4534 4561 return Tmp; 4562 } 4563 4564 4565 /** 4566 * Converts from SoftFloat extended 80-bit floating point format (extFloat80_t) 4567 * to the packed IPRT 80-bit floating point (RTFLOAT80U) format. 4568 * 4569 * This is only a structure format conversion, nothing else. 4570 */ 4571 DECLINLINE(PRTFLOAT80U) iemFpuSoftF80ToIprt(PRTFLOAT80U pr80Dst, extFloat80_t const r80XSrc) 4572 { 4573 pr80Dst->s2.uSignAndExponent = r80XSrc.signExp; 4574 pr80Dst->s2.uMantissa = r80XSrc.signif; 4575 return pr80Dst; 4535 4576 } 4536 4577 … … 5265 5306 5266 5307 5308 /** 5309 * Helper for iemAImpl_fsqrt_r80, called both on normal and denormal numbers. 5310 */ 5267 5311 static uint16_t iemAImpl_fsqrt_r80_normal(PCRTFLOAT80U pr80Val, PRTFLOAT80U pr80Result, uint16_t fFcw, uint16_t fFsw) 5268 5312 { 5269 5313 Assert(!pr80Val->s.fSign); 5270 5271 softfloat_state_t SoftState = 5272 { 5273 softfloat_tininess_afterRounding, 5274 (fFcw & X86_FCW_RC_MASK) == X86_FCW_RC_NEAREST ? (uint8_t)softfloat_round_near_even 5275 : (fFcw & X86_FCW_RC_MASK) == X86_FCW_RC_UP ? (uint8_t)softfloat_round_max 5276 : (fFcw & X86_FCW_RC_MASK) == X86_FCW_RC_DOWN ? (uint8_t)softfloat_round_min 5277 : (uint8_t)softfloat_round_minMag, 5278 0, 5279 (fFcw & X86_FCW_PC_MASK) == X86_FCW_PC_53 ? (uint8_t)64 5280 : (fFcw & X86_FCW_PC_MASK) == X86_FCW_PC_24 ? (uint8_t)32 : (uint8_t)80 5281 }; 5282 5283 extFloat80_t r80XResult = extF80_sqrt(iemFpuSoftF80FromIprt(pr80Val), &SoftState); 5284 pr80Result->s2.uSignAndExponent = r80XResult.signExp; 5285 pr80Result->s2.uMantissa = r80XResult.signif; 5286 fFsw |= SoftState.exceptionFlags & X86_FSW_XCPT_MASK; 5287 fFsw |= (uint16_t)(SoftState.exceptionFlags & softfloat_flag_c1) << (2); 5288 if (!(fFsw & fFcw & X86_FSW_XCPT_MASK)) 5289 fFsw |= X86_FSW_ES | X86_FSW_B; 5290 5291 return fFsw; 5314 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_FCW(fFcw); 5315 iemFpuSoftF80ToIprt(pr80Result, extF80_sqrt(iemFpuSoftF80FromIprt(pr80Val), &SoftState)); 5316 return IEM_SOFTFLOAT_STATE_TO_FSW(fFsw, &SoftState, fFcw); 5292 5317 } 5293 5318
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