VirtualBox

Changeset 94617 in vbox for trunk/src/VBox


Ignore:
Timestamp:
Apr 15, 2022 1:02:18 PM (3 years ago)
Author:
vboxsync
Message:

VMM/*.cpp.h: Doxygen fixes.

Location:
trunk/src/VBox/VMM/VMMAll
Files:
4 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h

    r94051 r94617  
    8787     */
    8888    /** @todo Test the assertion in the intel manual that the CPU reads two
    89      *        bytes.  The question is how this works wrt to #PF and #GP on the
     89     *        bytes.  The question is how this works wrt to \#PF and \#GP on the
    9090     *        2nd byte when it's not required. */
    9191    uint16_t bmBytes = UINT16_MAX;
    … …  
    664664                return rcStrict;
    665665
    666             /** @todo Is the popf VME #GP(0) delivered after updating RSP+RIP
     666            /** @todo Is the popf VME \#GP(0) delivered after updating RSP+RIP
    667667             *        or before? */
    668668            if (    (   (u16Value & X86_EFL_IF)
    … …  
    768768 * @param   uNewPC          The new program counter (RIP) value (loaded from the
    769769 *                          operand).
    770  * @param   enmEffOpSize    The effective operand size.
    771770 */
    772771IEM_CIMPL_DEF_1(iemCImpl_call_16, uint16_t, uNewPC)
    … …  
    823822 * @param   uNewPC          The new program counter (RIP) value (loaded from the
    824823 *                          operand).
    825  * @param   enmEffOpSize    The effective operand size.
    826824 */
    827825IEM_CIMPL_DEF_1(iemCImpl_call_32, uint32_t, uNewPC)
    … …  
    878876 * @param   uNewPC          The new program counter (RIP) value (loaded from the
    879877 *                          operand).
    880  * @param   enmEffOpSize    The effective operand size.
    881878 */
    882879IEM_CIMPL_DEF_1(iemCImpl_call_64, uint64_t, uNewPC)
    … …  
    10681065     * must be 16-bit or 32-bit.
    10691066     */
    1070     /** @todo: effective operand size is probably irrelevant here, only the
    1071      *         call gate bitness matters??
     1067    /** @todo effective operand size is probably irrelevant here, only the
     1068     *        call gate bitness matters??
    10721069     */
    10731070    VBOXSTRICTRC    rcStrict;
    … …  
    11821179    if (enmBranch == IEMBRANCH_JUMP)
    11831180    {
    1184         /** @todo: This is very similar to regular far jumps; merge! */
     1181        /** @todo This is very similar to regular far jumps; merge! */
    11851182        /* Jumps are fairly simple... */
    11861183
    … …  
    13851382            }
    13861383
    1387             /** @todo: According to Intel, new stack is checked for enough space first,
    1388              *         then switched. According to AMD, the stack is switched first and
    1389              *         then pushes might fault!
    1390              *         NB: OS/2 Warp 3/4 actively relies on the fact that possible
    1391              *         incoming stack #PF happens before actual stack switch. AMD is
    1392              *         either lying or implicitly assumes that new state is committed
    1393              *         only if and when an instruction doesn't fault.
     1384            /** @todo According to Intel, new stack is checked for enough space first,
     1385             *        then switched. According to AMD, the stack is switched first and
     1386             *        then pushes might fault!
     1387             *        NB: OS/2 Warp 3/4 actively relies on the fact that possible
     1388             *        incoming stack \#PF happens before actual stack switch. AMD is
     1389             *        either lying or implicitly assumes that new state is committed
     1390             *        only if and when an instruction doesn't fault.
    13941391             */
    13951392
    1396             /** @todo: According to AMD, CS is loaded first, then SS.
    1397              *         According to Intel, it's the other way around!?
     1393            /** @todo According to AMD, CS is loaded first, then SS.
     1394             *        According to Intel, it's the other way around!?
    13981395             */
    13991396
    1400             /** @todo: Intel and AMD disagree on when exactly the CPL changes! */
     1397            /** @todo Intel and AMD disagree on when exactly the CPL changes! */
    14011398
    14021399            /* Set the accessed bit before committing new SS. */
    … …  
    15981595        {
    15991596            /* Same privilege. */
    1600             /** @todo: This is very similar to regular far calls; merge! */
     1597            /** @todo This is very similar to regular far calls; merge! */
    16011598
    16021599            /* Check stack first - may #SS(0). */
    … …  
    18931890        {
    18941891            Log(("jmpf %04x:%08RX64 -> out of bounds (%#x)\n", uSel, offSeg, cbLimit));
    1895             /** @todo: Intel says this is #GP(0)! */
     1892            /** @todo Intel says this is \#GP(0)! */
    18961893            return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
    18971894        }
    … …  
    20972094        {
    20982095            Log(("callf %04x:%08RX64 -> out of bounds (%#x)\n", uSel, offSeg, cbLimit));
    2099             /** @todo: Intel says this is #GP(0)! */
     2096            /** @todo Intel says this is \#GP(0)! */
    21002097            return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
    21012098        }
    … …  
    24282425                Log(("retf %04x:%08RX64 %04x:%08RX64 - out of bounds (%#x)-> #GP(CS).\n",
    24292426                     uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp, cbLimitCs));
    2430                 /** @todo: Intel says this is #GP(0)! */
     2427                /** @todo Intel says this is \#GP(0)! */
    24312428                return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
    24322429            }
    … …  
    25242521            {
    25252522                Log(("retf %04x:%08RX64 -> out of bounds (%#x)\n", uNewCs, uNewRip, cbLimitCs));
    2526                 /** @todo: Intel says this is #GP(0)! */
     2523                /** @todo Intel says this is \#GP(0)! */
    25272524                return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
    25282525            }
    … …  
    26612658 *
    26622659 * @param   enmEffOpSize    The effective operand size.
     2660 * @param   cbFrame         Frame size.
     2661 * @param   cParameters     Frame parameter count.
    26632662 */
    26642663IEM_CIMPL_DEF_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters)
    … …  
    33543353            Log(("iret %04x:%08x/%04x:%08x -> EIP is out of bounds (%#x) -> #GP(0)\n",
    33553354                 uNewCs, uNewEip, uNewSS, uNewESP, cbLimitCS));
    3356             /** @todo: Which is it, #GP(0) or #GP(sel)? */
     3355            /** @todo Which is it, \#GP(0) or \#GP(sel)? */
    33573356            return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
    33583357        }
    … …  
    34353434        {
    34363435            Log(("iret %04x:%08x - EIP is out of bounds (%#x) -> #GP(0)\n", uNewCs, uNewEip, cbLimitCS));
    3437             /** @todo: Which is it, #GP(0) or #GP(sel)? */
     3436            /** @todo Which is it, \#GP(0) or \#GP(sel)? */
    34383437            return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
    34393438        }
    … …  
    37093708            Log(("iret %04x:%016RX64/%04x:%016RX64 -> EIP is out of bounds (%#x) -> #GP(0)\n",
    37103709                 uNewCs, uNewRip, uNewSs, uNewRsp, cbLimitCS));
    3711             /** @todo: Which is it, #GP(0) or #GP(sel)? */
     3710            /** @todo Which is it, \#GP(0) or \#GP(sel)? */
    37123711            return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
    37133712        }
    … …  
    48624861 *
    48634862 * @returns VINF_SUCCESS.
    4864  * @param   pu16Dst         Pointer to the destination register.
     4863 * @param   pu64Dst         Pointer to the destination register.
    48654864 * @param   uSel            The selector to load details for.
    48664865 * @param   fIsLar          true = LAR, false = LSL.
    … …  
    49694968 * @returns VINF_SUCCESS.
    49704969 * @param   pu16Dst         Pointer to the destination register.
    4971  * @param   u16Sel          The selector to load details for.
     4970 * @param   uSel            The selector to load details for.
    49724971 * @param   fIsLar          true = LAR, false = LSL.
    49734972 */
    … …  
    53115310 * Implements sldt mem.
    53125311 *
    5313  * @param   iGReg           The general register to store the CRx value in.
    53145312 * @param   iEffSeg         The effective segment register to use with @a GCPtrMem.
    53155313 * @param   GCPtrEffDst     Where to store the 16-bit CR0 value.
    … …  
    54895487 * Implements str mem.
    54905488 *
    5491  * @param   iGReg           The general register to store the CRx value in.
    54925489 * @param   iEffSeg         The effective segment register to use with @a GCPtrMem.
    54935490 * @param   GCPtrEffDst     Where to store the 16-bit CR0 value.
    … …  
    56825679 * Implements smsw mem.
    56835680 *
    5684  * @param   iGReg           The general register to store the CR0 value in.
    56855681 * @param   iEffSeg         The effective segment register to use with @a GCPtrMem.
    56865682 * @param   GCPtrEffDst     Where to store the 16-bit CR0 value.
    … …  
    57395735 * @param   iCrReg          The CRx register to write (valid).
    57405736 * @param   uNewCrX         The new value.
    5741  * @param   enmAccessCrx    The instruction that caused the CrX load.
     5737 * @param   enmAccessCrX    The instruction that caused the CrX load.
    57425738 * @param   iGReg           The general register in case of a 'mov CRx,GReg'
    57435739 *                          instruction.
    … …  
    83808376 * Implements 'FXRSTOR'.
    83818377 *
     8378 * @param   iEffSeg         The effective segment register for @a GCPtrEff.
    83828379 * @param   GCPtrEff        The address of the image.
    83838380 * @param   enmEffOpSize    The operand size (only REX.W really matters).
    … …  
    88698866 * Implements 'STMXCSR'.
    88708867 *
     8868 * @param   iEffSeg         The effective segment register for @a GCPtrEff.
    88718869 * @param   GCPtrEff        The address of the image.
    88728870 */
    … …  
    89038901 * Implements 'VSTMXCSR'.
    89048902 *
     8903 * @param   iEffSeg         The effective segment register for @a GCPtrEff.
    89058904 * @param   GCPtrEff        The address of the image.
    89068905 */
    … …  
    89398938 * Implements 'LDMXCSR'.
    89408939 *
     8940 * @param   iEffSeg         The effective segment register for @a GCPtrEff.
    89418941 * @param   GCPtrEff        The address of the image.
    89428942 */
    … …  
    91239123 *
    91249124 * @param   enmEffOpSize    The operand size (only REX.W really matters).
    9125  * @param   iEffSeg         The effective segment register for @a GCPtrEff.
     9125 * @param   iEffSeg         The effective segment register for @a GCPtrEffDst.
    91269126 * @param   GCPtrEffDst     The address of the image.
    91279127 */
    … …  
    91499149 * Implements 'FNSAVE'.
    91509150 *
     9151 * @param   enmEffOpSize    The operand size.
     9152 * @param   iEffSeg         The effective segment register for @a GCPtrEffDst.
    91519153 * @param   GCPtrEffDst     The address of the image.
    9152  * @param   enmEffOpSize    The operand size.
    91539154 */
    91549155IEM_CIMPL_DEF_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
    … …  
    92019202 *
    92029203 * @param   enmEffOpSize    The operand size (only REX.W really matters).
    9203  * @param   iEffSeg         The effective segment register for @a GCPtrEff.
     9204 * @param   iEffSeg         The effective segment register for @a GCPtrEffSrc.
    92049205 * @param   GCPtrEffSrc     The address of the image.
    92059206 */
    … …  
    92279228 * Implements 'FRSTOR'.
    92289229 *
     9230 * @param   enmEffOpSize    The operand size.
     9231 * @param   iEffSeg         The effective segment register for @a GCPtrEffSrc.
    92299232 * @param   GCPtrEffSrc     The address of the image.
    9230  * @param   enmEffOpSize    The operand size.
    92319233 */
    92329234IEM_CIMPL_DEF_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc)
    … …  
    93379339 * Implements 'FCOMI', 'FCOMIP', 'FUCOMI', and 'FUCOMIP'.
    93389340 *
    9339  * @param   cToAdd              1 or 7.
     9341 * @param   iStReg          The other stack register.
     9342 * @param   pfnAImpl        The assembly comparison implementation.
     9343 * @param   fPop            Whether we should pop the stack when done or not.
    93409344 */
    93419345IEM_CIMPL_DEF_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop)

  • trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h

    r94538 r94617  
    10341034 * @optest      amd   / efl|=af  ax=0x0000 -> ax=0xfe0a efl&|=cf,po,af,nz,ng,nv
    10351035 * @optest      intel / efl|=af  ax=0x0100 -> ax=0xff0a efl&|=cf,po,af,nz,pl,nv
    1036  * @optest8     amd   / efl|=af  ax=0x0100 -> ax=0xff0a efl&|=cf,po,af,nz,ng,nv
     1036 * @optest      amd   / efl|=af  ax=0x0100 -> ax=0xff0a efl&|=cf,po,af,nz,ng,nv
    10371037 * @optest      intel / efl|=af  ax=0x000a -> ax=0xff04 efl&|=cf,pe,af,nz,pl,nv
    1038  * @optest10    amd   / efl|=af  ax=0x000a -> ax=0xff04 efl&|=cf,pe,af,nz,ng,nv
     1038 * @optest      amd   / efl|=af  ax=0x000a -> ax=0xff04 efl&|=cf,pe,af,nz,ng,nv
    10391039 * @optest            / efl|=af  ax=0x010a -> ax=0x0004 efl&|=cf,pe,af,nz,pl,nv
    10401040 * @optest            / efl|=af  ax=0x020a -> ax=0x0104 efl&|=cf,pe,af,nz,pl,nv
    … …  
    10481048 * @optest      amd   / efl&~=af ax=0xff09 -> ax=0xff09 efl&|=nc,po,na,nz,ng,nv
    10491049 * @optest      intel / efl&~=af ax=0x000b -> ax=0xff05 efl&|=cf,po,af,nz,pl,nv
    1050  * @optest22    amd   / efl&~=af ax=0x000b -> ax=0xff05 efl&|=cf,po,af,nz,ng,nv
     1050 * @optest      amd   / efl&~=af ax=0x000b -> ax=0xff05 efl&|=cf,po,af,nz,ng,nv
    10511051 * @optest      intel / efl&~=af ax=0x000c -> ax=0xff06 efl&|=cf,po,af,nz,pl,nv
    1052  * @optest24    amd   / efl&~=af ax=0x000c -> ax=0xff06 efl&|=cf,po,af,nz,ng,nv
     1052 * @optest      amd   / efl&~=af ax=0x000c -> ax=0xff06 efl&|=cf,po,af,nz,ng,nv
    10531053 * @optest      intel / efl&~=af ax=0x000d -> ax=0xff07 efl&|=cf,pe,af,nz,pl,nv
    1054  * @optest26    amd   / efl&~=af ax=0x000d -> ax=0xff07 efl&|=cf,pe,af,nz,ng,nv
     1054 * @optest      amd   / efl&~=af ax=0x000d -> ax=0xff07 efl&|=cf,pe,af,nz,ng,nv
    10551055 * @optest      intel / efl&~=af ax=0x000e -> ax=0xff08 efl&|=cf,pe,af,nz,pl,nv
    1056  * @optest28    amd   / efl&~=af ax=0x000e -> ax=0xff08 efl&|=cf,pe,af,nz,ng,nv
     1056 * @optest      amd   / efl&~=af ax=0x000e -> ax=0xff08 efl&|=cf,pe,af,nz,ng,nv
    10571057 * @optest      intel / efl&~=af ax=0x000f -> ax=0xff09 efl&|=cf,po,af,nz,pl,nv
    1058  * @optest30    amd   / efl&~=af ax=0x000f -> ax=0xff09 efl&|=cf,po,af,nz,ng,nv
    1059  * @optest31    intel / efl&~=af ax=0x00fa -> ax=0xff04 efl&|=cf,pe,af,nz,pl,nv
    1060  * @optest32    amd   / efl&~=af ax=0x00fa -> ax=0xff04 efl&|=cf,pe,af,nz,ng,nv
    1061  * @optest33    intel / efl&~=af ax=0xfffa -> ax=0xfe04 efl&|=cf,pe,af,nz,pl,nv
    1062  * @optest34    amd   / efl&~=af ax=0xfffa -> ax=0xfe04 efl&|=cf,pe,af,nz,ng,nv
     1058 * @optest      amd   / efl&~=af ax=0x000f -> ax=0xff09 efl&|=cf,po,af,nz,ng,nv
     1059 * @optest      intel / efl&~=af ax=0x00fa -> ax=0xff04 efl&|=cf,pe,af,nz,pl,nv
     1060 * @optest      amd   / efl&~=af ax=0x00fa -> ax=0xff04 efl&|=cf,pe,af,nz,ng,nv
     1061 * @optest      intel / efl&~=af ax=0xfffa -> ax=0xfe04 efl&|=cf,pe,af,nz,pl,nv
     1062 * @optest      amd   / efl&~=af ax=0xfffa -> ax=0xfe04 efl&|=cf,pe,af,nz,ng,nv
    10631063 */
    10641064FNIEMOP_DEF(iemOp_aas)
    … …  
    70817081 * result in ST0.
    70827082 *
     7083 * @param   bRm         Mod R/M byte.
    70837084 * @param   pfnAImpl    Pointer to the instruction implementation (assembly).
    70847085 */
    … …  
    71137114 * flags.
    71147115 *
     7116 * @param   bRm         Mod R/M byte.
    71157117 * @param   pfnAImpl    Pointer to the instruction implementation (assembly).
    71167118 */
    … …  
    71457147 * flags, and popping when done.
    71467148 *
     7149 * @param   bRm         Mod R/M byte.
    71477150 * @param   pfnAImpl    Pointer to the instruction implementation (assembly).
    71487151 */
    … …  
    72417244 * the result in ST0.
    72427245 *
     7246 * @param   bRm         Mod R/M byte.
    72437247 * @param   pfnAImpl    Pointer to the instruction implementation (assembly).
    72447248 */
    … …  
    79407944 * in STn, and popping the stack unless IE, DE or ZE was raised.
    79417945 *
     7946 * @param   bRm         Mod R/M byte.
    79427947 * @param   pfnAImpl    Pointer to the instruction implementation (assembly).
    79437948 */
    … …  
    83938398 * the result in ST0.
    83948399 *
     8400 * @param   bRm         Mod R/M byte.
    83958401 * @param   pfnAImpl    Pointer to the instruction implementation (assembly).
    83968402 */
    … …  
    90619067 * result in STn unless IE, DE or ZE was raised.
    90629068 *
     9069 * @param   bRm         Mod R/M byte.
    90639070 * @param   pfnAImpl    Pointer to the instruction implementation (assembly).
    90649071 */
    … …  
    91429149 * memory operand, and storing the result in ST0.
    91439150 *
    9144  * @param   pfnAImpl    Pointer to the instruction implementation (assembly).
     9151 * @param   bRm         Mod R/M byte.
     9152 * @param   pfnImpl     Pointer to the instruction implementation (assembly).
    91459153 */
    91469154FNIEMOP_DEF_2(iemOpHlpFpu_ST0_m64r, uint8_t, bRm, PFNIEMAIMPLFPUR64, pfnImpl)
    … …  
    97029710 * the result in ST0.
    97039711 *
     9712 * @param   bRm         Mod R/M byte.
    97049713 * @param   pfnAImpl    Pointer to the instruction implementation (assembly).
    97059714 */
    … …  
    1038010389    IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
    1038110390
    10382     /** @todo Check out the #GP case if EIP < CS.Base or EIP > CS.Limit when
     10391    /** @todo Check out the \#GP case if EIP < CS.Base or EIP > CS.Limit when
    1038310392     * using the 32-bit operand size override.  How can that be restarted?  See
    1038410393     * weird pseudo code in intel manual. */
    … …  
    1070310712{
    1070410713    IEMOP_MNEMONIC(int1, "int1"); /* icebp */
    10705     /** @todo Does not generate #UD on 286, or so they say...  Was allegedly a
     10714    /** @todo Does not generate \#UD on 286, or so they say...  Was allegedly a
    1070610715     * prefix byte on 8086 and/or/maybe 80286 without meaning according to the 286
    1070710716     * LOADALL memo.  Needs some testing. */

  • trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap2.cpp.h

    r93115 r94617  
    560560
    561561/**
    562  * Group 17 jump table for the VEX.F3 variant..
     562 * Group 17 jump table for the VEX.F3 variant.
    563563 */
    564564IEM_STATIC const PFNIEMOPRM g_apfnVexGroup17_f3[] =

  • trunk/src/VBox/VMM/VMMAll/NEMAllNativeTemplate-win.cpp.h

    r94610 r94617  
    22212221                                        pExit->VpException.InstructionByteCount))
    22222222            {
    2223 #if 1 /** @todo Need to emulate instruction or we get a triple fault when trying to inject the #GP... */
     2223#if 1 /** @todo Need to emulate instruction or we get a triple fault when trying to inject the \#GP... */
    22242224                rcStrict = IEMExecOneWithPrefetchedByPC(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), pExit->VpContext.Rip,
    22252225                                                        pExit->VpException.InstructionBytes,
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