Changeset 94712 in vbox

Timestamp:

Apr 26, 2022 11:49:13 PM (3 years ago)

Author:

vboxsync

Message:

VMM/IEM: Some TLB compile and doc tweaks. bugref:9898

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/IEMAllCImplVmxInstr.cpp.h (modified) (1 diff)
• include/IEMInternal.h (modified) (5 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h

@@ -25 +25 @@
  * relative offsets.
  */
-# ifdef IEM_WITH_CODE_TLB
-#  define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm)         do { } while (0)
-#  define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib)               do { } while (0)
-#  define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp)         do { } while (0)
-#  define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp)   do { } while (0)
-#  define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp)         do { } while (0)
-#  define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp)   do { } while (0)
-#  define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp)  do { } while (0)
-#  define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp)   do { } while (0)
-#  error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
+# ifdef IEM_WITH_CODE_TLB /** @todo IEM TLB */
+#  define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm)         do { a_bModRm  = 0; RT_NOREF(a_offModRm); } while (0)
+#  define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib)               do { a_bSib    = 0; RT_NOREF(a_offSib);  } while (0)
+#  define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp)         do { a_u16Disp = 0; RT_NOREF(a_offDisp); } while (0)
+#  define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp)   do { a_u16Disp = 0; RT_NOREF(a_offDisp); } while (0)
+#  define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp)         do { a_u32Disp = 0; RT_NOREF(a_offDisp); } while (0)
+#  define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp)   do { a_u32Disp = 0; RT_NOREF(a_offDisp); } while (0)
+#  define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp)  do { a_u64Disp = 0; RT_NOREF(a_offDisp); } while (0)
+#  define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp)   do { a_u64Disp = 0; RT_NOREF(a_offDisp); } while (0)
+#  if 1
+#   error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
+#  endif
 # else  /* !IEM_WITH_CODE_TLB */
 #  define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \

trunk/src/VBox/VMM/include/IEMInternal.h

@@ -75 +75 @@
 
 
-//#define IEM_WITH_CODE_TLB// - work in progress
+//#define IEM_WITH_CODE_TLB // - work in progress
+//#define IEM_WITH_DATA_TLB // - incomplete in progress
 
 
@@ -212 +213 @@
 
         ; Check access.
-        movsx   rax, ACCESS_FLAGS | MAPPING_R3_NOT_VALID | 0xffffff00
+        mov     rax, ACCESS_FLAGS | MAPPING_R3_NOT_VALID | 0xffffff00
         and     rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
         cmp     rax, [uTlbPhysRev]
@@ -239 +240 @@
 {
     /** The TLB entry tag.
-     * Bits 35 thru 0 are made up of the virtual address shifted right 12 bits.
+     * Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
+     * is ASSUMING a virtual address width of 48 bits.
+     *
      * Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
      *
@@ -248 +251 @@
      * @note    Try use SHRD instruction?  After seeing
      *          https://gmplib.org/~tege/x86-timing.pdf, maybe not.
+     *
+     * @todo    This will need to be reorganized for 57-bit wide virtual address and
+     *          PCID (currently 12 bits) and ASID (currently 6 bits) support.  We'll
+     *          have to move the TLB entry versioning entirely to the
+     *          fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
+     *          19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
+     *          consumed by PCID and ASID (12 + 6 = 18).
      */
     uint64_t                uTag;
@@ -290 +300 @@
 #define IEMTLBE_F_PG_NO_WRITE       RT_BIT_64(3) /**< Phys page:   Not writable (access handler, ROM, whatever). */
 #define IEMTLBE_F_PG_NO_READ        RT_BIT_64(4) /**< Phys page:   Not readable (MMIO / access handler, ROM) */
-#define IEMTLBE_F_PT_NO_DIRTY       RT_BIT_64(5) /**< Page tables: Not dirty (needs to be made dirty on write). */
-#define IEMTLBE_F_NO_MAPPINGR3      RT_BIT_64(6) /**< TLB entry:   The IEMTLBENTRY::pMappingR3 member is invalid. */
+#define IEMTLBE_F_PT_NO_DIRTY       RT_BIT_64(6) /**< Page tables: Not dirty (needs to be made dirty on write). */
+#define IEMTLBE_F_NO_MAPPINGR3      RT_BIT_64(7) /**< TLB entry:   The IEMTLBENTRY::pMappingR3 member is invalid. */
 #define IEMTLBE_F_PHYS_REV          UINT64_C(0xffffffffffffff00) /**< Physical revision mask. */
 /** @} */