Changeset 9484 in vbox

Timestamp:

Jun 6, 2008 2:02:24 PM (17 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

31744

Message:

Save & restore CSTAR, STAR, SFMASK & KERNEL_GSBASE MSRs (VT-x)

Location:

trunk/src/VBox/VMM/VMMR0

Files:

• HWACCMR0A.asm (modified) (11 diffs)
• HWVMXR0.cpp (modified) (1 diff)

trunk/src/VBox/VMM/VMMR0/HWACCMR0A.asm

@@ -65 +65 @@
 
 %ifdef RT_ARCH_AMD64
+  ; Save a host and load the corresponding guest MSR (trashes rdx & rcx)
+  %macro LOADGUESTMSR 2
+    mov     rcx, %1
+    rdmsr
+    push    rdx
+    push    rax
+    xor     rdx, rdx
+    mov     rax, qword [xSI + %2]
+    wrmsr
+  %endmacro
+
+  ; Save a guest and load the corresponding host MSR (trashes rdx & rcx)
+  %macro LOADHOSTMSR 2
+    mov     rcx, %1
+    rdmsr
+    mov     qword [xSI + %2], rax
+    pop     rax
+    pop     rdx
+    wrmsr
+  %endmacro
+
  %ifdef ASM_CALL64_GCC
   %macro MYPUSHAD 0
@@ -102 +123 @@
  %endif
 
+; trashes, rax, rdx & rcx
  %macro MYPUSHSEGS 2
     mov     %2, es
@@ -109 +131 @@
 
     ; Special case for FS; Windows and Linux either don't use it or restore it when leaving kernel mode, Solaris OTOH doesn't and we must save it.
-    push    rcx
     mov     ecx, MSR_K8_FS_BASE
     rdmsr
-    pop     rcx
     push    rdx
     push    rax
@@ -118 +138 @@
 
     ; Special case for GS; OSes typically use swapgs to reset the hidden base register for GS on entry into the kernel. The same happens on exit
-    push    rcx
     mov     ecx, MSR_K8_GS_BASE
     rdmsr
-    pop     rcx
     push    rdx
     push    rax
@@ -127 +145 @@
  %endmacro
 
+; trashes, rax, rdx & rcx
  %macro MYPOPSEGS 2
     ; Note: do not step through this code with a debugger!
@@ -132 +151 @@
     pop     rax
     pop     rdx
-    push    rcx
     mov     ecx, MSR_K8_GS_BASE
     wrmsr
-    pop     rcx
 
     pop     fs
     pop     rax
     pop     rdx
-    push    rcx
     mov     ecx, MSR_K8_FS_BASE
     wrmsr
-    pop     rcx
     ; Now it's safe to step again
 
@@ -233 +248 @@
 
     ;/* Save segment registers */
-    ; Note: MYPUSHSEGS trashes rdx (among others), so we moved it here (msvc amd64 case)
+    ; Note: MYPUSHSEGS trashes rdx & rcx, so we moved it here (msvc amd64 case)
     MYPUSHSEGS xAX, ax
 
@@ -434 +449 @@
 
     ;/* Save segment registers */
-    ; Note: MYPUSHSEGS trashes rdx (among others), so we moved it here (msvc amd64 case)
+    ; Note: MYPUSHSEGS trashes rdx & rcx, so we moved it here (msvc amd64 case)
     MYPUSHSEGS xAX, ax
+
+    ; Save the host LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs and restore the guest MSRs
+    ; @todo use the automatic load feature for MSRs
+    LOADGUESTMSR MSR_K8_LSTAR, CPUMCTX.msrLSTAR
+    LOADGUESTMSR MSR_K8_CSTAR, CPUMCTX.msrCSTAR
+    LOADGUESTMSR MSR_K8_SF_MASK, CPUMCTX.msrSFMASK
+    LOADGUESTMSR MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
 
     ; Save the pCtx pointer
@@ -544 +566 @@
     add     xSP, xS      ; pCtx
 
+    ; Save the guest LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs and restore the host MSRs
+    ; @todo use the automatic load feature for MSRs
+    LOADHOSTMSR MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
+    LOADHOSTMSR MSR_K8_SF_MASK, CPUMCTX.msrSFMASK
+    LOADHOSTMSR MSR_K8_CSTAR, CPUMCTX.msrCSTAR
+    LOADHOSTMSR MSR_K8_LSTAR, CPUMCTX.msrLSTAR
+
     ; Restore segment registers
     MYPOPSEGS xAX, ax
@@ -569 +598 @@
 
     add     xSP, xS     ; pCtx
+
+    ; Save the guest LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs and restore the host MSRs
+    ; @todo use the automatic load feature for MSRs
+    LOADHOSTMSR MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
+    LOADHOSTMSR MSR_K8_SF_MASK, CPUMCTX.msrSFMASK
+    LOADHOSTMSR MSR_K8_CSTAR, CPUMCTX.msrCSTAR
+    LOADHOSTMSR MSR_K8_LSTAR, CPUMCTX.msrLSTAR
 
     ; Restore segment registers
@@ -589 +625 @@
 
     add     xSP, xS     ; pCtx
+
+    ; Save the guest LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs and restore the host MSRs
+    ; @todo use the automatic load feature for MSRs
+    LOADHOSTMSR MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
+    LOADHOSTMSR MSR_K8_SF_MASK, CPUMCTX.msrSFMASK
+    LOADHOSTMSR MSR_K8_CSTAR, CPUMCTX.msrCSTAR
+    LOADHOSTMSR MSR_K8_LSTAR, CPUMCTX.msrLSTAR
 
     ; Restore segment registers

trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

@@ -951 +951 @@
      */
     val = (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF);
-
-    /* Mask away the bits that the CPU doesn't support */
-    /** @todo make sure they don't conflict with the above requirements. */
-    val &= (pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL);
-    /* else Must be zero when AMD64 is not available. */
-    rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
-    AssertRC(rc);
-
     /* 64 bits guest mode? */
     if (pCtx->msrEFER & MSR_K6_EFER_LMA)
-    {
         val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
+    /* else Must be zero when AMD64 is not available. */
+
+    /* Mask away the bits that the CPU doesn't support */
+    val &= (pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL);
+    rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
+    AssertRC(rc);
+
+    /* 64 bits guest mode? */
+    if (pCtx->msrEFER & MSR_K6_EFER_LMA)
+    {
 #ifndef VBOX_WITH_64_BITS_GUESTS
         return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;