Changeset 95296 in vbox
- Timestamp:
- Jun 15, 2022 10:06:20 PM (2 years ago)
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 4 edited
-
bs3-cpu-instr-2-template.c (modified) (4 diffs)
-
bs3-cpu-instr-2-template.mac (modified) (1 diff)
-
bs3-cpu-instr-2.c (modified) (2 diffs)
-
bs3kit/bs3kit.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2-template.c
r93115 r95296 33 33 34 34 35 36 37 35 /********************************************************************************************************************************* 38 36 * Structures and Typedefs * … … 62 60 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_div_xBX_ud2); 63 61 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_idiv_xBX_ud2); 62 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_rorx_RBX_RDX_2_icebp); 63 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_rorx_EBX_EDX_2_icebp); 64 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_rorx_EBX_EDX_2_icebp_L1); 65 # if ARCH_BITS == 64 66 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_rorx_EBX_EDX_2_icebp_X1); 67 # endif 68 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V1); 69 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V15); 64 70 # if ARCH_BITS == 64 65 71 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_cmpxchg16b_rdi_ud2); … … 597 603 598 604 605 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_rorx)(uint8_t bMode) 606 { 607 static const struct 608 { 609 FPFNBS3FAR pfnWorker; 610 bool fOkay; 611 RTCCUINTXREG uIn; 612 RTCCUINTXREG uOut; 613 } s_aTests[] = 614 { 615 { BS3_CMN_NM(bs3CpuInstr2_rorx_RBX_RDX_2_icebp), true, // #0 616 0, /* -> */ 0 }, 617 { BS3_CMN_NM(bs3CpuInstr2_rorx_RBX_RDX_2_icebp), true, // #1 618 ~(RTCCUINTXREG)2, /* -> */ ~(RTCCUINTXREG)0 >> 1 }, 619 { BS3_CMN_NM(bs3CpuInstr2_rorx_EBX_EDX_2_icebp), true, // #2 620 0, /* -> */ 0 }, 621 { BS3_CMN_NM(bs3CpuInstr2_rorx_EBX_EDX_2_icebp), true, // #3 622 ~(RTCCUINTXREG)2, /* -> */ (RTCCUINTXREG)(~(uint32_t)0 >> 1) }, 623 624 { BS3_CMN_NM(bs3CpuInstr2_rorx_EBX_EDX_2_icebp_L1), false, // #4 625 RTCCUINTXREG_MAX, /* -> */ 0 }, 626 { BS3_CMN_NM(bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V1), false, // #5 627 RTCCUINTXREG_MAX, /* -> */ 0 }, 628 { BS3_CMN_NM(bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V15), false, // #6 629 RTCCUINTXREG_MAX, /* -> */ 0 }, 630 # if ARCH_BITS == 64 /* The VEX.X=0 encoding mean LES instruction in 32-bit and 16-bit mode. */ 631 { BS3_CMN_NM(bs3CpuInstr2_rorx_EBX_EDX_2_icebp_X1), true, // #7 632 UINT32_C(0xf1e2d3c5), /* -> */ (RTCCUINTXREG)UINT32_C(0x7c78b4f1) }, 633 # endif 634 }; 635 636 BS3REGCTX Ctx; 637 BS3TRAPFRAME TrapFrame; 638 unsigned i, j; 639 640 /* Ensure the structures are allocated before we sample the stack pointer. */ 641 Bs3MemSet(&Ctx, 0, sizeof(Ctx)); 642 Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); 643 644 /* 645 * Create test context. 646 */ 647 Bs3RegCtxSaveEx(&Ctx, bMode, 512); 648 649 /* 650 * Do the tests twice, first with all flags set, then once again with 651 * flags cleared. The flags are not supposed to be touched at all. 652 */ 653 Ctx.rflags.u16 |= X86_EFL_STATUS_BITS; 654 for (j = 0; j < 2; j++) 655 { 656 for (i = 0; i < RT_ELEMENTS(s_aTests); i++) 657 { 658 bool const fOkay = !BS3_MODE_IS_RM_OR_V86(bMode) && s_aTests[i].fOkay; 659 uint64_t uExpectRbx; 660 uint64_t uExpectRip; 661 Ctx.rbx.uCcXReg = RTCCUINTXREG_MAX * 1019; 662 Ctx.rdx.uCcXReg = s_aTests[i].uIn; 663 Bs3RegCtxSetRipCsFromCurPtr(&Ctx, s_aTests[i].pfnWorker); 664 uExpectRbx = fOkay ? s_aTests[i].uOut : Ctx.rbx.u; 665 uExpectRip = Ctx.rip.u + (fOkay ? 6 : 0); 666 Bs3TrapSetJmpAndRestore(&Ctx, &TrapFrame); 667 668 if ( TrapFrame.bXcpt != X86_XCPT_UD 669 || TrapFrame.Ctx.rip.u != uExpectRip 670 || TrapFrame.Ctx.rdx.u != Ctx.rdx.u 671 || TrapFrame.Ctx.rbx.u != uExpectRbx 672 /* check that nothing else really changed: */ 673 || (TrapFrame.Ctx.rflags.u16 & X86_EFL_STATUS_BITS) != (Ctx.rflags.u16 & X86_EFL_STATUS_BITS) 674 || TrapFrame.Ctx.rax.u != Ctx.rax.u 675 || TrapFrame.Ctx.rcx.u != Ctx.rcx.u 676 || TrapFrame.Ctx.rsp.u != Ctx.rsp.u 677 || TrapFrame.Ctx.rbp.u != Ctx.rbp.u 678 || TrapFrame.Ctx.rsi.u != Ctx.rsi.u 679 || TrapFrame.Ctx.rdi.u != Ctx.rdi.u 680 ) 681 { 682 Bs3TestFailedF("test #%i failed: input %#" RTCCUINTXREG_XFMT, i, s_aTests[i].uIn); 683 if (TrapFrame.bXcpt != X86_XCPT_UD) 684 Bs3TestFailedF("Expected bXcpt = %#x, got %#x", X86_XCPT_UD, TrapFrame.bXcpt); 685 if (TrapFrame.Ctx.rip.u != uExpectRip) 686 Bs3TestFailedF("Expected RIP = %#06RX16, got %#06RX16 (src)", uExpectRip, TrapFrame.Ctx.rip.u); 687 if (TrapFrame.Ctx.rdx.u != Ctx.rdx.u) 688 Bs3TestFailedF("Expected RDX = %#06RX16, got %#06RX16 (src)", Ctx.rdx.u, TrapFrame.Ctx.rdx.u); 689 if (TrapFrame.Ctx.rbx.u != uExpectRbx) 690 Bs3TestFailedF("Expected RBX = %#06RX16, got %#06RX16 (dst)", uExpectRbx, TrapFrame.Ctx.rbx.u); 691 692 if ((TrapFrame.Ctx.rflags.u16 & X86_EFL_STATUS_BITS) != (Ctx.rflags.u16 & X86_EFL_STATUS_BITS)) 693 Bs3TestFailedF("Expected EFLAGS = %#06RX16, got %#06RX16", 694 Ctx.rflags.u16 & X86_EFL_STATUS_BITS, TrapFrame.Ctx.rflags.u16 & X86_EFL_STATUS_BITS); 695 if (TrapFrame.Ctx.rax.u != Ctx.rax.u) 696 Bs3TestFailedF("Expected RAX = %#06RX16, got %#06RX16", Ctx.rax.u, TrapFrame.Ctx.rax.u); 697 if (TrapFrame.Ctx.rcx.u != Ctx.rcx.u) 698 Bs3TestFailedF("Expected RCX = %#06RX16, got %#06RX16", Ctx.rcx.u, TrapFrame.Ctx.rcx.u); 699 if (TrapFrame.Ctx.rsp.u != Ctx.rsp.u) 700 Bs3TestFailedF("Expected RSP = %#06RX16, got %#06RX16", Ctx.rsp.u, TrapFrame.Ctx.rsp.u); 701 if (TrapFrame.Ctx.rbp.u != Ctx.rbp.u) 702 Bs3TestFailedF("Expected RBP = %#06RX16, got %#06RX16", Ctx.rbp.u, TrapFrame.Ctx.rbp.u); 703 if (TrapFrame.Ctx.rsi.u != Ctx.rsi.u) 704 Bs3TestFailedF("Expected RSI = %#06RX16, got %#06RX16", Ctx.rsi.u, TrapFrame.Ctx.rsi.u); 705 if (TrapFrame.Ctx.rdi.u != Ctx.rdi.u) 706 Bs3TestFailedF("Expected RDI = %#06RX16, got %#06RX16", Ctx.rdi.u, TrapFrame.Ctx.rdi.u); 707 } 708 } 709 Ctx.rflags.u16 &= ~X86_EFL_STATUS_BITS; 710 } 711 712 return 0; 713 } 714 715 599 716 # if ARCH_BITS == 64 717 600 718 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_cmpxchg16b)(uint8_t bMode) 601 719 { … … 1020 1138 return 0; 1021 1139 } 1140 1022 1141 # endif /* ARCH_BITS == 64 */ 1023 1024 1142 1025 1143 #endif /* BS3_INSTANTIATING_CMN */ -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2-template.mac
r93115 r95296 83 83 BS3_PROC_END_CMN bs3CpuInstr2_idiv_xBX_ud2 84 84 85 85 ; 86 ; RORX - VEX instruction with a couple of questions about non-standard encodings. 87 ; 88 %define icebp ud2 89 BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp, BS3_PBC_NEAR 90 %if TMPL_BITS != 16 91 rorx ebx, edx, 2 92 %else 93 db 0C4h,0E3h,07Bh,0F0h,0DAh,002h ; wrong nasm mode, whatever 94 %endif 95 .again: 96 icebp 97 jmp .again 98 BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp 99 100 BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_RBX_RDX_2_icebp, BS3_PBC_NEAR 101 %if TMPL_BITS == 64 102 rorx rbx, rdx, 2 103 %else 104 db 0C4h,0E3h,0FBh,0F0h,0DAh,002h ; 32-bit ignores VEX.W=1 (10980xe) 105 %endif 106 .again: 107 icebp 108 jmp .again 109 BS3_PROC_END_CMN bs3CpuInstr2_rorx_RBX_RDX_2_icebp 110 111 BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_L1, BS3_PBC_NEAR 112 db 0C4h, 0E3h, 07Bh | 4h, 0F0h, 0DAh, 002h ; VEX.L=1 should #UD according to the docs 113 .again: 114 icebp 115 jmp .again 116 BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_L1 117 118 BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V1, BS3_PBC_NEAR 119 db 0C4h, 0E3h, 003h | ~(1 << 3), 0F0h, 0DAh, 002h ; VEX.VVVV=1 - behaviour is undocumented - 10980xe #UD 120 .again: 121 icebp 122 jmp .again 123 BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V1 124 125 BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V15, BS3_PBC_NEAR 126 db 0C4h, 0E3h, 003h | ~(15 << 3), 0F0h, 0DAh, 002h ; VEX.VVVV=15 - behaviour is not documented - 10980xe #UD 127 .again: 128 icebp 129 jmp .again 130 BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_V15 131 132 %if TMPL_BITS == 64 133 BS3_PROC_BEGIN_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_X1, BS3_PBC_NEAR 134 db 0C4h, 0E3h & ~40h, 07Bh, 0F0h, 0DAh, 002h ; VEX.X=0 - behaviour is not documented - ignored by 10980xe 135 .again: 136 icebp 137 jmp .again 138 BS3_PROC_END_CMN bs3CpuInstr2_rorx_EBX_EDX_2_icebp_X1 139 %endif 140 141 142 ; 143 ; 144 ; 86 145 %if TMPL_BITS == 64 87 146 BS3_PROC_BEGIN_CMN bs3CpuInstr2_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2.c
r93115 r95296 39 39 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_div); 40 40 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_idiv); 41 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_rorx); 41 42 BS3TESTMODE_PROTOTYPES_CMN_64(bs3CpuInstr2_cmpxchg16b); 42 43 BS3TESTMODE_PROTOTYPES_CMN_64(bs3CpuInstr2_wrfsbase); … … 55 56 BS3TESTMODEENTRY_CMN("div", bs3CpuInstr2_div), 56 57 BS3TESTMODEENTRY_CMN("idiv", bs3CpuInstr2_idiv), 58 BS3TESTMODEENTRY_CMN("rorx", bs3CpuInstr2_rorx), 57 59 BS3TESTMODEENTRY_CMN_64("cmpxchg16b", bs3CpuInstr2_cmpxchg16b), 58 60 BS3TESTMODEENTRY_CMN_64("wrfsbase", bs3CpuInstr2_wrfsbase), -
trunk/src/VBox/ValidationKit/bootsectors/bs3kit/bs3kit.h
r93115 r95296 2556 2556 /** 32-bit view. */ 2557 2557 uint32_t au32[2]; 2558 /** Unsigned integer, depending on compiler context. 2559 * This generally follows ARCH_BITS. */ 2560 RTCCUINTREG uCcReg; 2561 /** Extended unsigned integer, depending on compiler context. 2562 * This is 32-bit in 16-bit and 32-bit compiler contexts, and 64-bit in 2563 * 64-bit. */ 2564 RTCCUINTXREG uCcXReg; 2558 2565 } BS3REG; 2559 2566 /** Pointer to an integer register. */
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