Changeset 95305 in vbox for trunk/src/VBox/ValidationKit
- Timestamp:
- Jun 19, 2022 3:23:31 PM (3 years ago)
- svn:sync-xref-src-repo-rev:
- 151895
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 3 edited
-
bs3-cpu-instr-2-template.c (modified) (3 diffs)
-
bs3-cpu-instr-2-template.mac (modified) (1 diff)
-
bs3-cpu-instr-2.c (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2-template.c
r95303 r95305 56 56 #ifdef BS3_INSTANTIATING_CMN 57 57 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_mul_xBX_ud2); 58 58 59 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_imul_xBX_ud2); 59 60 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_imul_xCX_xBX_ud2); 61 60 62 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_div_xBX_ud2); 61 63 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_idiv_xBX_ud2); 64 62 65 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_rorx_RBX_RDX_2_icebp); 63 66 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_rorx_EBX_EDX_2_icebp); … … 70 73 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_rorx_RBX_DSxDI_68_icebp); 71 74 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_rorx_EBX_DSxDI_36_icebp); 75 76 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_andn_RAX_RCX_RBX_icebp); 77 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_andn_RAX_RCX_FSxBX_icebp); 78 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_andn_EAX_ECX_EBX_icebp); 79 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_andn_EAX_ECX_FSxBX_icebp); 80 81 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_bextr_RAX_RBX_RCX_icebp); 82 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_bextr_RAX_FSxBX_RCX_icebp); 83 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_bextr_EAX_EBX_ECX_icebp); 84 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_bextr_EAX_FSxBX_ECX_icebp); 85 86 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_shlx_RAX_RBX_RCX_icebp); 87 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_shlx_RAX_FSxBX_RCX_icebp); 88 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_shlx_EAX_EBX_ECX_icebp); 89 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_shlx_EAX_FSxBX_ECX_icebp); 90 91 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_sarx_RAX_RBX_RCX_icebp); 92 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_sarx_RAX_FSxBX_RCX_icebp); 93 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_sarx_EAX_EBX_ECX_icebp); 94 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_sarx_EAX_FSxBX_ECX_icebp); 95 96 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_shrx_RAX_RBX_RCX_icebp); 97 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_shrx_RAX_FSxBX_RCX_icebp); 98 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_shrx_EAX_EBX_ECX_icebp); 99 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_shrx_EAX_FSxBX_ECX_icebp); 100 72 101 # if ARCH_BITS == 64 73 102 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_cmpxchg16b_rdi_ud2); … … 746 775 747 776 return 0; 777 } 778 779 780 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_andn)(uint8_t bMode) 781 { 782 #define ANDN_CHECK_EFLAGS (uint16_t)(X86_EFL_CF | X86_EFL_ZF | X86_EFL_OF | X86_EFL_SF) 783 #define ANDN_IGNORE_EFLAGS (uint16_t)(X86_EFL_AF | X86_EFL_PF) /* undefined, ignoring for now */ 784 static const struct 785 { 786 FPFNBS3FAR pfnWorker; 787 bool fMemSrc; 788 uint8_t cbInstr; 789 RTCCUINTXREG uSrc1; 790 RTCCUINTXREG uSrc2; 791 RTCCUINTXREG uOut; 792 uint16_t fEFlags; 793 } s_aTests[] = 794 { 795 /* 64 bits register width (32 bits in 32- and 16-bit modes): */ 796 { BS3_CMN_NM(bs3CpuInstr2_andn_RAX_RCX_RBX_icebp), false, 5, // #0 797 0, 0, /* -> */ 0, X86_EFL_ZF }, 798 { BS3_CMN_NM(bs3CpuInstr2_andn_RAX_RCX_RBX_icebp), false, 5, // #1 799 2, ~(RTCCUINTXREG)3, /* -> */ ~(RTCCUINTXREG)3, X86_EFL_SF }, 800 { BS3_CMN_NM(bs3CpuInstr2_andn_RAX_RCX_FSxBX_icebp), true, 6, // #2 801 0, 0, /* -> */ 0, X86_EFL_ZF }, 802 { BS3_CMN_NM(bs3CpuInstr2_andn_RAX_RCX_FSxBX_icebp), true, 6, // #3 803 2, ~(RTCCUINTXREG)3, /* -> */ ~(RTCCUINTXREG)3, X86_EFL_SF }, 804 805 /* 32-bit register width */ 806 { BS3_CMN_NM(bs3CpuInstr2_andn_EAX_ECX_EBX_icebp), false, 5, // #4 807 0, 0, /* -> */ 0, X86_EFL_ZF }, 808 { BS3_CMN_NM(bs3CpuInstr2_andn_EAX_ECX_EBX_icebp), false, 5, // #5 809 2, ~(RTCCUINTXREG)7, /* -> */ ~(uint32_t)7, X86_EFL_SF }, 810 { BS3_CMN_NM(bs3CpuInstr2_andn_EAX_ECX_FSxBX_icebp), true, 6, // #6 811 0, 0, /* -> */ 0, X86_EFL_ZF }, 812 { BS3_CMN_NM(bs3CpuInstr2_andn_EAX_ECX_FSxBX_icebp), true, 6, // #7 813 2, ~(RTCCUINTXREG)7, /* -> */ ~(uint32_t)7, X86_EFL_SF }, 814 815 }; 816 817 BS3REGCTX Ctx; 818 BS3TRAPFRAME TrapFrame; 819 unsigned i, j; 820 uint32_t uStdExtFeatEbx = 0; 821 bool fSupportsAndN; 822 823 if (g_uBs3CpuDetected & BS3CPU_F_CPUID) 824 ASMCpuIdExSlow(7, 0, 0, 0, NULL, &uStdExtFeatEbx, NULL, NULL); 825 fSupportsAndN = RT_BOOL(uStdExtFeatEbx & X86_CPUID_STEXT_FEATURE_EBX_BMI1); 826 827 /* Ensure the structures are allocated before we sample the stack pointer. */ 828 Bs3MemSet(&Ctx, 0, sizeof(Ctx)); 829 Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); 830 831 /* 832 * Create test context. 833 */ 834 Bs3RegCtxSaveEx(&Ctx, bMode, 512); 835 836 /* 837 * Do the tests twice, first with all flags set, then once again with 838 * flags cleared. The flags are not supposed to be touched at all. 839 */ 840 Ctx.rflags.u16 |= X86_EFL_STATUS_BITS; 841 for (j = 0; j < 2; j++) 842 { 843 for (i = 0; i < RT_ELEMENTS(s_aTests); i++) 844 { 845 bool const fOkay = !BS3_MODE_IS_RM_OR_V86(bMode) && fSupportsAndN; 846 uint8_t const bExpectXcpt = fOkay ? X86_XCPT_DB : X86_XCPT_UD; 847 uint64_t uExpectRax, uExpectRip; 848 RTCCUINTXREG uMemSrc2, uMemSrc2Expect; 849 850 Ctx.rax.uCcXReg = RTCCUINTXREG_MAX * 1019; 851 Ctx.rcx.uCcXReg = s_aTests[i].uSrc1; 852 if (!s_aTests[i].fMemSrc) 853 { 854 Ctx.rbx.uCcXReg = s_aTests[i].uSrc2; 855 uMemSrc2Expect = uMemSrc2 = ~s_aTests[i].uSrc2; 856 } 857 else 858 { 859 uMemSrc2Expect = uMemSrc2 = s_aTests[i].uSrc2; 860 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, &uMemSrc2); 861 } 862 Bs3RegCtxSetRipCsFromCurPtr(&Ctx, s_aTests[i].pfnWorker); 863 uExpectRax = fOkay ? s_aTests[i].uOut : Ctx.rax.u; 864 uExpectRip = Ctx.rip.u + (fOkay ? s_aTests[i].cbInstr + 1 : 0); 865 Bs3TrapSetJmpAndRestore(&Ctx, &TrapFrame); 866 867 if ( TrapFrame.bXcpt != bExpectXcpt 868 || TrapFrame.Ctx.rip.u != uExpectRip 869 || TrapFrame.Ctx.rcx.u != Ctx.rcx.u 870 || TrapFrame.Ctx.rbx.u != Ctx.rbx.u 871 || TrapFrame.Ctx.rax.u != uExpectRax 872 /* check that nothing else really changed: */ 873 || (TrapFrame.Ctx.rflags.u16 & ANDN_CHECK_EFLAGS) 874 != ((fOkay ? s_aTests[i].fEFlags : Ctx.rflags.u16) & ANDN_CHECK_EFLAGS) 875 || (TrapFrame.Ctx.rflags.u16 & ~(ANDN_CHECK_EFLAGS | ANDN_IGNORE_EFLAGS) & X86_EFL_STATUS_BITS) 876 != (Ctx.rflags.u16 & ~(ANDN_CHECK_EFLAGS | ANDN_IGNORE_EFLAGS) & X86_EFL_STATUS_BITS) 877 || TrapFrame.Ctx.rdx.u != Ctx.rdx.u 878 || TrapFrame.Ctx.rsp.u != Ctx.rsp.u 879 || TrapFrame.Ctx.rbp.u != Ctx.rbp.u 880 || TrapFrame.Ctx.rsi.u != Ctx.rsi.u 881 || TrapFrame.Ctx.rdi.u != Ctx.rdi.u 882 || uMemSrc2 != uMemSrc2Expect 883 ) 884 { 885 Bs3TestFailedF("test #%i failed: input %#" RTCCUINTXREG_XFMT ", %#" RTCCUINTXREG_XFMT, i, s_aTests[i].uSrc1, s_aTests[i].uSrc2); 886 if (TrapFrame.bXcpt != bExpectXcpt) 887 Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bExpectXcpt, TrapFrame.bXcpt); 888 if (TrapFrame.Ctx.rip.u != uExpectRip) 889 Bs3TestFailedF("Expected RIP = %#06RX64, got %#06RX64", uExpectRip, TrapFrame.Ctx.rip.u); 890 if (TrapFrame.Ctx.rax.u != uExpectRax) 891 Bs3TestFailedF("Expected RAX = %#06RX64, got %#06RX64", uExpectRax, TrapFrame.Ctx.rax.u); 892 if (TrapFrame.Ctx.rcx.u != Ctx.rcx.u) 893 Bs3TestFailedF("Expected RCX = %#06RX64, got %#06RX64", Ctx.rcx.u, TrapFrame.Ctx.rcx.u); 894 if (TrapFrame.Ctx.rbx.u != Ctx.rbx.u) 895 Bs3TestFailedF("Expected RBX = %#06RX64, got %#06RX64 (dst)", Ctx.rbx.u, TrapFrame.Ctx.rbx.u); 896 if ( (TrapFrame.Ctx.rflags.u16 & ANDN_CHECK_EFLAGS) 897 != ((fOkay ? s_aTests[i].fEFlags : Ctx.rflags.u16) & ANDN_CHECK_EFLAGS)) 898 Bs3TestFailedF("Expected EFLAGS = %#06RX64, got %#06RX64 (output)", 899 (fOkay ? s_aTests[i].fEFlags : Ctx.rflags.u16) & ANDN_CHECK_EFLAGS, TrapFrame.Ctx.rflags.u16 & ANDN_CHECK_EFLAGS); 900 if ( (TrapFrame.Ctx.rflags.u16 & ~(ANDN_CHECK_EFLAGS | ANDN_IGNORE_EFLAGS) & X86_EFL_STATUS_BITS) 901 != (Ctx.rflags.u16 & ~(ANDN_CHECK_EFLAGS | ANDN_IGNORE_EFLAGS) & X86_EFL_STATUS_BITS)) 902 Bs3TestFailedF("Expected EFLAGS = %#06RX64, got %#06RX64 (immutable)", 903 Ctx.rflags.u16 & ~(ANDN_CHECK_EFLAGS | ANDN_IGNORE_EFLAGS) & X86_EFL_STATUS_BITS, 904 TrapFrame.Ctx.rflags.u16 & ~(ANDN_CHECK_EFLAGS | ANDN_IGNORE_EFLAGS) & X86_EFL_STATUS_BITS); 905 906 if (TrapFrame.Ctx.rdx.u != Ctx.rdx.u) 907 Bs3TestFailedF("Expected RDX = %#06RX64, got %#06RX64 (src)", Ctx.rdx.u, TrapFrame.Ctx.rdx.u); 908 if (TrapFrame.Ctx.rsp.u != Ctx.rsp.u) 909 Bs3TestFailedF("Expected RSP = %#06RX64, got %#06RX64", Ctx.rsp.u, TrapFrame.Ctx.rsp.u); 910 if (TrapFrame.Ctx.rbp.u != Ctx.rbp.u) 911 Bs3TestFailedF("Expected RBP = %#06RX64, got %#06RX64", Ctx.rbp.u, TrapFrame.Ctx.rbp.u); 912 if (TrapFrame.Ctx.rsi.u != Ctx.rsi.u) 913 Bs3TestFailedF("Expected RSI = %#06RX64, got %#06RX64", Ctx.rsi.u, TrapFrame.Ctx.rsi.u); 914 if (TrapFrame.Ctx.rdi.u != Ctx.rdi.u) 915 Bs3TestFailedF("Expected RDI = %#06RX64, got %#06RX64", Ctx.rdi.u, TrapFrame.Ctx.rdi.u); 916 if (uMemSrc2 != uMemSrc2Expect) 917 Bs3TestFailedF("Expected uMemSrc2 = %#06RX64, got %#06RX64", (uint64_t)uMemSrc2Expect, (uint64_t)uMemSrc2); 918 } 919 } 920 Ctx.rflags.u16 &= ~X86_EFL_STATUS_BITS; 921 } 922 923 return 0; 924 } 925 926 /* 927 * For testing BEXTR, SHLX SARX & SHRX. 928 */ 929 typedef struct BS3CPUINSTR2_SUBTEST_Gy_Ey_By_T 930 { 931 RTCCUINTXREG uSrc1; 932 RTCCUINTXREG uSrc2; 933 RTCCUINTXREG uOut; 934 uint16_t fEflOut; 935 } BS3CPUINSTR2_SUBTEST_Gy_Ey_By_T; 936 937 typedef struct BS3CPUINSTR2_TEST_Gy_Ey_By_T 938 { 939 FPFNBS3FAR pfnWorker; 940 bool fMemSrc; 941 uint8_t cbInstr; 942 uint8_t cSubTests; 943 BS3CPUINSTR2_SUBTEST_Gy_Ey_By_T const *paSubTests; 944 } BS3CPUINSTR2_TEST_Gy_Ey_By_T; 945 946 static uint8_t bs3CpuInstr2_Common_Gy_Ey_By(uint8_t bMode, BS3CPUINSTR2_TEST_Gy_Ey_By_T const *paTests, unsigned cTests, 947 uint32_t fStdExtFeatEbx, uint16_t fEflCheck, uint16_t fEflIgnore) 948 { 949 BS3REGCTX Ctx; 950 BS3TRAPFRAME TrapFrame; 951 unsigned i, j, k; 952 uint32_t uStdExtFeatEbx = 0; 953 bool fSupportsInstr; 954 955 fEflCheck &= ~fEflIgnore; 956 957 if (g_uBs3CpuDetected & BS3CPU_F_CPUID) 958 ASMCpuIdExSlow(7, 0, 0, 0, NULL, &uStdExtFeatEbx, NULL, NULL); 959 fSupportsInstr = RT_BOOL(uStdExtFeatEbx & fStdExtFeatEbx); 960 961 /* Ensure the structures are allocated before we sample the stack pointer. */ 962 Bs3MemSet(&Ctx, 0, sizeof(Ctx)); 963 Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); 964 965 /* 966 * Create test context. 967 */ 968 Bs3RegCtxSaveEx(&Ctx, bMode, 512); 969 970 /* 971 * Do the tests twice, first with all flags set, then once again with 972 * flags cleared. The flags are not supposed to be touched at all. 973 */ 974 Ctx.rflags.u16 |= X86_EFL_STATUS_BITS; 975 for (j = 0; j < 2; j++) 976 { 977 for (i = 0; i < cTests; i++) 978 { 979 for (k = 0; k < paTests[i].cSubTests; k++) 980 { 981 bool const fOkay = !BS3_MODE_IS_RM_OR_V86(bMode) && fSupportsInstr; 982 uint8_t const bExpectXcpt = fOkay ? X86_XCPT_DB : X86_XCPT_UD; 983 uint64_t uExpectRax, uExpectRip; 984 RTCCUINTXREG uMemSrc1, uMemSrc1Expect; 985 986 Ctx.rax.uCcXReg = RTCCUINTXREG_MAX * 1019; 987 Ctx.rcx.uCcXReg = paTests[i].paSubTests[k].uSrc2; 988 if (!paTests[i].fMemSrc) 989 { 990 Ctx.rbx.uCcXReg = paTests[i].paSubTests[k].uSrc1; 991 uMemSrc1Expect = uMemSrc1 = ~paTests[i].paSubTests[k].uSrc1; 992 } 993 else 994 { 995 uMemSrc1Expect = uMemSrc1 = paTests[i].paSubTests[k].uSrc1; 996 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, &uMemSrc1); 997 } 998 Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[i].pfnWorker); 999 uExpectRax = fOkay ? paTests[i].paSubTests[k].uOut : Ctx.rax.u; 1000 uExpectRip = Ctx.rip.u + (fOkay ? paTests[i].cbInstr + 1 : 0); 1001 Bs3TrapSetJmpAndRestore(&Ctx, &TrapFrame); 1002 1003 if ( TrapFrame.bXcpt != bExpectXcpt 1004 || TrapFrame.Ctx.rip.u != uExpectRip 1005 || TrapFrame.Ctx.rcx.u != Ctx.rcx.u 1006 || TrapFrame.Ctx.rbx.u != Ctx.rbx.u 1007 || TrapFrame.Ctx.rax.u != uExpectRax 1008 /* check that nothing else really changed: */ 1009 || (TrapFrame.Ctx.rflags.u16 & fEflCheck) 1010 != ((fOkay ? paTests[i].paSubTests[k].fEflOut : Ctx.rflags.u16) & fEflCheck) 1011 || (TrapFrame.Ctx.rflags.u16 & ~(fEflCheck | fEflIgnore) & X86_EFL_STATUS_BITS) 1012 != (Ctx.rflags.u16 & ~(fEflCheck | fEflIgnore) & X86_EFL_STATUS_BITS) 1013 || TrapFrame.Ctx.rdx.u != Ctx.rdx.u 1014 || TrapFrame.Ctx.rsp.u != Ctx.rsp.u 1015 || TrapFrame.Ctx.rbp.u != Ctx.rbp.u 1016 || TrapFrame.Ctx.rsi.u != Ctx.rsi.u 1017 || TrapFrame.Ctx.rdi.u != Ctx.rdi.u 1018 || uMemSrc1 != uMemSrc1Expect 1019 ) 1020 { 1021 Bs3TestFailedF("test #%i/%i failed: input %#" RTCCUINTXREG_XFMT ", %#" RTCCUINTXREG_XFMT, 1022 i, k, paTests[i].paSubTests[k].uSrc1, paTests[i].paSubTests[k].uSrc2); 1023 if (TrapFrame.bXcpt != bExpectXcpt) 1024 Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bExpectXcpt, TrapFrame.bXcpt); 1025 if (TrapFrame.Ctx.rip.u != uExpectRip) 1026 Bs3TestFailedF("Expected RIP = %#06RX64, got %#06RX64", uExpectRip, TrapFrame.Ctx.rip.u); 1027 if (TrapFrame.Ctx.rax.u != uExpectRax) 1028 Bs3TestFailedF("Expected RAX = %#06RX64, got %#06RX64", uExpectRax, TrapFrame.Ctx.rax.u); 1029 if (TrapFrame.Ctx.rcx.u != Ctx.rcx.u) 1030 Bs3TestFailedF("Expected RCX = %#06RX64, got %#06RX64", Ctx.rcx.u, TrapFrame.Ctx.rcx.u); 1031 if (TrapFrame.Ctx.rbx.u != Ctx.rbx.u) 1032 Bs3TestFailedF("Expected RBX = %#06RX64, got %#06RX64 (dst)", Ctx.rbx.u, TrapFrame.Ctx.rbx.u); 1033 if ( (TrapFrame.Ctx.rflags.u16 & fEflCheck) 1034 != ((fOkay ? paTests[i].paSubTests[k].fEflOut : Ctx.rflags.u16) & fEflCheck)) 1035 Bs3TestFailedF("Expected EFLAGS = %#06RX64, got %#06RX64 (output)", 1036 (fOkay ? paTests[i].paSubTests[k].fEflOut : Ctx.rflags.u16) & fEflCheck, 1037 TrapFrame.Ctx.rflags.u16 & fEflCheck); 1038 if ( (TrapFrame.Ctx.rflags.u16 & ~(fEflCheck | fEflIgnore) & X86_EFL_STATUS_BITS) 1039 != (Ctx.rflags.u16 & ~(fEflCheck | fEflIgnore) & X86_EFL_STATUS_BITS)) 1040 Bs3TestFailedF("Expected EFLAGS = %#06RX64, got %#06RX64 (immutable)", 1041 Ctx.rflags.u16 & ~(fEflCheck | fEflIgnore) & X86_EFL_STATUS_BITS, 1042 TrapFrame.Ctx.rflags.u16 & ~(fEflCheck | fEflIgnore) & X86_EFL_STATUS_BITS); 1043 1044 if (TrapFrame.Ctx.rdx.u != Ctx.rdx.u) 1045 Bs3TestFailedF("Expected RDX = %#06RX64, got %#06RX64 (src)", Ctx.rdx.u, TrapFrame.Ctx.rdx.u); 1046 if (TrapFrame.Ctx.rsp.u != Ctx.rsp.u) 1047 Bs3TestFailedF("Expected RSP = %#06RX64, got %#06RX64", Ctx.rsp.u, TrapFrame.Ctx.rsp.u); 1048 if (TrapFrame.Ctx.rbp.u != Ctx.rbp.u) 1049 Bs3TestFailedF("Expected RBP = %#06RX64, got %#06RX64", Ctx.rbp.u, TrapFrame.Ctx.rbp.u); 1050 if (TrapFrame.Ctx.rsi.u != Ctx.rsi.u) 1051 Bs3TestFailedF("Expected RSI = %#06RX64, got %#06RX64", Ctx.rsi.u, TrapFrame.Ctx.rsi.u); 1052 if (TrapFrame.Ctx.rdi.u != Ctx.rdi.u) 1053 Bs3TestFailedF("Expected RDI = %#06RX64, got %#06RX64", Ctx.rdi.u, TrapFrame.Ctx.rdi.u); 1054 if (uMemSrc1 != uMemSrc1Expect) 1055 Bs3TestFailedF("Expected uMemSrc1 = %#06RX64, got %#06RX64", (uint64_t)uMemSrc1Expect, (uint64_t)uMemSrc1); 1056 } 1057 } 1058 } 1059 Ctx.rflags.u16 &= ~X86_EFL_STATUS_BITS; 1060 } 1061 1062 return 0; 1063 } 1064 1065 1066 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_bextr)(uint8_t bMode) 1067 { 1068 /* 64 bits register width (32 bits in 32- and 16-bit modes): */ 1069 static BS3CPUINSTR2_SUBTEST_Gy_Ey_By_T const s_aSubTests64[] = 1070 { 1071 { 0, RT_MAKE_U16(0, 0), /* -> */ 0, X86_EFL_ZF }, 1072 { 0, RT_MAKE_U16(16, 33), /* -> */ 0, X86_EFL_ZF }, 1073 { ~(RTCCUINTXREG)7, RT_MAKE_U16(2, 4), /* -> */ 0xe, 0}, 1074 { ~(RTCCUINTXREG)7, RT_MAKE_U16(40, 8), /* -> */ ARCH_BITS == 64 ? 0xff : 0x00, ARCH_BITS == 64 ? 0 : X86_EFL_ZF }, 1075 }; 1076 1077 /* 32-bit register width */ 1078 static BS3CPUINSTR2_SUBTEST_Gy_Ey_By_T const s_aSubTests32[] = 1079 { 1080 { 0, RT_MAKE_U16(0, 0), /* -> */ 0, X86_EFL_ZF }, 1081 { 0, RT_MAKE_U16(16, 18), /* -> */ 0, X86_EFL_ZF }, 1082 { ~(RTCCUINTXREG)7, RT_MAKE_U16(2, 4), /* -> */ 0xe, 0 }, 1083 { ~(RTCCUINTXREG)7, RT_MAKE_U16(24, 8), /* -> */ 0xff, 0 }, 1084 { ~(RTCCUINTXREG)7, RT_MAKE_U16(31, 9), /* -> */ 1, 0 }, 1085 { ~(RTCCUINTXREG)7, RT_MAKE_U16(42, 8), /* -> */ 0, X86_EFL_ZF }, 1086 }; 1087 1088 static BS3CPUINSTR2_TEST_Gy_Ey_By_T const s_aTests[] = 1089 { 1090 { BS3_CMN_NM(bs3CpuInstr2_bextr_RAX_RBX_RCX_icebp), false, 5, RT_ELEMENTS(s_aSubTests64), s_aSubTests64 }, 1091 { BS3_CMN_NM(bs3CpuInstr2_bextr_RAX_FSxBX_RCX_icebp), true, 6, RT_ELEMENTS(s_aSubTests64), s_aSubTests64 }, 1092 { BS3_CMN_NM(bs3CpuInstr2_bextr_EAX_EBX_ECX_icebp), false, 5, RT_ELEMENTS(s_aSubTests32), s_aSubTests32 }, 1093 { BS3_CMN_NM(bs3CpuInstr2_bextr_EAX_FSxBX_ECX_icebp), true, 6, RT_ELEMENTS(s_aSubTests32), s_aSubTests32 }, 1094 }; 1095 return bs3CpuInstr2_Common_Gy_Ey_By(bMode, s_aTests, RT_ELEMENTS(s_aTests), X86_CPUID_STEXT_FEATURE_EBX_BMI1, 1096 X86_EFL_STATUS_BITS, X86_EFL_AF | X86_EFL_SF | X86_EFL_PF); 1097 } 1098 1099 1100 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_shlx)(uint8_t bMode) 1101 { 1102 /* 64 bits register width (32 bits in 32- and 16-bit modes): */ 1103 static BS3CPUINSTR2_SUBTEST_Gy_Ey_By_T const s_aSubTests64[] = 1104 { 1105 { 0, 0, /* -> */ 0, 0 }, 1106 { 0, ~(RTCCUINTXREG)3, /* -> */ 0, 0 }, 1107 { ~(RTCCUINTXREG)7, 8, /* -> */ ~(RTCCUINTXREG)0x7ff, 0}, 1108 { ~(RTCCUINTXREG)7, 40, /* -> */ ~(RTCCUINTXREG)7 << (ARCH_BITS == 64 ? 40 : 8), 0 }, 1109 { ~(RTCCUINTXREG)7, 72, /* -> */ ~(RTCCUINTXREG)7 << 8, 0 }, 1110 }; 1111 1112 /* 32-bit register width */ 1113 static BS3CPUINSTR2_SUBTEST_Gy_Ey_By_T const s_aSubTests32[] = 1114 { 1115 { 0, 0, /* -> */ 0, 0 }, 1116 { 0, ~(RTCCUINTXREG)9, /* -> */ 0, 0 }, 1117 { ~(RTCCUINTXREG)7, 8, /* -> */ UINT32_C(0xfffff800), 0 }, 1118 { ~(RTCCUINTXREG)7, 8, /* -> */ UINT32_C(0xfffff800), 0 }, 1119 }; 1120 1121 static BS3CPUINSTR2_TEST_Gy_Ey_By_T const s_aTests[] = 1122 { 1123 { BS3_CMN_NM(bs3CpuInstr2_shlx_RAX_RBX_RCX_icebp), false, 5, RT_ELEMENTS(s_aSubTests64), s_aSubTests64 }, 1124 { BS3_CMN_NM(bs3CpuInstr2_shlx_RAX_FSxBX_RCX_icebp), true, 6, RT_ELEMENTS(s_aSubTests64), s_aSubTests64 }, 1125 { BS3_CMN_NM(bs3CpuInstr2_shlx_EAX_EBX_ECX_icebp), false, 5, RT_ELEMENTS(s_aSubTests32), s_aSubTests32 }, 1126 { BS3_CMN_NM(bs3CpuInstr2_shlx_EAX_FSxBX_ECX_icebp), true, 6, RT_ELEMENTS(s_aSubTests32), s_aSubTests32 }, 1127 }; 1128 return bs3CpuInstr2_Common_Gy_Ey_By(bMode, s_aTests, RT_ELEMENTS(s_aTests), X86_CPUID_STEXT_FEATURE_EBX_BMI1, 1129 0, 0); 1130 } 1131 1132 1133 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_sarx)(uint8_t bMode) 1134 { 1135 /* 64 bits register width (32 bits in 32- and 16-bit modes): */ 1136 static BS3CPUINSTR2_SUBTEST_Gy_Ey_By_T const s_aSubTests64[] = 1137 { 1138 { 0, 0, /* -> */ 0, 0 }, 1139 { 0, ~(RTCCUINTXREG)3, /* -> */ 0, 0 }, 1140 { (RTCCUINTXREG)1 << (RTCCINTXREG_BITS - 1), RTCCINTXREG_BITS - 1, /* -> */ ~(RTCCUINTXREG)0, 0 }, 1141 { (RTCCUINTXREG)1 << (RTCCINTXREG_BITS - 1), RTCCINTXREG_BITS - 1 + 64, /* -> */ ~(RTCCUINTXREG)0, 0 }, 1142 { (RTCCUINTXREG)1 << (RTCCINTXREG_BITS - 2), RTCCINTXREG_BITS - 3, /* -> */ 2, 0 }, 1143 { (RTCCUINTXREG)1 << (RTCCINTXREG_BITS - 2), RTCCINTXREG_BITS - 3 + 64, /* -> */ 2, 0 }, 1144 }; 1145 1146 /* 32-bit register width */ 1147 static BS3CPUINSTR2_SUBTEST_Gy_Ey_By_T const s_aSubTests32[] = 1148 { 1149 { 0, 0, /* -> */ 0, 0 }, 1150 { 0, ~(RTCCUINTXREG)9, /* -> */ 0, 0 }, 1151 { ~(RTCCUINTXREG)UINT32_C(0x7fffffff), 24, /* -> */ UINT32_C(0xffffff80), 0 }, 1152 { ~(RTCCUINTXREG)UINT32_C(0x7fffffff), 24+32, /* -> */ UINT32_C(0xffffff80), 0 }, 1153 { ~(RTCCUINTXREG)UINT32_C(0xbfffffff), 24, /* -> */ UINT32_C(0x40), 0 }, 1154 { ~(RTCCUINTXREG)UINT32_C(0xbfffffff), 24+32, /* -> */ UINT32_C(0x40), 0 }, 1155 }; 1156 1157 static BS3CPUINSTR2_TEST_Gy_Ey_By_T const s_aTests[] = 1158 { 1159 { BS3_CMN_NM(bs3CpuInstr2_sarx_RAX_RBX_RCX_icebp), false, 5, RT_ELEMENTS(s_aSubTests64), s_aSubTests64 }, 1160 { BS3_CMN_NM(bs3CpuInstr2_sarx_RAX_FSxBX_RCX_icebp), true, 6, RT_ELEMENTS(s_aSubTests64), s_aSubTests64 }, 1161 { BS3_CMN_NM(bs3CpuInstr2_sarx_EAX_EBX_ECX_icebp), false, 5, RT_ELEMENTS(s_aSubTests32), s_aSubTests32 }, 1162 { BS3_CMN_NM(bs3CpuInstr2_sarx_EAX_FSxBX_ECX_icebp), true, 6, RT_ELEMENTS(s_aSubTests32), s_aSubTests32 }, 1163 }; 1164 return bs3CpuInstr2_Common_Gy_Ey_By(bMode, s_aTests, RT_ELEMENTS(s_aTests), X86_CPUID_STEXT_FEATURE_EBX_BMI1, 1165 0, 0); 1166 } 1167 1168 1169 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_shrx)(uint8_t bMode) 1170 { 1171 /* 64 bits register width (32 bits in 32- and 16-bit modes): */ 1172 static BS3CPUINSTR2_SUBTEST_Gy_Ey_By_T const s_aSubTests64[] = 1173 { 1174 { 0, 0, /* -> */ 0, 0 }, 1175 { 0, ~(RTCCUINTXREG)3, /* -> */ 0, 0 }, 1176 { (RTCCUINTXREG)1 << (RTCCINTXREG_BITS - 1), RTCCINTXREG_BITS - 1, /* -> */ 1, 0 }, 1177 { (RTCCUINTXREG)1 << (RTCCINTXREG_BITS - 1), RTCCINTXREG_BITS - 1 + 64, /* -> */ 1, 0 }, 1178 { (RTCCUINTXREG)1 << (RTCCINTXREG_BITS - 2), RTCCINTXREG_BITS - 3, /* -> */ 2, 0 }, 1179 { (RTCCUINTXREG)1 << (RTCCINTXREG_BITS - 2), RTCCINTXREG_BITS - 3 + 64, /* -> */ 2, 0 }, 1180 }; 1181 1182 /* 32-bit register width */ 1183 static BS3CPUINSTR2_SUBTEST_Gy_Ey_By_T const s_aSubTests32[] = 1184 { 1185 { 0, 0, /* -> */ 0, 0 }, 1186 { 0, ~(RTCCUINTXREG)9, /* -> */ 0, 0 }, 1187 { ~(RTCCUINTXREG)UINT32_C(0x7fffffff), 24, /* -> */ UINT32_C(0x80), 0 }, 1188 { ~(RTCCUINTXREG)UINT32_C(0x7fffffff), 24+32, /* -> */ UINT32_C(0x80), 0 }, 1189 { ~(RTCCUINTXREG)UINT32_C(0xbfffffff), 24, /* -> */ UINT32_C(0x40), 0 }, 1190 { ~(RTCCUINTXREG)UINT32_C(0xbfffffff), 24+32, /* -> */ UINT32_C(0x40), 0 }, 1191 }; 1192 1193 static BS3CPUINSTR2_TEST_Gy_Ey_By_T const s_aTests[] = 1194 { 1195 { BS3_CMN_NM(bs3CpuInstr2_shrx_RAX_RBX_RCX_icebp), false, 5, RT_ELEMENTS(s_aSubTests64), s_aSubTests64 }, 1196 { BS3_CMN_NM(bs3CpuInstr2_shrx_RAX_FSxBX_RCX_icebp), true, 6, RT_ELEMENTS(s_aSubTests64), s_aSubTests64 }, 1197 { BS3_CMN_NM(bs3CpuInstr2_shrx_EAX_EBX_ECX_icebp), false, 5, RT_ELEMENTS(s_aSubTests32), s_aSubTests32 }, 1198 { BS3_CMN_NM(bs3CpuInstr2_shrx_EAX_FSxBX_ECX_icebp), true, 6, RT_ELEMENTS(s_aSubTests32), s_aSubTests32 }, 1199 }; 1200 return bs3CpuInstr2_Common_Gy_Ey_By(bMode, s_aTests, RT_ELEMENTS(s_aTests), X86_CPUID_STEXT_FEATURE_EBX_BMI1, 1201 0, 0); 748 1202 } 749 1203 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2-template.mac
r95303 r95305 156 156 BS3_PROC_END_CMN bs3CpuInstr2_rorx_RBX_DSxDI_68_icebp 157 157 158 ; 159 ; ANDN (BMI1) 160 ; 161 BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_RAX_RCX_RBX_icebp, BS3_PBC_NEAR 162 %if TMPL_BITS == 64 163 andn rax, rcx, rbx 164 %else 165 db 0C4h,0E2h,0F0h,0F2h,0C3h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe) 166 %endif 167 .again: 168 icebp 169 jmp .again 170 BS3_PROC_END_CMN bs3CpuInstr2_andn_RAX_RCX_RBX_icebp 171 172 BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_EAX_ECX_EBX_icebp, BS3_PBC_NEAR 173 andn eax, ecx, ebx 174 .again: 175 icebp 176 jmp .again 177 BS3_PROC_END_CMN bs3CpuInstr2_andn_EAX_ECX_EBX_icebp 178 179 180 BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_RAX_RCX_FSxBX_icebp, BS3_PBC_NEAR 181 %if TMPL_BITS == 64 182 andn rax, rcx, [fs:rbx] 183 %elif TMPL_BITS == 32 184 db 064h,0C4h,0E2h,0F0h,0F2h,003h ; andn rax, rcx, [fs:ebx] 185 %else 186 db 064h,0C4h,0E2h,0F0h,0F2h,007h ; andn rax, rcx, [fs:bx] 187 %endif 188 .again: 189 icebp 190 jmp .again 191 BS3_PROC_END_CMN bs3CpuInstr2_andn_RAX_RCX_FSxBX_icebp 192 193 BS3_PROC_BEGIN_CMN bs3CpuInstr2_andn_EAX_ECX_FSxBX_icebp, BS3_PBC_NEAR 194 andn eax, ecx, [fs:xBX] 195 .again: 196 icebp 197 jmp .again 198 BS3_PROC_END_CMN bs3CpuInstr2_andn_EAX_ECX_FSxBX_icebp 199 200 201 ; 202 ; BEXTR / SHLX / SARX / SHRX - BMI1 203 ; These are encoded in the exact same way, only the VEX.pp differs. 204 ; 205 %ifndef SHLX_SARX_SHRX_DEFINED 206 %define SHLX_SARX_SHRX_DEFINED 207 %macro SHLX_SARX_SHRX 2 208 209 BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_RCX_icebp, BS3_PBC_NEAR 210 %if TMPL_BITS == 64 211 %1 rax, rbx, rcx ; SHLX=C4E2F1F7C3 212 %else 213 db 0C4h,0E2h,0F0h|%2,0F7h,0C3h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe) 214 %endif 215 .again: 216 icebp 217 jmp .again 218 BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_RCX_icebp 219 220 BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_ECX_icebp, BS3_PBC_NEAR 221 %1 eax, ebx, ecx 222 .again: 223 icebp 224 jmp .again 225 BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_ECX_icebp 226 227 BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_RCX_icebp, BS3_PBC_NEAR 228 %if TMPL_BITS == 64 229 %1 rax, [fs:rbx], rcx ; SHLX=64C4E2F1F703 230 %elif TMPL_BITS == 32 231 db 064h,0C4h,0E2h,0F0h|%2,0F7h,003h 232 %else 233 db 064h,0C4h,0E2h,0F0h|%2,0F7h,007h 234 %endif 235 .again: 236 icebp 237 jmp .again 238 BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_RCX_icebp 239 240 BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_ECX_icebp, BS3_PBC_NEAR 241 %1 eax, [fs:xBX], ecx 242 .again: 243 icebp 244 jmp .again 245 BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_ECX_icebp 246 247 %endmacro 248 %endif 249 250 SHLX_SARX_SHRX bextr, 0 ; none 251 SHLX_SARX_SHRX shlx, 1 ; 66h 252 SHLX_SARX_SHRX sarx, 2 ; f3h 253 SHLX_SARX_SHRX shrx, 3 ; f2h 158 254 159 255 ; -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2.c
r95296 r95305 40 40 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_idiv); 41 41 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_rorx); 42 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_andn); 43 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_bextr); 44 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_shlx); 45 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_sarx); 46 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_shrx); 42 47 BS3TESTMODE_PROTOTYPES_CMN_64(bs3CpuInstr2_cmpxchg16b); 43 48 BS3TESTMODE_PROTOTYPES_CMN_64(bs3CpuInstr2_wrfsbase); … … 52 57 static const BS3TESTMODEENTRY g_aModeTests[] = 53 58 { 59 #if 1 54 60 BS3TESTMODEENTRY_CMN("mul", bs3CpuInstr2_mul), 55 61 BS3TESTMODEENTRY_CMN("imul", bs3CpuInstr2_imul), 56 62 BS3TESTMODEENTRY_CMN("div", bs3CpuInstr2_div), 57 63 BS3TESTMODEENTRY_CMN("idiv", bs3CpuInstr2_idiv), 58 BS3TESTMODEENTRY_CMN("rorx", bs3CpuInstr2_rorx), 64 #endif 65 #if 1 /* BMI1 & BMI2 */ 66 BS3TESTMODEENTRY_CMN("rorx", bs3CpuInstr2_rorx), 67 BS3TESTMODEENTRY_CMN("andn", bs3CpuInstr2_andn), 68 BS3TESTMODEENTRY_CMN("bextr", bs3CpuInstr2_bextr), 69 BS3TESTMODEENTRY_CMN("shlx", bs3CpuInstr2_shlx), 70 BS3TESTMODEENTRY_CMN("sarx", bs3CpuInstr2_sarx), 71 BS3TESTMODEENTRY_CMN("shrx", bs3CpuInstr2_shrx), 72 #endif 73 #if 1 59 74 BS3TESTMODEENTRY_CMN_64("cmpxchg16b", bs3CpuInstr2_cmpxchg16b), 60 75 BS3TESTMODEENTRY_CMN_64("wrfsbase", bs3CpuInstr2_wrfsbase), … … 62 77 BS3TESTMODEENTRY_CMN_64("rdfsbase", bs3CpuInstr2_rdfsbase), 63 78 BS3TESTMODEENTRY_CMN_64("rdgsbase", bs3CpuInstr2_rdgsbase), 79 #endif 64 80 }; 65 81
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