Changeset 95306 in vbox
- Timestamp:
- Jun 19, 2022 8:07:38 PM (2 years ago)
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 3 edited
-
bs3-cpu-instr-2-template.c (modified) (2 diffs)
-
bs3-cpu-instr-2-template.mac (modified) (1 diff)
-
bs3-cpu-instr-2.c (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2-template.c
r95305 r95306 62 62 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_div_xBX_ud2); 63 63 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_idiv_xBX_ud2); 64 65 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_bsf_AX_BX_ud2); 66 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_bsf_EAX_EBX_ud2); 67 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_bsf_RAX_RBX_ud2); 68 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_bsf_AX_FSxBX_ud2); 69 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_bsf_EAX_FSxBX_ud2); 70 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_bsf_RAX_FSxBX_ud2); 71 72 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_f2_bsf_AX_BX_ud2); 73 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_f2_bsf_EAX_EBX_ud2); 74 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_f2_bsf_RAX_RBX_ud2); 75 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_f2_bsf_AX_FSxBX_ud2); 76 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_f2_bsf_EAX_FSxBX_ud2); 77 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_f2_bsf_RAX_FSxBX_ud2); 78 79 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_tzcnt_AX_BX_ud2); 80 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_tzcnt_EAX_EBX_ud2); 81 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_tzcnt_RAX_RBX_ud2); 82 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_tzcnt_AX_FSxBX_ud2); 83 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_tzcnt_EAX_FSxBX_ud2); 84 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_tzcnt_RAX_FSxBX_ud2); 85 86 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_f2_tzcnt_AX_BX_ud2); 87 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_f2_tzcnt_EAX_EBX_ud2); 88 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_f2_tzcnt_RAX_RBX_ud2); 89 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_f2_tzcnt_AX_FSxBX_ud2); 90 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_f2_tzcnt_EAX_FSxBX_ud2); 91 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_f2_tzcnt_RAX_FSxBX_ud2); 92 93 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_bsr_AX_BX_ud2); 94 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_bsr_EAX_EBX_ud2); 95 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_bsr_RAX_RBX_ud2); 96 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_bsr_AX_FSxBX_ud2); 97 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_bsr_EAX_FSxBX_ud2); 98 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_bsr_RAX_FSxBX_ud2); 99 100 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_f2_bsr_AX_BX_ud2); 101 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_f2_bsr_EAX_EBX_ud2); 102 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_f2_bsr_RAX_RBX_ud2); 103 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_f2_bsr_AX_FSxBX_ud2); 104 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_f2_bsr_EAX_FSxBX_ud2); 105 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_f2_bsr_RAX_FSxBX_ud2); 106 107 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_lzcnt_AX_BX_ud2); 108 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_lzcnt_EAX_EBX_ud2); 109 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_lzcnt_RAX_RBX_ud2); 110 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_lzcnt_AX_FSxBX_ud2); 111 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_lzcnt_EAX_FSxBX_ud2); 112 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_lzcnt_RAX_FSxBX_ud2); 113 114 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_f2_lzcnt_AX_BX_ud2); 115 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_f2_lzcnt_EAX_EBX_ud2); 116 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_f2_lzcnt_RAX_RBX_ud2); 117 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_f2_lzcnt_AX_FSxBX_ud2); 118 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_f2_lzcnt_EAX_FSxBX_ud2); 119 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_f2_lzcnt_RAX_FSxBX_ud2); 64 120 65 121 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_rorx_RBX_RDX_2_icebp); … … 634 690 635 691 692 /* 693 * BSF/BSR (386+) & TZCNT/LZCNT (BMI1,ABM) 694 */ 695 696 typedef struct BS3CPUINSTR2_SUBTEST_BITSCAN_T 697 { 698 RTCCUINTXREG uSrc; 699 RTCCUINTXREG uOut; 700 bool fOutNotSet; 701 uint16_t fEflOut; 702 } BS3CPUINSTR2_SUBTEST_BITSCAN_T; 703 704 typedef struct BS3CPUINSTR2_TEST_BITSCAN_T 705 { 706 FPFNBS3FAR pfnWorker; 707 bool fMemSrc; 708 uint8_t cbInstr; 709 uint8_t cOpBits; 710 uint16_t fEflCheck; 711 uint8_t cSubTests; 712 BS3CPUINSTR2_SUBTEST_BITSCAN_T const *paSubTests; 713 } BS3CPUINSTR2_TEST_BITSCAN_T; 714 715 static uint8_t bs3CpuInstr2_BitScan(uint8_t bMode, BS3CPUINSTR2_TEST_BITSCAN_T const *paTests, unsigned cTests) 716 { 717 BS3REGCTX Ctx; 718 BS3TRAPFRAME TrapFrame; 719 unsigned i, j, k; 720 721 /* Ensure the structures are allocated before we sample the stack pointer. */ 722 Bs3MemSet(&Ctx, 0, sizeof(Ctx)); 723 Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); 724 725 /* 726 * Create test context. 727 */ 728 Bs3RegCtxSaveEx(&Ctx, bMode, 512); 729 730 /* 731 * Do the tests twice, first with all flags set, then once again with 732 * flags cleared. The flags are not supposed to be touched at all. 733 */ 734 Ctx.rflags.u16 |= X86_EFL_STATUS_BITS; 735 for (j = 0; j < 2; j++) 736 { 737 for (i = 0; i < cTests; i++) 738 { 739 for (k = 0; k < paTests[i].cSubTests; k++) 740 { 741 uint64_t uExpectRax, uExpectRip; 742 RTCCUINTXREG uMemSrc, uMemSrcExpect; 743 744 Ctx.rax.uCcXReg = RTCCUINTXREG_MAX * 1019; 745 if (!paTests[i].fMemSrc) 746 { 747 Ctx.rbx.uCcXReg = paTests[i].paSubTests[k].uSrc; 748 uMemSrcExpect = uMemSrc = ~paTests[i].paSubTests[k].uSrc; 749 } 750 else 751 { 752 uMemSrcExpect = uMemSrc = paTests[i].paSubTests[k].uSrc; 753 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, &uMemSrc); 754 } 755 Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[i].pfnWorker); 756 if (paTests[i].paSubTests[k].fOutNotSet) 757 uExpectRax = Ctx.rax.u; 758 else if (paTests[i].cOpBits != 16) 759 uExpectRax = paTests[i].paSubTests[k].uOut; 760 else 761 uExpectRax = paTests[i].paSubTests[k].uOut | (Ctx.rax.u & UINT64_C(0xffffffffffff0000)); 762 uExpectRip = Ctx.rip.u + paTests[i].cbInstr; 763 Bs3TrapSetJmpAndRestore(&Ctx, &TrapFrame); 764 765 if ( TrapFrame.bXcpt != X86_XCPT_UD 766 || TrapFrame.Ctx.rip.u != uExpectRip 767 || TrapFrame.Ctx.rbx.u != Ctx.rbx.u 768 || TrapFrame.Ctx.rax.u != uExpectRax 769 || (TrapFrame.Ctx.rflags.u16 & paTests[i].fEflCheck) 770 != (paTests[i].paSubTests[k].fEflOut & paTests[i].fEflCheck) 771 /* check that nothing else really changed: */ 772 || TrapFrame.Ctx.rcx.u != Ctx.rcx.u 773 || TrapFrame.Ctx.rdx.u != Ctx.rdx.u 774 || TrapFrame.Ctx.rsp.u != Ctx.rsp.u 775 || TrapFrame.Ctx.rbp.u != Ctx.rbp.u 776 || TrapFrame.Ctx.rsi.u != Ctx.rsi.u 777 || TrapFrame.Ctx.rdi.u != Ctx.rdi.u 778 || uMemSrc != uMemSrcExpect 779 ) 780 { 781 Bs3TestFailedF("test #%i/%i failed: input %#" RTCCUINTXREG_XFMT, 782 i, k, paTests[i].paSubTests[k].uSrc); 783 if (TrapFrame.bXcpt != X86_XCPT_UD) 784 Bs3TestFailedF("Expected bXcpt = %#x, got %#x", X86_XCPT_UD, TrapFrame.bXcpt); 785 if (TrapFrame.Ctx.rip.u != uExpectRip) 786 Bs3TestFailedF("Expected RIP = %#06RX64, got %#06RX64", uExpectRip, TrapFrame.Ctx.rip.u); 787 if (TrapFrame.Ctx.rax.u != uExpectRax) 788 Bs3TestFailedF("Expected RAX = %#06RX64, got %#06RX64", uExpectRax, TrapFrame.Ctx.rax.u); 789 if (TrapFrame.Ctx.rcx.u != Ctx.rcx.u) 790 Bs3TestFailedF("Expected RCX = %#06RX64, got %#06RX64", Ctx.rcx.u, TrapFrame.Ctx.rcx.u); 791 if (TrapFrame.Ctx.rbx.u != Ctx.rbx.u) 792 Bs3TestFailedF("Expected RBX = %#06RX64, got %#06RX64 (dst)", Ctx.rbx.u, TrapFrame.Ctx.rbx.u); 793 if ( (TrapFrame.Ctx.rflags.u16 & paTests[i].fEflCheck) 794 != (paTests[i].paSubTests[k].fEflOut & paTests[i].fEflCheck)) 795 Bs3TestFailedF("Expected EFLAGS = %#06RX64, got %#06RX64 (output)", 796 paTests[i].paSubTests[k].fEflOut & paTests[i].fEflCheck, 797 TrapFrame.Ctx.rflags.u16 & paTests[i].fEflCheck); 798 799 if (TrapFrame.Ctx.rdx.u != Ctx.rdx.u) 800 Bs3TestFailedF("Expected RDX = %#06RX64, got %#06RX64 (src)", Ctx.rdx.u, TrapFrame.Ctx.rdx.u); 801 if (TrapFrame.Ctx.rsp.u != Ctx.rsp.u) 802 Bs3TestFailedF("Expected RSP = %#06RX64, got %#06RX64", Ctx.rsp.u, TrapFrame.Ctx.rsp.u); 803 if (TrapFrame.Ctx.rbp.u != Ctx.rbp.u) 804 Bs3TestFailedF("Expected RBP = %#06RX64, got %#06RX64", Ctx.rbp.u, TrapFrame.Ctx.rbp.u); 805 if (TrapFrame.Ctx.rsi.u != Ctx.rsi.u) 806 Bs3TestFailedF("Expected RSI = %#06RX64, got %#06RX64", Ctx.rsi.u, TrapFrame.Ctx.rsi.u); 807 if (TrapFrame.Ctx.rdi.u != Ctx.rdi.u) 808 Bs3TestFailedF("Expected RDI = %#06RX64, got %#06RX64", Ctx.rdi.u, TrapFrame.Ctx.rdi.u); 809 if (uMemSrc != uMemSrcExpect) 810 Bs3TestFailedF("Expected uMemSrc = %#06RX64, got %#06RX64", (uint64_t)uMemSrcExpect, (uint64_t)uMemSrc); 811 } 812 } 813 } 814 Ctx.rflags.u16 &= ~X86_EFL_STATUS_BITS; 815 } 816 817 return 0; 818 } 819 820 821 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_bsf_tzcnt)(uint8_t bMode) 822 { 823 static BS3CPUINSTR2_SUBTEST_BITSCAN_T const s_aSubTestsBsf16[] = 824 { 825 { 0, /* -> */ 0, true, X86_EFL_ZF }, 826 { ~(RTCCUINTXREG)UINT16_MAX, /* -> */ 0, true, X86_EFL_ZF }, 827 { ~(RTCCUINTXREG)0, /* -> */ 0, false, 0 }, 828 { ~(RTCCUINTXREG)1, /* -> */ 1, false, 0 }, 829 { UINT16_C(0x8000), /* -> */ 15, false, 0 }, 830 { UINT16_C(0x4560), /* -> */ 5, false, 0 }, 831 }; 832 static BS3CPUINSTR2_SUBTEST_BITSCAN_T const s_aSubTestsTzCnt16[] = 833 { 834 { 0, /* -> */ 16, false, X86_EFL_CF }, 835 { ~(RTCCUINTXREG)UINT16_MAX, /* -> */ 16, false, X86_EFL_CF }, 836 { ~(RTCCUINTXREG)0, /* -> */ 0, false, X86_EFL_ZF }, 837 { ~(RTCCUINTXREG)1, /* -> */ 1, false, 0 }, 838 { UINT16_C(0x8000), /* -> */ 15, false, 0 }, 839 { UINT16_C(0x4560), /* -> */ 5, false, 0 }, 840 }; 841 static BS3CPUINSTR2_SUBTEST_BITSCAN_T const s_aSubTestsBsf32[] = 842 { 843 { 0, /* -> */ 0, true, X86_EFL_ZF }, 844 #if ARCH_BITS == 64 845 { ~(RTCCUINTXREG)UINT32_MAX, /* -> */ 0, true, X86_EFL_ZF }, 846 #endif 847 { ~(RTCCUINTXREG)0, /* -> */ 0, false, 0 }, 848 { ~(RTCCUINTXREG)1, /* -> */ 1, false, 0 }, 849 { UINT16_C(0x8000), /* -> */ 15, false, 0 }, 850 { UINT16_C(0x4560), /* -> */ 5, false, 0 }, 851 { UINT32_C(0x80000000), /* -> */ 31, false, 0 }, 852 { UINT32_C(0x45600000), /* -> */ 21, false, 0 }, 853 }; 854 static BS3CPUINSTR2_SUBTEST_BITSCAN_T const s_aSubTestsTzCnt32[] = 855 { 856 { 0, /* -> */ 32, false, X86_EFL_CF }, 857 #if ARCH_BITS == 64 858 { ~(RTCCUINTXREG)UINT32_MAX, /* -> */ 32, false, X86_EFL_CF }, 859 #endif 860 { ~(RTCCUINTXREG)0, /* -> */ 0, false, X86_EFL_ZF }, 861 { ~(RTCCUINTXREG)1, /* -> */ 1, false, 0 }, 862 { UINT16_C(0x8000), /* -> */ 15, false, 0 }, 863 { UINT16_C(0x4560), /* -> */ 5, false, 0 }, 864 { UINT32_C(0x80000000), /* -> */ 31, false, 0 }, 865 { UINT32_C(0x45600000), /* -> */ 21, false, 0 }, 866 }; 867 #if ARCH_BITS == 64 868 static BS3CPUINSTR2_SUBTEST_BITSCAN_T const s_aSubTestsBsf64[] = 869 { 870 { 0, /* -> */ 0, true, X86_EFL_ZF }, 871 { ~(RTCCUINTXREG)0, /* -> */ 0, false, 0 }, 872 { ~(RTCCUINTXREG)1, /* -> */ 1, false, 0 }, 873 { UINT16_C(0x8000), /* -> */ 15, false, 0 }, 874 { UINT16_C(0x4560), /* -> */ 5, false, 0 }, 875 { UINT32_C(0x80000000), /* -> */ 31, false, 0 }, 876 { UINT32_C(0x45600000), /* -> */ 21, false, 0 }, 877 { UINT64_C(0x8000000000000000), /* -> */ 63, false, 0 }, 878 { UINT64_C(0x4560000000000000), /* -> */ 53, false, 0 }, 879 }; 880 static BS3CPUINSTR2_SUBTEST_BITSCAN_T const s_aSubTestsTzCnt64[] = 881 { 882 { 0, /* -> */ 64, false, X86_EFL_CF }, 883 { ~(RTCCUINTXREG)0, /* -> */ 0, false, X86_EFL_ZF }, 884 { ~(RTCCUINTXREG)1, /* -> */ 1, false, 0 }, 885 { UINT16_C(0x8000), /* -> */ 15, false, 0 }, 886 { UINT16_C(0x4560), /* -> */ 5, false, 0 }, 887 { UINT32_C(0x80000000), /* -> */ 31, false, 0 }, 888 { UINT32_C(0x45600000), /* -> */ 21, false, 0 }, 889 { UINT64_C(0x8000000000000000), /* -> */ 63, false, 0 }, 890 { UINT64_C(0x4560000000000000), /* -> */ 53, false, 0 }, 891 }; 892 #endif 893 static BS3CPUINSTR2_TEST_BITSCAN_T s_aTests[] = 894 { 895 { BS3_CMN_NM(bs3CpuInstr2_bsf_AX_BX_ud2), false, 3 + (ARCH_BITS != 16), 16, X86_EFL_ZF, 896 RT_ELEMENTS(s_aSubTestsBsf16), s_aSubTestsBsf16 }, 897 { BS3_CMN_NM(bs3CpuInstr2_bsf_AX_FSxBX_ud2), true, 4 + (ARCH_BITS != 16), 16, X86_EFL_ZF, 898 RT_ELEMENTS(s_aSubTestsBsf16), s_aSubTestsBsf16 }, 899 { BS3_CMN_NM(bs3CpuInstr2_bsf_EAX_EBX_ud2), false, 3 + (ARCH_BITS == 16), 32, X86_EFL_ZF, 900 RT_ELEMENTS(s_aSubTestsBsf32), s_aSubTestsBsf32 }, 901 { BS3_CMN_NM(bs3CpuInstr2_bsf_EAX_FSxBX_ud2), true, 4 + (ARCH_BITS == 16), 32, X86_EFL_ZF, 902 RT_ELEMENTS(s_aSubTestsBsf32), s_aSubTestsBsf32 }, 903 #if ARCH_BITS == 64 904 { BS3_CMN_NM(bs3CpuInstr2_bsf_RAX_RBX_ud2), false, 4, 64, X86_EFL_ZF, 905 RT_ELEMENTS(s_aSubTestsBsf64), s_aSubTestsBsf64 }, 906 { BS3_CMN_NM(bs3CpuInstr2_bsf_RAX_FSxBX_ud2), true, 5, 64, X86_EFL_ZF, 907 RT_ELEMENTS(s_aSubTestsBsf64), s_aSubTestsBsf64 }, 908 #endif 909 /* f2 prefixed variant: */ 910 { BS3_CMN_NM(bs3CpuInstr2_f2_bsf_AX_BX_ud2), false, 4 + (ARCH_BITS != 16), 16, X86_EFL_ZF, 911 RT_ELEMENTS(s_aSubTestsBsf16), s_aSubTestsBsf16 }, 912 { BS3_CMN_NM(bs3CpuInstr2_f2_bsf_AX_FSxBX_ud2), true, 5 + (ARCH_BITS != 16), 16, X86_EFL_ZF, 913 RT_ELEMENTS(s_aSubTestsBsf16), s_aSubTestsBsf16 }, 914 { BS3_CMN_NM(bs3CpuInstr2_f2_bsf_EAX_EBX_ud2), false, 4 + (ARCH_BITS == 16), 32, X86_EFL_ZF, 915 RT_ELEMENTS(s_aSubTestsBsf32), s_aSubTestsBsf32 }, 916 { BS3_CMN_NM(bs3CpuInstr2_f2_bsf_EAX_FSxBX_ud2), true, 5 + (ARCH_BITS == 16), 32, X86_EFL_ZF, 917 RT_ELEMENTS(s_aSubTestsBsf32), s_aSubTestsBsf32 }, 918 #if ARCH_BITS == 64 919 { BS3_CMN_NM(bs3CpuInstr2_f2_bsf_RAX_RBX_ud2), false, 5, 64, X86_EFL_ZF, 920 RT_ELEMENTS(s_aSubTestsBsf64), s_aSubTestsBsf64 }, 921 { BS3_CMN_NM(bs3CpuInstr2_f2_bsf_RAX_FSxBX_ud2), true, 6, 64, X86_EFL_ZF, 922 RT_ELEMENTS(s_aSubTestsBsf64), s_aSubTestsBsf64 }, 923 #endif 924 925 /* tzcnt: */ 926 { BS3_CMN_NM(bs3CpuInstr2_tzcnt_AX_BX_ud2), false, 4 + (ARCH_BITS != 16), 16, X86_EFL_ZF | X86_EFL_CF, 927 RT_ELEMENTS(s_aSubTestsTzCnt16), s_aSubTestsTzCnt16 }, 928 { BS3_CMN_NM(bs3CpuInstr2_tzcnt_AX_FSxBX_ud2), true, 5 + (ARCH_BITS != 16), 16, X86_EFL_ZF | X86_EFL_CF, 929 RT_ELEMENTS(s_aSubTestsTzCnt16), s_aSubTestsTzCnt16 }, 930 { BS3_CMN_NM(bs3CpuInstr2_tzcnt_EAX_EBX_ud2), false, 4 + (ARCH_BITS == 16), 32, X86_EFL_ZF | X86_EFL_CF, 931 RT_ELEMENTS(s_aSubTestsTzCnt32), s_aSubTestsTzCnt32 }, 932 { BS3_CMN_NM(bs3CpuInstr2_tzcnt_EAX_FSxBX_ud2), true, 5 + (ARCH_BITS == 16), 32, X86_EFL_ZF | X86_EFL_CF, 933 RT_ELEMENTS(s_aSubTestsTzCnt32), s_aSubTestsTzCnt32 }, 934 #if ARCH_BITS == 64 935 { BS3_CMN_NM(bs3CpuInstr2_tzcnt_RAX_RBX_ud2), false, 5, 64, X86_EFL_ZF | X86_EFL_CF, 936 RT_ELEMENTS(s_aSubTestsTzCnt64), s_aSubTestsTzCnt64 }, 937 { BS3_CMN_NM(bs3CpuInstr2_tzcnt_RAX_FSxBX_ud2), true, 6, 64, X86_EFL_ZF | X86_EFL_CF, 938 RT_ELEMENTS(s_aSubTestsTzCnt64), s_aSubTestsTzCnt64 }, 939 #endif 940 /* f2 prefixed tzcnt variant (last prefix (f3) should prevail): */ 941 { BS3_CMN_NM(bs3CpuInstr2_f2_tzcnt_AX_BX_ud2), false, 5 + (ARCH_BITS != 16), 16, X86_EFL_ZF | X86_EFL_CF, 942 RT_ELEMENTS(s_aSubTestsTzCnt16), s_aSubTestsTzCnt16 }, 943 { BS3_CMN_NM(bs3CpuInstr2_f2_tzcnt_AX_FSxBX_ud2), true, 6 + (ARCH_BITS != 16), 16, X86_EFL_ZF | X86_EFL_CF, 944 RT_ELEMENTS(s_aSubTestsTzCnt16), s_aSubTestsTzCnt16 }, 945 { BS3_CMN_NM(bs3CpuInstr2_f2_tzcnt_EAX_EBX_ud2), false, 5 + (ARCH_BITS == 16), 32, X86_EFL_ZF | X86_EFL_CF, 946 RT_ELEMENTS(s_aSubTestsTzCnt32), s_aSubTestsTzCnt32 }, 947 { BS3_CMN_NM(bs3CpuInstr2_f2_tzcnt_EAX_FSxBX_ud2),true, 6 + (ARCH_BITS == 16), 32, X86_EFL_ZF | X86_EFL_CF, 948 RT_ELEMENTS(s_aSubTestsTzCnt32), s_aSubTestsTzCnt32 }, 949 #if ARCH_BITS == 64 950 { BS3_CMN_NM(bs3CpuInstr2_f2_tzcnt_RAX_RBX_ud2), false, 6, 64, X86_EFL_ZF | X86_EFL_CF, 951 RT_ELEMENTS(s_aSubTestsTzCnt64), s_aSubTestsTzCnt64 }, 952 { BS3_CMN_NM(bs3CpuInstr2_f2_tzcnt_RAX_FSxBX_ud2),true, 7, 64, X86_EFL_ZF | X86_EFL_CF, 953 RT_ELEMENTS(s_aSubTestsTzCnt64), s_aSubTestsTzCnt64 }, 954 #endif 955 }; 956 957 uint32_t uStdExtFeatEbx = 0; 958 if (g_uBs3CpuDetected & BS3CPU_F_CPUID) 959 ASMCpuIdExSlow(7, 0, 0, 0, NULL, &uStdExtFeatEbx, NULL, NULL); 960 if (!(uStdExtFeatEbx & X86_CPUID_STEXT_FEATURE_EBX_BMI1)) 961 { 962 unsigned i = RT_ELEMENTS(s_aTests); 963 while (i-- > 0) 964 if (s_aTests[i].fEflCheck & X86_EFL_CF) 965 { 966 s_aTests[i].fEflCheck = X86_EFL_ZF; 967 switch (s_aTests[i].cOpBits) 968 { 969 case 16: 970 s_aTests[i].cSubTests = RT_ELEMENTS(s_aSubTestsBsf16); 971 s_aTests[i].paSubTests = s_aSubTestsBsf16; 972 break; 973 case 32: 974 s_aTests[i].cSubTests = RT_ELEMENTS(s_aSubTestsBsf32); 975 s_aTests[i].paSubTests = s_aSubTestsBsf32; 976 break; 977 #if ARCH_BITS == 64 978 case 64: 979 s_aTests[i].cSubTests = RT_ELEMENTS(s_aSubTestsBsf64); 980 s_aTests[i].paSubTests = s_aSubTestsBsf64; 981 break; 982 #endif 983 } 984 } 985 Bs3TestPrintf("tzcnt not supported\n"); 986 } 987 988 return bs3CpuInstr2_BitScan(bMode, s_aTests, RT_ELEMENTS(s_aTests)); 989 } 990 991 992 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_bsr_lzcnt)(uint8_t bMode) 993 { 994 static BS3CPUINSTR2_SUBTEST_BITSCAN_T const s_aSubTestsBsr16[] = 995 { 996 { 0, /* -> */ 0, true, X86_EFL_ZF }, 997 { ~(RTCCUINTXREG)UINT16_MAX, /* -> */ 0, true, X86_EFL_ZF }, 998 { ~(RTCCUINTXREG)0, /* -> */ 15, false, 0 }, 999 { ~(RTCCUINTXREG)1, /* -> */ 15, false, 0 }, 1000 { UINT16_C(0x0001), /* -> */ 0, false, 0 }, 1001 { UINT16_C(0x0002), /* -> */ 1, false, 0 }, 1002 { UINT16_C(0x4560), /* -> */ 14, false, 0 }, 1003 }; 1004 static BS3CPUINSTR2_SUBTEST_BITSCAN_T const s_aSubTestsLzCnt16[] = 1005 { 1006 { 0, /* -> */ 16, false, X86_EFL_CF }, 1007 { ~(RTCCUINTXREG)UINT16_MAX, /* -> */ 16, false, X86_EFL_CF }, 1008 { ~(RTCCUINTXREG)0, /* -> */ 0, false, X86_EFL_ZF }, 1009 { ~(RTCCUINTXREG)1, /* -> */ 0, false, X86_EFL_ZF }, 1010 { UINT16_C(0x8000), /* -> */ 0, false, X86_EFL_ZF }, 1011 { UINT16_C(0x4560), /* -> */ 1, false, 0 }, 1012 { UINT16_C(0x003f), /* -> */ 10, false, 0 }, 1013 { UINT16_C(0x0001), /* -> */ 15, false, 0 }, 1014 }; 1015 static BS3CPUINSTR2_SUBTEST_BITSCAN_T const s_aSubTestsBsr32[] = 1016 { 1017 { 0, /* -> */ 0, true, X86_EFL_ZF }, 1018 #if ARCH_BITS == 64 1019 { ~(RTCCUINTXREG)UINT32_MAX, /* -> */ 0, true, X86_EFL_ZF }, 1020 #endif 1021 { ~(RTCCUINTXREG)0, /* -> */ 31, false, 0 }, 1022 { ~(RTCCUINTXREG)1, /* -> */ 31, false, 0 }, 1023 { 1, /* -> */ 0, false, 0 }, 1024 { 2, /* -> */ 1, false, 0 }, 1025 { UINT16_C(0x8000), /* -> */ 15, false, 0 }, 1026 { UINT16_C(0x4560), /* -> */ 14, false, 0 }, 1027 { UINT32_C(0x80000000), /* -> */ 31, false, 0 }, 1028 { UINT32_C(0x45600000), /* -> */ 30, false, 0 }, 1029 }; 1030 static BS3CPUINSTR2_SUBTEST_BITSCAN_T const s_aSubTestsLzCnt32[] = 1031 { 1032 { 0, /* -> */ 32, false, X86_EFL_CF }, 1033 #if ARCH_BITS == 64 1034 { ~(RTCCUINTXREG)UINT32_MAX, /* -> */ 32, false, X86_EFL_CF }, 1035 #endif 1036 { ~(RTCCUINTXREG)0, /* -> */ 0, false, X86_EFL_ZF }, 1037 { ~(RTCCUINTXREG)1, /* -> */ 0, false, X86_EFL_ZF }, 1038 { 1, /* -> */ 31, false, 0 }, 1039 { 2, /* -> */ 30, false, 0}, 1040 { UINT16_C(0x8000), /* -> */ 16, false, 0 }, 1041 { UINT16_C(0x4560), /* -> */ 17, false, 0 }, 1042 { UINT32_C(0x80000000), /* -> */ 0, false, X86_EFL_ZF }, 1043 { UINT32_C(0x45600000), /* -> */ 1, false, 0 }, 1044 { UINT32_C(0x0000ffff), /* -> */ 16, false, 0 }, 1045 }; 1046 #if ARCH_BITS == 64 1047 static BS3CPUINSTR2_SUBTEST_BITSCAN_T const s_aSubTestsBsr64[] = 1048 { 1049 { 0, /* -> */ 0, true, X86_EFL_ZF }, 1050 { ~(RTCCUINTXREG)0, /* -> */ 63, false, 0 }, 1051 { ~(RTCCUINTXREG)1, /* -> */ 63, false, 0 }, 1052 { 1, /* -> */ 0, false, 0 }, 1053 { 2, /* -> */ 1, false, 0 }, 1054 { UINT16_C(0x8000), /* -> */ 15, false, 0 }, 1055 { UINT16_C(0x4560), /* -> */ 14, false, 0 }, 1056 { UINT32_C(0x80000000), /* -> */ 31, false, 0 }, 1057 { UINT32_C(0x45600000), /* -> */ 30, false, 0 }, 1058 { UINT64_C(0x8000000000000000), /* -> */ 63, false, 0 }, 1059 { UINT64_C(0x0045600000000000), /* -> */ 54, false, 0 }, 1060 }; 1061 static BS3CPUINSTR2_SUBTEST_BITSCAN_T const s_aSubTestsLzCnt64[] = 1062 { 1063 { 0, /* -> */ 64, false, X86_EFL_CF }, 1064 { ~(RTCCUINTXREG)0, /* -> */ 0, false, X86_EFL_ZF }, 1065 { ~(RTCCUINTXREG)1, /* -> */ 0, false, X86_EFL_ZF }, 1066 { 1, /* -> */ 63, false, 0 }, 1067 { 2, /* -> */ 62, false, 0 }, 1068 { UINT16_C(0x8000), /* -> */ 48, false, 0 }, 1069 { UINT16_C(0x4560), /* -> */ 49, false, 0 }, 1070 { UINT32_C(0x80000000), /* -> */ 32, false, 0 }, 1071 { UINT32_C(0x45600000), /* -> */ 33, false, 0 }, 1072 { UINT64_C(0x8000000000000000), /* -> */ 0, false, X86_EFL_ZF }, 1073 { UINT64_C(0x4560000000000000), /* -> */ 1, false, 0 }, 1074 { UINT64_C(0x0045600000000000), /* -> */ 9, false, 0 }, 1075 }; 1076 #endif 1077 static BS3CPUINSTR2_TEST_BITSCAN_T s_aTests[] = 1078 { 1079 { BS3_CMN_NM(bs3CpuInstr2_bsr_AX_BX_ud2), false, 3 + (ARCH_BITS != 16), 16, X86_EFL_ZF, 1080 RT_ELEMENTS(s_aSubTestsBsr16), s_aSubTestsBsr16 }, 1081 { BS3_CMN_NM(bs3CpuInstr2_bsr_AX_FSxBX_ud2), true, 4 + (ARCH_BITS != 16), 16, X86_EFL_ZF, 1082 RT_ELEMENTS(s_aSubTestsBsr16), s_aSubTestsBsr16 }, 1083 { BS3_CMN_NM(bs3CpuInstr2_bsr_EAX_EBX_ud2), false, 3 + (ARCH_BITS == 16), 32, X86_EFL_ZF, 1084 RT_ELEMENTS(s_aSubTestsBsr32), s_aSubTestsBsr32 }, 1085 { BS3_CMN_NM(bs3CpuInstr2_bsr_EAX_FSxBX_ud2), true, 4 + (ARCH_BITS == 16), 32, X86_EFL_ZF, 1086 RT_ELEMENTS(s_aSubTestsBsr32), s_aSubTestsBsr32 }, 1087 #if ARCH_BITS == 64 1088 { BS3_CMN_NM(bs3CpuInstr2_bsr_RAX_RBX_ud2), false, 4, 64, X86_EFL_ZF, 1089 RT_ELEMENTS(s_aSubTestsBsr64), s_aSubTestsBsr64 }, 1090 { BS3_CMN_NM(bs3CpuInstr2_bsr_RAX_FSxBX_ud2), true, 5, 64, X86_EFL_ZF, 1091 RT_ELEMENTS(s_aSubTestsBsr64), s_aSubTestsBsr64 }, 1092 #endif 1093 /* f2 prefixed variant: */ 1094 { BS3_CMN_NM(bs3CpuInstr2_f2_bsr_AX_BX_ud2), false, 4 + (ARCH_BITS != 16), 16, X86_EFL_ZF, 1095 RT_ELEMENTS(s_aSubTestsBsr16), s_aSubTestsBsr16 }, 1096 { BS3_CMN_NM(bs3CpuInstr2_f2_bsr_AX_FSxBX_ud2), true, 5 + (ARCH_BITS != 16), 16, X86_EFL_ZF, 1097 RT_ELEMENTS(s_aSubTestsBsr16), s_aSubTestsBsr16 }, 1098 { BS3_CMN_NM(bs3CpuInstr2_f2_bsr_EAX_EBX_ud2), false, 4 + (ARCH_BITS == 16), 32, X86_EFL_ZF, 1099 RT_ELEMENTS(s_aSubTestsBsr32), s_aSubTestsBsr32 }, 1100 { BS3_CMN_NM(bs3CpuInstr2_f2_bsr_EAX_FSxBX_ud2), true, 5 + (ARCH_BITS == 16), 32, X86_EFL_ZF, 1101 RT_ELEMENTS(s_aSubTestsBsr32), s_aSubTestsBsr32 }, 1102 #if ARCH_BITS == 64 1103 { BS3_CMN_NM(bs3CpuInstr2_f2_bsr_RAX_RBX_ud2), false, 5, 64, X86_EFL_ZF, 1104 RT_ELEMENTS(s_aSubTestsBsr64), s_aSubTestsBsr64 }, 1105 { BS3_CMN_NM(bs3CpuInstr2_f2_bsr_RAX_FSxBX_ud2), true, 6, 64, X86_EFL_ZF, 1106 RT_ELEMENTS(s_aSubTestsBsr64), s_aSubTestsBsr64 }, 1107 #endif 1108 1109 /* lzcnt: */ 1110 { BS3_CMN_NM(bs3CpuInstr2_lzcnt_AX_BX_ud2), false, 4 + (ARCH_BITS != 16), 16, X86_EFL_ZF | X86_EFL_CF, 1111 RT_ELEMENTS(s_aSubTestsLzCnt16), s_aSubTestsLzCnt16 }, 1112 { BS3_CMN_NM(bs3CpuInstr2_lzcnt_AX_FSxBX_ud2), true, 5 + (ARCH_BITS != 16), 16, X86_EFL_ZF | X86_EFL_CF, 1113 RT_ELEMENTS(s_aSubTestsLzCnt16), s_aSubTestsLzCnt16 }, 1114 { BS3_CMN_NM(bs3CpuInstr2_lzcnt_EAX_EBX_ud2), false, 4 + (ARCH_BITS == 16), 32, X86_EFL_ZF | X86_EFL_CF, 1115 RT_ELEMENTS(s_aSubTestsLzCnt32), s_aSubTestsLzCnt32 }, 1116 { BS3_CMN_NM(bs3CpuInstr2_lzcnt_EAX_FSxBX_ud2), true, 5 + (ARCH_BITS == 16), 32, X86_EFL_ZF | X86_EFL_CF, 1117 RT_ELEMENTS(s_aSubTestsLzCnt32), s_aSubTestsLzCnt32 }, 1118 #if ARCH_BITS == 64 1119 { BS3_CMN_NM(bs3CpuInstr2_lzcnt_RAX_RBX_ud2), false, 5, 64, X86_EFL_ZF | X86_EFL_CF, 1120 RT_ELEMENTS(s_aSubTestsLzCnt64), s_aSubTestsLzCnt64 }, 1121 { BS3_CMN_NM(bs3CpuInstr2_lzcnt_RAX_FSxBX_ud2), true, 6, 64, X86_EFL_ZF | X86_EFL_CF, 1122 RT_ELEMENTS(s_aSubTestsLzCnt64), s_aSubTestsLzCnt64 }, 1123 #endif 1124 /* f2 prefixed lzcnt variant (last prefix (f3) should prevail): */ 1125 { BS3_CMN_NM(bs3CpuInstr2_f2_lzcnt_AX_BX_ud2), false, 5 + (ARCH_BITS != 16), 16, X86_EFL_ZF | X86_EFL_CF, 1126 RT_ELEMENTS(s_aSubTestsLzCnt16), s_aSubTestsLzCnt16 }, 1127 { BS3_CMN_NM(bs3CpuInstr2_f2_lzcnt_AX_FSxBX_ud2), true, 6 + (ARCH_BITS != 16), 16, X86_EFL_ZF | X86_EFL_CF, 1128 RT_ELEMENTS(s_aSubTestsLzCnt16), s_aSubTestsLzCnt16 }, 1129 { BS3_CMN_NM(bs3CpuInstr2_f2_lzcnt_EAX_EBX_ud2), false, 5 + (ARCH_BITS == 16), 32, X86_EFL_ZF | X86_EFL_CF, 1130 RT_ELEMENTS(s_aSubTestsLzCnt32), s_aSubTestsLzCnt32 }, 1131 { BS3_CMN_NM(bs3CpuInstr2_f2_lzcnt_EAX_FSxBX_ud2),true, 6 + (ARCH_BITS == 16), 32, X86_EFL_ZF | X86_EFL_CF, 1132 RT_ELEMENTS(s_aSubTestsLzCnt32), s_aSubTestsLzCnt32 }, 1133 #if ARCH_BITS == 64 1134 { BS3_CMN_NM(bs3CpuInstr2_f2_lzcnt_RAX_RBX_ud2), false, 6, 64, X86_EFL_ZF | X86_EFL_CF, 1135 RT_ELEMENTS(s_aSubTestsLzCnt64), s_aSubTestsLzCnt64 }, 1136 { BS3_CMN_NM(bs3CpuInstr2_f2_lzcnt_RAX_FSxBX_ud2),true, 7, 64, X86_EFL_ZF | X86_EFL_CF, 1137 RT_ELEMENTS(s_aSubTestsLzCnt64), s_aSubTestsLzCnt64 }, 1138 #endif 1139 }; 1140 1141 uint32_t uExtFeatEcx = 0; 1142 if (g_uBs3CpuDetected & BS3CPU_F_CPUID_EXT_LEAVES) 1143 ASMCpuIdExSlow(UINT32_C(0x80000001), 0, 0, 0, NULL, NULL, &uExtFeatEcx, NULL); 1144 if (!(uExtFeatEcx & X86_CPUID_AMD_FEATURE_ECX_ABM)) 1145 { 1146 unsigned i = RT_ELEMENTS(s_aTests); 1147 while (i-- > 0) 1148 if (s_aTests[i].fEflCheck & X86_EFL_CF) 1149 { 1150 s_aTests[i].fEflCheck = X86_EFL_ZF; 1151 switch (s_aTests[i].cOpBits) 1152 { 1153 case 16: 1154 s_aTests[i].cSubTests = RT_ELEMENTS(s_aSubTestsBsr16); 1155 s_aTests[i].paSubTests = s_aSubTestsBsr16; 1156 break; 1157 case 32: 1158 s_aTests[i].cSubTests = RT_ELEMENTS(s_aSubTestsBsr32); 1159 s_aTests[i].paSubTests = s_aSubTestsBsr32; 1160 break; 1161 #if ARCH_BITS == 64 1162 case 64: 1163 s_aTests[i].cSubTests = RT_ELEMENTS(s_aSubTestsBsr64); 1164 s_aTests[i].paSubTests = s_aSubTestsBsr64; 1165 break; 1166 #endif 1167 } 1168 } 1169 Bs3TestPrintf("lzcnt not supported\n"); 1170 } 1171 1172 return bs3CpuInstr2_BitScan(bMode, s_aTests, RT_ELEMENTS(s_aTests)); 1173 } 1174 1175 1176 /** 1177 * RORX 1178 */ 636 1179 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_rorx)(uint8_t bMode) 637 1180 { -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2-template.mac
r95305 r95306 82 82 jmp .again 83 83 BS3_PROC_END_CMN bs3CpuInstr2_idiv_xBX_ud2 84 85 86 ; 87 ; BSF / BSR / TZCNT / LZCNT 88 ; 89 %ifndef EMIT_BITSCAN_DEFINED 90 %define EMIT_BITSCAN_DEFINED 91 %macro EMIT_BITSCAN 3 92 BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _AX_BX_ud2, BS3_PBC_NEAR 93 %2 94 %1 ax, bx 95 .again: 96 ud2 97 jmp .again 98 BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _AX_BX_ud2 99 100 BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _AX_FSxBX_ud2, BS3_PBC_NEAR 101 %2 102 %1 ax, [fs:xBX] 103 .again: 104 ud2 105 jmp .again 106 BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _AX_FSxBX_ud2 107 108 BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_EBX_ud2, BS3_PBC_NEAR 109 %2 110 %1 eax, ebx 111 .again: 112 ud2 113 jmp .again 114 BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_EBX_ud2 115 116 BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_FSxBX_ud2, BS3_PBC_NEAR 117 %2 118 %1 eax, [fs:xBX] 119 .again: 120 ud2 121 jmp .again 122 BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _EAX_FSxBX_ud2 123 124 %if TMPL_BITS == 64 125 BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_RBX_ud2, BS3_PBC_NEAR 126 %2 127 %1 rax, rbx 128 .again: 129 ud2 130 jmp .again 131 BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_RBX_ud2 132 133 BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_FSxBX_ud2, BS3_PBC_NEAR 134 %2 135 %1 rax, [fs:xBX] 136 .again: 137 ud2 138 jmp .again 139 BS3_PROC_END_CMN bs3CpuInstr2_ %+ %3 %+ _RAX_FSxBX_ud2 140 %endif 141 %endmacro 142 %endif 143 144 EMIT_BITSCAN bsf, .ignored:, bsf 145 EMIT_BITSCAN bsr, .ignored:, bsr 146 EMIT_BITSCAN tzcnt, .ignored:, tzcnt 147 EMIT_BITSCAN lzcnt, .ignored:, lzcnt 148 EMIT_BITSCAN bsf, db 0f2h, f2_bsf 149 EMIT_BITSCAN bsr, db 0f2h, f2_bsr 150 EMIT_BITSCAN tzcnt, db 0f2h, f2_tzcnt 151 EMIT_BITSCAN lzcnt, db 0f2h, f2_lzcnt 152 84 153 85 154 ; -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2.c
r95305 r95306 39 39 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_div); 40 40 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_idiv); 41 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_bsf_tzcnt); 42 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_bsr_lzcnt); 41 43 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_rorx); 42 44 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_andn); … … 62 64 BS3TESTMODEENTRY_CMN("div", bs3CpuInstr2_div), 63 65 BS3TESTMODEENTRY_CMN("idiv", bs3CpuInstr2_idiv), 66 #endif 67 #if 1 /* BSF/BSR (386+) & TZCNT/LZCNT (BMI1,ABM) */ 68 BS3TESTMODEENTRY_CMN("bsf/tzcnt", bs3CpuInstr2_bsf_tzcnt), 69 BS3TESTMODEENTRY_CMN("bsr/lzcnt", bs3CpuInstr2_bsr_lzcnt), 64 70 #endif 65 71 #if 1 /* BMI1 & BMI2 */
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