Changeset 95340 in vbox for trunk/src/VBox/ValidationKit
- Timestamp:
- Jun 22, 2022 10:36:40 AM (3 years ago)
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 3 edited
-
bs3-cpu-instr-2-template.c (modified) (4 diffs)
-
bs3-cpu-instr-2-template.mac (modified) (1 diff)
-
bs3-cpu-instr-2.c (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2-template.c
r95306 r95340 154 154 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_shrx_EAX_EBX_ECX_icebp); 155 155 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_shrx_EAX_FSxBX_ECX_icebp); 156 157 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_blsr_RAX_RBX_icebp); 158 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_blsr_RAX_FSxBX_icebp); 159 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_blsr_EAX_EBX_icebp); 160 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_blsr_EAX_FSxBX_icebp); 161 162 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_blsmsk_RAX_RBX_icebp); 163 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_blsmsk_RAX_FSxBX_icebp); 164 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_blsmsk_EAX_EBX_icebp); 165 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_blsmsk_EAX_FSxBX_icebp); 166 167 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_blsi_RAX_RBX_icebp); 168 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_blsi_RAX_FSxBX_icebp); 169 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_blsi_EAX_EBX_icebp); 170 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_blsi_EAX_FSxBX_icebp); 156 171 157 172 # if ARCH_BITS == 64 … … 1573 1588 Bs3TestFailedF("Expected RCX = %#06RX64, got %#06RX64", Ctx.rcx.u, TrapFrame.Ctx.rcx.u); 1574 1589 if (TrapFrame.Ctx.rbx.u != Ctx.rbx.u) 1575 Bs3TestFailedF("Expected RBX = %#06RX64, got %#06RX64 (dst)", Ctx.rbx.u, TrapFrame.Ctx.rbx.u);1590 Bs3TestFailedF("Expected RBX = %#06RX64, got %#06RX64", Ctx.rbx.u, TrapFrame.Ctx.rbx.u); 1576 1591 if ( (TrapFrame.Ctx.rflags.u16 & fEflCheck) 1577 1592 != ((fOkay ? paTests[i].paSubTests[k].fEflOut : Ctx.rflags.u16) & fEflCheck)) … … 1586 1601 1587 1602 if (TrapFrame.Ctx.rdx.u != Ctx.rdx.u) 1588 Bs3TestFailedF("Expected RDX = %#06RX64, got %#06RX64 (src)", Ctx.rdx.u, TrapFrame.Ctx.rdx.u);1603 Bs3TestFailedF("Expected RDX = %#06RX64, got %#06RX64", Ctx.rdx.u, TrapFrame.Ctx.rdx.u); 1589 1604 if (TrapFrame.Ctx.rsp.u != Ctx.rsp.u) 1590 1605 Bs3TestFailedF("Expected RSP = %#06RX64, got %#06RX64", Ctx.rsp.u, TrapFrame.Ctx.rsp.u); … … 1743 1758 return bs3CpuInstr2_Common_Gy_Ey_By(bMode, s_aTests, RT_ELEMENTS(s_aTests), X86_CPUID_STEXT_FEATURE_EBX_BMI1, 1744 1759 0, 0); 1760 } 1761 1762 1763 /* 1764 * For testing BLSR, BLSMSK, and BLSI. 1765 */ 1766 typedef struct BS3CPUINSTR2_SUBTEST_By_Ey_T 1767 { 1768 RTCCUINTXREG uSrc; 1769 RTCCUINTXREG uDst; 1770 uint16_t fEflOut; 1771 } BS3CPUINSTR2_SUBTEST_By_Ey_T; 1772 1773 typedef struct BS3CPUINSTR2_TEST_By_Ey_T 1774 { 1775 FPFNBS3FAR pfnWorker; 1776 bool fMemSrc; 1777 uint8_t cbInstr; 1778 uint8_t cSubTests; 1779 BS3CPUINSTR2_SUBTEST_By_Ey_T const *paSubTests; 1780 } BS3CPUINSTR2_TEST_By_Ey_T; 1781 1782 static uint8_t bs3CpuInstr2_Common_By_Ey(uint8_t bMode, BS3CPUINSTR2_TEST_By_Ey_T const *paTests, unsigned cTests, 1783 uint32_t fStdExtFeatEbx, uint16_t fEflCheck, uint16_t fEflIgnore) 1784 { 1785 BS3REGCTX Ctx; 1786 BS3TRAPFRAME TrapFrame; 1787 unsigned i, j, k; 1788 uint32_t uStdExtFeatEbx = 0; 1789 bool fSupportsInstr; 1790 1791 fEflCheck &= ~fEflIgnore; 1792 1793 if (g_uBs3CpuDetected & BS3CPU_F_CPUID) 1794 ASMCpuIdExSlow(7, 0, 0, 0, NULL, &uStdExtFeatEbx, NULL, NULL); 1795 fSupportsInstr = RT_BOOL(uStdExtFeatEbx & fStdExtFeatEbx); 1796 1797 /* Ensure the structures are allocated before we sample the stack pointer. */ 1798 Bs3MemSet(&Ctx, 0, sizeof(Ctx)); 1799 Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); 1800 1801 /* 1802 * Create test context. 1803 */ 1804 Bs3RegCtxSaveEx(&Ctx, bMode, 512); 1805 1806 /* 1807 * Do the tests twice, first with all flags set, then once again with 1808 * flags cleared. The flags are not supposed to be touched at all. 1809 */ 1810 Ctx.rflags.u16 |= X86_EFL_STATUS_BITS; 1811 for (j = 0; j < 2; j++) 1812 { 1813 for (i = 0; i < cTests; i++) 1814 { 1815 for (k = 0; k < paTests[i].cSubTests; k++) 1816 { 1817 bool const fOkay = !BS3_MODE_IS_RM_OR_V86(bMode) && fSupportsInstr; 1818 uint8_t const bExpectXcpt = fOkay ? X86_XCPT_DB : X86_XCPT_UD; 1819 uint64_t uExpectRax, uExpectRip; 1820 RTCCUINTXREG uMemSrc, uMemSrcExpect; 1821 1822 Ctx.rax.uCcXReg = ~paTests[i].paSubTests[k].uSrc ^ 0x593e7591; 1823 if (!paTests[i].fMemSrc) 1824 { 1825 Ctx.rbx.uCcXReg = paTests[i].paSubTests[k].uSrc; 1826 uMemSrcExpect = uMemSrc = ~paTests[i].paSubTests[k].uSrc; 1827 } 1828 else 1829 { 1830 uMemSrcExpect = uMemSrc = paTests[i].paSubTests[k].uSrc; 1831 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, &uMemSrc); 1832 } 1833 Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[i].pfnWorker); 1834 uExpectRax = fOkay ? paTests[i].paSubTests[k].uDst : Ctx.rax.u; 1835 uExpectRip = Ctx.rip.u + (fOkay ? paTests[i].cbInstr + 1 : 0); 1836 Bs3TrapSetJmpAndRestore(&Ctx, &TrapFrame); 1837 1838 if ( TrapFrame.bXcpt != bExpectXcpt 1839 || TrapFrame.Ctx.rip.u != uExpectRip 1840 || TrapFrame.Ctx.rbx.u != Ctx.rbx.u 1841 || TrapFrame.Ctx.rax.u != uExpectRax 1842 /* check that nothing else really changed: */ 1843 || (TrapFrame.Ctx.rflags.u16 & fEflCheck) 1844 != ((fOkay ? paTests[i].paSubTests[k].fEflOut : Ctx.rflags.u16) & fEflCheck) 1845 || (TrapFrame.Ctx.rflags.u16 & ~(fEflCheck | fEflIgnore) & X86_EFL_STATUS_BITS) 1846 != (Ctx.rflags.u16 & ~(fEflCheck | fEflIgnore) & X86_EFL_STATUS_BITS) 1847 || TrapFrame.Ctx.rcx.u != Ctx.rcx.u 1848 || TrapFrame.Ctx.rdx.u != Ctx.rdx.u 1849 || TrapFrame.Ctx.rsp.u != Ctx.rsp.u 1850 || TrapFrame.Ctx.rbp.u != Ctx.rbp.u 1851 || TrapFrame.Ctx.rsi.u != Ctx.rsi.u 1852 || TrapFrame.Ctx.rdi.u != Ctx.rdi.u 1853 || uMemSrc != uMemSrcExpect 1854 ) 1855 { 1856 Bs3TestFailedF("test #%i/%i failed: input %#" RTCCUINTXREG_XFMT, 1857 i, k, paTests[i].paSubTests[k].uSrc); 1858 if (TrapFrame.bXcpt != bExpectXcpt) 1859 Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bExpectXcpt, TrapFrame.bXcpt); 1860 if (TrapFrame.Ctx.rip.u != uExpectRip) 1861 Bs3TestFailedF("Expected RIP = %#06RX64, got %#06RX64", uExpectRip, TrapFrame.Ctx.rip.u); 1862 if (TrapFrame.Ctx.rax.u != uExpectRax) 1863 Bs3TestFailedF("Expected RAX = %#06RX64, got %#06RX64", uExpectRax, TrapFrame.Ctx.rax.u); 1864 if (TrapFrame.Ctx.rbx.u != Ctx.rbx.u) 1865 Bs3TestFailedF("Expected RBX = %#06RX64, got %#06RX64 (dst)", Ctx.rbx.u, TrapFrame.Ctx.rbx.u); 1866 if ( (TrapFrame.Ctx.rflags.u16 & fEflCheck) 1867 != ((fOkay ? paTests[i].paSubTests[k].fEflOut : Ctx.rflags.u16) & fEflCheck)) 1868 Bs3TestFailedF("Expected EFLAGS = %#06RX64, got %#06RX64 (output)", 1869 (fOkay ? paTests[i].paSubTests[k].fEflOut : Ctx.rflags.u16) & fEflCheck, 1870 TrapFrame.Ctx.rflags.u16 & fEflCheck); 1871 if ( (TrapFrame.Ctx.rflags.u16 & ~(fEflCheck | fEflIgnore) & X86_EFL_STATUS_BITS) 1872 != (Ctx.rflags.u16 & ~(fEflCheck | fEflIgnore) & X86_EFL_STATUS_BITS)) 1873 Bs3TestFailedF("Expected EFLAGS = %#06RX64, got %#06RX64 (immutable)", 1874 Ctx.rflags.u16 & ~(fEflCheck | fEflIgnore) & X86_EFL_STATUS_BITS, 1875 TrapFrame.Ctx.rflags.u16 & ~(fEflCheck | fEflIgnore) & X86_EFL_STATUS_BITS); 1876 1877 if (TrapFrame.Ctx.rcx.u != Ctx.rcx.u) 1878 Bs3TestFailedF("Expected RCX = %#06RX64, got %#06RX64", Ctx.rcx.u, TrapFrame.Ctx.rcx.u); 1879 if (TrapFrame.Ctx.rdx.u != Ctx.rdx.u) 1880 Bs3TestFailedF("Expected RDX = %#06RX64, got %#06RX64", Ctx.rdx.u, TrapFrame.Ctx.rdx.u); 1881 if (TrapFrame.Ctx.rsp.u != Ctx.rsp.u) 1882 Bs3TestFailedF("Expected RSP = %#06RX64, got %#06RX64", Ctx.rsp.u, TrapFrame.Ctx.rsp.u); 1883 if (TrapFrame.Ctx.rbp.u != Ctx.rbp.u) 1884 Bs3TestFailedF("Expected RBP = %#06RX64, got %#06RX64", Ctx.rbp.u, TrapFrame.Ctx.rbp.u); 1885 if (TrapFrame.Ctx.rsi.u != Ctx.rsi.u) 1886 Bs3TestFailedF("Expected RSI = %#06RX64, got %#06RX64", Ctx.rsi.u, TrapFrame.Ctx.rsi.u); 1887 if (TrapFrame.Ctx.rdi.u != Ctx.rdi.u) 1888 Bs3TestFailedF("Expected RDI = %#06RX64, got %#06RX64", Ctx.rdi.u, TrapFrame.Ctx.rdi.u); 1889 if (uMemSrc != uMemSrcExpect) 1890 Bs3TestFailedF("Expected uMemSrc = %#06RX64, got %#06RX64", (uint64_t)uMemSrcExpect, (uint64_t)uMemSrc); 1891 } 1892 } 1893 } 1894 Ctx.rflags.u16 &= ~X86_EFL_STATUS_BITS; 1895 } 1896 1897 return 0; 1898 } 1899 1900 1901 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_blsr)(uint8_t bMode) 1902 { 1903 /* 64 bits register width (32 bits in 32- and 16-bit modes): */ 1904 static BS3CPUINSTR2_SUBTEST_By_Ey_T const s_aSubTests64[] = 1905 { 1906 { 0, /* -> */ 0, X86_EFL_ZF | X86_EFL_CF }, 1907 { 1, /* -> */ 0, X86_EFL_ZF }, 1908 { 2, /* -> */ 0, X86_EFL_ZF }, 1909 { 3, /* -> */ 2, 0 }, 1910 { 5, /* -> */ 4, 0 }, 1911 { 6, /* -> */ 4, 0 }, 1912 { 7, /* -> */ 6, 0 }, 1913 { 9, /* -> */ 8, 0 }, 1914 { 10, /* -> */ 8, 0 }, 1915 { ~(RTCCUINTXREG)1, /* -> */ ~(RTCCUINTXREG)3, X86_EFL_SF }, 1916 { (RTCCUINTXREG)3 << (RTCCINTXREG_BITS - 2), /* -> */ (RTCCUINTXREG)2 << (RTCCINTXREG_BITS - 2), X86_EFL_SF }, 1917 }; 1918 1919 /* 32-bit register width */ 1920 static BS3CPUINSTR2_SUBTEST_By_Ey_T const s_aSubTests32[] = 1921 { 1922 { 0, /* -> */ 0, X86_EFL_ZF | X86_EFL_CF }, 1923 { 1, /* -> */ 0, X86_EFL_ZF }, 1924 { ~(RTCCUINTXREG)1, /* -> */ UINT32_C(0xfffffffc), X86_EFL_SF }, 1925 { ~(RTCCUINTXREG)0 << 30, /* -> */ UINT32_C(0x80000000), X86_EFL_SF }, 1926 }; 1927 1928 static BS3CPUINSTR2_TEST_By_Ey_T const s_aTests[] = 1929 { 1930 { BS3_CMN_NM(bs3CpuInstr2_blsr_RAX_RBX_icebp), false, 5, RT_ELEMENTS(s_aSubTests64), s_aSubTests64 }, 1931 { BS3_CMN_NM(bs3CpuInstr2_blsr_RAX_FSxBX_icebp), true, 6, RT_ELEMENTS(s_aSubTests64), s_aSubTests64 }, 1932 { BS3_CMN_NM(bs3CpuInstr2_blsr_EAX_EBX_icebp), false, 5, RT_ELEMENTS(s_aSubTests32), s_aSubTests32 }, 1933 { BS3_CMN_NM(bs3CpuInstr2_blsr_EAX_FSxBX_icebp), true, 6, RT_ELEMENTS(s_aSubTests32), s_aSubTests32 }, 1934 }; 1935 return bs3CpuInstr2_Common_By_Ey(bMode, s_aTests, RT_ELEMENTS(s_aTests), X86_CPUID_STEXT_FEATURE_EBX_BMI1, 1936 X86_EFL_STATUS_BITS, 0); 1937 } 1938 1939 1940 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_blsmsk)(uint8_t bMode) 1941 { 1942 /* 64 bits register width (32 bits in 32- and 16-bit modes): */ 1943 static BS3CPUINSTR2_SUBTEST_By_Ey_T const s_aSubTests64[] = 1944 { 1945 { 0, /* -> */ ~(RTCCUINTXREG)0, X86_EFL_CF | X86_EFL_SF }, 1946 { 1, /* -> */ 1, 0 }, 1947 { ~(RTCCUINTXREG)1, /* -> */ 3, 0 }, 1948 { (RTCCUINTXREG)3 << (RTCCINTXREG_BITS - 2), /* -> */ ~((RTCCUINTXREG)2 << (RTCCINTXREG_BITS - 2)), 0 }, 1949 }; 1950 1951 /* 32-bit register width */ 1952 static BS3CPUINSTR2_SUBTEST_By_Ey_T const s_aSubTests32[] = 1953 { 1954 { 0, /* -> */ UINT32_MAX, X86_EFL_CF | X86_EFL_SF }, 1955 { 1, /* -> */ 1, 0 }, 1956 { ~(RTCCUINTXREG)1, /* -> */ 3, 0 }, 1957 { ~(RTCCUINTXREG)0 << 30, /* -> */ UINT32_C(0x7fffffff), 0}, 1958 }; 1959 1960 static BS3CPUINSTR2_TEST_By_Ey_T const s_aTests[] = 1961 { 1962 { BS3_CMN_NM(bs3CpuInstr2_blsmsk_RAX_RBX_icebp), false, 5, RT_ELEMENTS(s_aSubTests64), s_aSubTests64 }, 1963 { BS3_CMN_NM(bs3CpuInstr2_blsmsk_RAX_FSxBX_icebp), true, 6, RT_ELEMENTS(s_aSubTests64), s_aSubTests64 }, 1964 { BS3_CMN_NM(bs3CpuInstr2_blsmsk_EAX_EBX_icebp), false, 5, RT_ELEMENTS(s_aSubTests32), s_aSubTests32 }, 1965 { BS3_CMN_NM(bs3CpuInstr2_blsmsk_EAX_FSxBX_icebp), true, 6, RT_ELEMENTS(s_aSubTests32), s_aSubTests32 }, 1966 }; 1967 return bs3CpuInstr2_Common_By_Ey(bMode, s_aTests, RT_ELEMENTS(s_aTests), X86_CPUID_STEXT_FEATURE_EBX_BMI1, 1968 X86_EFL_STATUS_BITS, 0); 1969 } 1970 1971 1972 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_blsi)(uint8_t bMode) 1973 { 1974 /* 64 bits register width (32 bits in 32- and 16-bit modes): */ 1975 static BS3CPUINSTR2_SUBTEST_By_Ey_T const s_aSubTests64[] = 1976 { 1977 { 0, /* -> */ 0, X86_EFL_ZF }, 1978 { 1, /* -> */ 1, X86_EFL_CF }, 1979 { ~(RTCCUINTXREG)1, /* -> */ 2, X86_EFL_CF }, 1980 { (RTCCUINTXREG)3 << (RTCCINTXREG_BITS - 2), /* -> */ (RTCCUINTXREG)1 << (RTCCINTXREG_BITS - 2), X86_EFL_CF }, 1981 }; 1982 1983 /* 32-bit register width */ 1984 static BS3CPUINSTR2_SUBTEST_By_Ey_T const s_aSubTests32[] = 1985 { 1986 { 0, /* -> */ 0, X86_EFL_ZF }, 1987 { 1, /* -> */ 1, X86_EFL_CF }, 1988 { ~(RTCCUINTXREG)1, /* -> */ 2, X86_EFL_CF }, 1989 { ~(RTCCUINTXREG)0 << 30, /* -> */ UINT32_C(0x40000000), X86_EFL_CF }, 1990 }; 1991 1992 static BS3CPUINSTR2_TEST_By_Ey_T const s_aTests[] = 1993 { 1994 { BS3_CMN_NM(bs3CpuInstr2_blsi_RAX_RBX_icebp), false, 5, RT_ELEMENTS(s_aSubTests64), s_aSubTests64 }, 1995 { BS3_CMN_NM(bs3CpuInstr2_blsi_RAX_FSxBX_icebp), true, 6, RT_ELEMENTS(s_aSubTests64), s_aSubTests64 }, 1996 { BS3_CMN_NM(bs3CpuInstr2_blsi_EAX_EBX_icebp), false, 5, RT_ELEMENTS(s_aSubTests32), s_aSubTests32 }, 1997 { BS3_CMN_NM(bs3CpuInstr2_blsi_EAX_FSxBX_icebp), true, 6, RT_ELEMENTS(s_aSubTests32), s_aSubTests32 }, 1998 }; 1999 return bs3CpuInstr2_Common_By_Ey(bMode, s_aTests, RT_ELEMENTS(s_aTests), X86_CPUID_STEXT_FEATURE_EBX_BMI1, 2000 X86_EFL_STATUS_BITS, 0); 1745 2001 } 1746 2002 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2-template.mac
r95306 r95340 323 323 324 324 ; 325 ; BLSR / BLSMSK / BLSI 326 ; These are encoded in the exact same way, only the /r differs (%2). 327 ; 328 %ifndef BLSR_BLSMSK_BLSI_DEFINED 329 %define BLSR_BLSMSK_BLSI_DEFINED 330 %macro BLSR_BLSMSK_BLSI 2 331 332 BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_icebp, BS3_PBC_NEAR 333 %if TMPL_BITS == 64 334 %1 rax, rbx ; BLSR=C4E2F8F3CB 335 %else 336 db 0C4h,0E2h,0F8h,0F3h,0C3h | (%2 << 3) ; 32-bit & 16-bit ignores VEX.W=1 (10980xe) 337 %endif 338 .again: 339 icebp 340 jmp .again 341 BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_RBX_icebp 342 343 BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_icebp, BS3_PBC_NEAR 344 %1 eax, ebx 345 .again: 346 icebp 347 jmp .again 348 BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_EBX_icebp 349 350 BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_icebp, BS3_PBC_NEAR 351 %if TMPL_BITS == 64 352 %1 rax, [fs:rbx] ; BSLR=64C4E2F8F30B 353 %elif TMPL_BITS == 32 354 db 064h,0C4h,0E2h,0F8h,0F3h,003h | (%2 << 3) 355 %else 356 db 064h,0C4h,0E2h,0F8h,0F3h,007h | (%2 << 3) 357 %endif 358 .again: 359 icebp 360 jmp .again 361 BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _RAX_FSxBX_icebp 362 363 BS3_PROC_BEGIN_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_icebp, BS3_PBC_NEAR 364 %1 eax, [fs:xBX] 365 .again: 366 icebp 367 jmp .again 368 BS3_PROC_END_CMN bs3CpuInstr2_ %+ %1 %+ _EAX_FSxBX_icebp 369 370 %endmacro 371 %endif 372 373 BLSR_BLSMSK_BLSI blsr, 1 374 BLSR_BLSMSK_BLSI blsmsk, 2 375 BLSR_BLSMSK_BLSI blsi, 3 376 377 ; 325 378 ; 326 379 ; -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2.c
r95306 r95340 41 41 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_bsf_tzcnt); 42 42 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_bsr_lzcnt); 43 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_rorx);44 43 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_andn); 45 44 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_bextr); 45 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_blsr); 46 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_blsmsk); 47 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_blsi); 48 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_rorx); 46 49 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_shlx); 47 50 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_sarx); … … 69 72 BS3TESTMODEENTRY_CMN("bsr/lzcnt", bs3CpuInstr2_bsr_lzcnt), 70 73 #endif 71 #if 1 /* BMI1 & BMI2 */ 74 #if 1 /* BMI1 */ 75 BS3TESTMODEENTRY_CMN("andn", bs3CpuInstr2_andn), 76 BS3TESTMODEENTRY_CMN("bextr", bs3CpuInstr2_bextr), 77 BS3TESTMODEENTRY_CMN("blsr", bs3CpuInstr2_blsr), 78 BS3TESTMODEENTRY_CMN("blsmsk", bs3CpuInstr2_blsmsk), 79 BS3TESTMODEENTRY_CMN("blsi", bs3CpuInstr2_blsi), 80 #endif 81 #if 1 /* BMI2 */ 72 82 BS3TESTMODEENTRY_CMN("rorx", bs3CpuInstr2_rorx), 73 BS3TESTMODEENTRY_CMN("andn", bs3CpuInstr2_andn),74 BS3TESTMODEENTRY_CMN("bextr", bs3CpuInstr2_bextr),75 83 BS3TESTMODEENTRY_CMN("shlx", bs3CpuInstr2_shlx), 76 84 BS3TESTMODEENTRY_CMN("sarx", bs3CpuInstr2_sarx),
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