Changeset 95346 in vbox for trunk/src/VBox/ValidationKit
- Timestamp:
- Jun 22, 2022 8:50:05 PM (3 years ago)
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 3 edited
-
bs3-cpu-instr-2-template.c (modified) (2 diffs)
-
bs3-cpu-instr-2-template.mac (modified) (1 diff)
-
bs3-cpu-instr-2.c (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2-template.c
r95342 r95346 184 184 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_blsi_EAX_EBX_icebp); 185 185 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_blsi_EAX_FSxBX_icebp); 186 187 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_mulx_RAX_RCX_RBX_RDX_icebp); 188 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_mulx_RCX_RCX_RBX_RDX_icebp); 189 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_mulx_RAX_RCX_FSxBX_RDX_icebp); 190 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_mulx_EAX_ECX_EBX_EDX_icebp); 191 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_mulx_ECX_ECX_EBX_EDX_icebp); 192 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_mulx_EAX_ECX_FSxBX_EDX_icebp); 186 193 187 194 # if ARCH_BITS == 64 … … 2141 2148 2142 2149 2150 /* 2151 * MULX (BMI2) - destination registers (/r & vvvv) = r/m * rDX 2152 */ 2153 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_mulx)(uint8_t bMode) 2154 { 2155 static const struct 2156 { 2157 FPFNBS3FAR pfnWorker; 2158 bool fMemSrc; 2159 bool fSameDst; 2160 uint8_t cbInstr; 2161 RTCCUINTXREG uSrc1; 2162 RTCCUINTXREG uSrc2; 2163 RTCCUINTXREG uDst1; 2164 RTCCUINTXREG uDst2; 2165 } s_aTests[] = 2166 { 2167 /* 64 bits register width (32 bits in 32- and 16-bit modes): */ 2168 { BS3_CMN_NM(bs3CpuInstr2_mulx_RAX_RCX_RBX_RDX_icebp), false, false, 5, // #0 2169 0, 0, /* -> */ 0, 0 }, 2170 { BS3_CMN_NM(bs3CpuInstr2_mulx_RAX_RCX_RBX_RDX_icebp), false, false, 5, // #1 2171 ~(RTCCUINTXREG)0, ~(RTCCUINTXREG)0, /* -> */ ~(RTCCUINTXREG)1, 1 }, 2172 { BS3_CMN_NM(bs3CpuInstr2_mulx_RCX_RCX_RBX_RDX_icebp), false, true, 5, // #2 2173 ~(RTCCUINTXREG)0, ~(RTCCUINTXREG)0, /* -> */ ~(RTCCUINTXREG)1, ~(RTCCUINTXREG)1 }, 2174 { BS3_CMN_NM(bs3CpuInstr2_mulx_RAX_RCX_RBX_RDX_icebp), false, false, 5, // #3 2175 2, 2, /* -> */ 0, 4 }, 2176 { BS3_CMN_NM(bs3CpuInstr2_mulx_RAX_RCX_RBX_RDX_icebp), false, false, 5, // #4 2177 ~(RTCCUINTXREG)0, 42, /* -> */ 0x29, ~(RTCCUINTXREG)41 }, 2178 2179 { BS3_CMN_NM(bs3CpuInstr2_mulx_RAX_RCX_FSxBX_RDX_icebp), true, false, 6, // #5 2180 0, 0, /* -> */ 0, 0 }, 2181 { BS3_CMN_NM(bs3CpuInstr2_mulx_RAX_RCX_FSxBX_RDX_icebp), true, false, 6, // #6 2182 ~(RTCCUINTXREG)0, ~(RTCCUINTXREG)0, /* -> */ ~(RTCCUINTXREG)1, 1 }, 2183 { BS3_CMN_NM(bs3CpuInstr2_mulx_RAX_RCX_FSxBX_RDX_icebp), true, false, 6, // #7 2184 ~(RTCCUINTXREG)0, 42, /* -> */ 0x29, ~(RTCCUINTXREG)41 }, 2185 2186 /* 32-bit register width */ 2187 { BS3_CMN_NM(bs3CpuInstr2_mulx_EAX_ECX_EBX_EDX_icebp), false, false, 5, // #8 2188 0, 0, /* -> */ 0, 0 }, 2189 { BS3_CMN_NM(bs3CpuInstr2_mulx_EAX_ECX_EBX_EDX_icebp), false, false, 5, // #9 2190 ~(RTCCUINTXREG)0, ~(RTCCUINTXREG)0, /* -> */ ~(uint32_t)1, 1 }, 2191 { BS3_CMN_NM(bs3CpuInstr2_mulx_ECX_ECX_EBX_EDX_icebp), false, true, 5, // #10 2192 ~(RTCCUINTXREG)0, ~(RTCCUINTXREG)0, /* -> */ ~(uint32_t)1, ~(uint32_t)1 }, 2193 { BS3_CMN_NM(bs3CpuInstr2_mulx_EAX_ECX_EBX_EDX_icebp), false, false, 5, // #11 2194 2, 2, /* -> */ 0, 4 }, 2195 { BS3_CMN_NM(bs3CpuInstr2_mulx_EAX_ECX_EBX_EDX_icebp), false, false, 5, // #12 2196 ~(RTCCUINTXREG)0, 42, /* -> */ 0x29, ~(uint32_t)41 }, 2197 2198 { BS3_CMN_NM(bs3CpuInstr2_mulx_EAX_ECX_FSxBX_EDX_icebp), true, false, 6, // #13 2199 0, 0, /* -> */ 0, 0 }, 2200 { BS3_CMN_NM(bs3CpuInstr2_mulx_EAX_ECX_FSxBX_EDX_icebp), true, false, 6, // #14 2201 ~(RTCCUINTXREG)0, ~(RTCCUINTXREG)0, /* -> */ ~(uint32_t)1, 1 }, 2202 { BS3_CMN_NM(bs3CpuInstr2_mulx_EAX_ECX_FSxBX_EDX_icebp), true, false, 6, // #15 2203 ~(RTCCUINTXREG)0, 42, /* -> */ 0x29, ~(uint32_t)41 }, 2204 }; 2205 2206 BS3REGCTX Ctx; 2207 BS3TRAPFRAME TrapFrame; 2208 unsigned i, j; 2209 uint32_t uStdExtFeatEbx = 0; 2210 bool fSupportsAndN; 2211 2212 if (g_uBs3CpuDetected & BS3CPU_F_CPUID) 2213 ASMCpuIdExSlow(7, 0, 0, 0, NULL, &uStdExtFeatEbx, NULL, NULL); 2214 fSupportsAndN = RT_BOOL(uStdExtFeatEbx & X86_CPUID_STEXT_FEATURE_EBX_BMI2); 2215 2216 /* Ensure the structures are allocated before we sample the stack pointer. */ 2217 Bs3MemSet(&Ctx, 0, sizeof(Ctx)); 2218 Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); 2219 2220 /* 2221 * Create test context. 2222 */ 2223 Bs3RegCtxSaveEx(&Ctx, bMode, 512); 2224 2225 /* 2226 * Do the tests twice, first with all flags set, then once again with 2227 * flags cleared. The flags are not supposed to be touched at all. 2228 */ 2229 Ctx.rflags.u16 |= X86_EFL_STATUS_BITS; 2230 for (j = 0; j < 2; j++) 2231 { 2232 for (i = 0; i < RT_ELEMENTS(s_aTests); i++) 2233 { 2234 bool const fOkay = !BS3_MODE_IS_RM_OR_V86(bMode) && fSupportsAndN; 2235 uint8_t const bExpectXcpt = fOkay ? X86_XCPT_DB : X86_XCPT_UD; 2236 uint64_t uExpectRax, uExpectRcx, uExpectRip; 2237 RTCCUINTXREG uMemSrc1, uMemSrc1Expect; 2238 2239 Ctx.rax.uCcXReg = RTCCUINTXREG_MAX * 1019; 2240 Ctx.rcx.uCcXReg = RTCCUINTXREG_MAX * 4095; 2241 Ctx.rdx.uCcXReg = s_aTests[i].uSrc2; 2242 if (!s_aTests[i].fMemSrc) 2243 { 2244 Ctx.rbx.uCcXReg = s_aTests[i].uSrc1; 2245 uMemSrc1Expect = uMemSrc1 = ~s_aTests[i].uSrc1; 2246 } 2247 else 2248 { 2249 uMemSrc1Expect = uMemSrc1 = s_aTests[i].uSrc1; 2250 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, &uMemSrc1); 2251 } 2252 Bs3RegCtxSetRipCsFromCurPtr(&Ctx, s_aTests[i].pfnWorker); 2253 uExpectRax = fOkay && !s_aTests[i].fSameDst ? s_aTests[i].uDst1 : Ctx.rax.u; 2254 uExpectRcx = fOkay ? s_aTests[i].uDst2 : Ctx.rcx.u; 2255 uExpectRip = Ctx.rip.u + (fOkay ? s_aTests[i].cbInstr + 1 : 0); 2256 Bs3TrapSetJmpAndRestore(&Ctx, &TrapFrame); 2257 2258 if ( TrapFrame.bXcpt != bExpectXcpt 2259 || TrapFrame.Ctx.rip.u != uExpectRip 2260 || TrapFrame.Ctx.rbx.u != Ctx.rbx.u 2261 || TrapFrame.Ctx.rdx.u != Ctx.rdx.u 2262 || TrapFrame.Ctx.rax.u != uExpectRax 2263 || TrapFrame.Ctx.rcx.u != uExpectRcx 2264 /* check that nothing else really changed: */ 2265 || (TrapFrame.Ctx.rflags.u16 & X86_EFL_STATUS_BITS) != (Ctx.rflags.u16 & X86_EFL_STATUS_BITS) 2266 || TrapFrame.Ctx.rsp.u != Ctx.rsp.u 2267 || TrapFrame.Ctx.rbp.u != Ctx.rbp.u 2268 || TrapFrame.Ctx.rsi.u != Ctx.rsi.u 2269 || TrapFrame.Ctx.rdi.u != Ctx.rdi.u 2270 || uMemSrc1 != uMemSrc1Expect 2271 ) 2272 { 2273 Bs3TestFailedF("test #%i failed: input %#" RTCCUINTXREG_XFMT ", %#" RTCCUINTXREG_XFMT, i, s_aTests[i].uSrc1, s_aTests[i].uSrc2); 2274 if (TrapFrame.bXcpt != bExpectXcpt) 2275 Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bExpectXcpt, TrapFrame.bXcpt); 2276 if (TrapFrame.Ctx.rip.u != uExpectRip) 2277 Bs3TestFailedF("Expected RIP = %#06RX64, got %#06RX64", uExpectRip, TrapFrame.Ctx.rip.u); 2278 if (TrapFrame.Ctx.rax.u != uExpectRax) 2279 Bs3TestFailedF("Expected RAX = %#06RX64, got %#06RX64", uExpectRax, TrapFrame.Ctx.rax.u); 2280 if (TrapFrame.Ctx.rcx.u != uExpectRcx) 2281 Bs3TestFailedF("Expected RCX = %#06RX64, got %#06RX64", uExpectRcx, TrapFrame.Ctx.rcx.u); 2282 if (TrapFrame.Ctx.rbx.u != Ctx.rbx.u) 2283 Bs3TestFailedF("Expected RBX = %#06RX64, got %#06RX64 (dst)", Ctx.rbx.u, TrapFrame.Ctx.rbx.u); 2284 if (TrapFrame.Ctx.rdx.u != Ctx.rdx.u) 2285 Bs3TestFailedF("Expected RDX = %#06RX64, got %#06RX64 (src)", Ctx.rdx.u, TrapFrame.Ctx.rdx.u); 2286 2287 if ( (TrapFrame.Ctx.rflags.u16 & X86_EFL_STATUS_BITS) != (Ctx.rflags.u16 & X86_EFL_STATUS_BITS)) 2288 Bs3TestFailedF("Expected EFLAGS = %#06RX32, got %#06RX32 (immutable)", 2289 Ctx.rflags.u16 & X86_EFL_STATUS_BITS, TrapFrame.Ctx.rflags.u16 & X86_EFL_STATUS_BITS); 2290 if (TrapFrame.Ctx.rsp.u != Ctx.rsp.u) 2291 Bs3TestFailedF("Expected RSP = %#06RX64, got %#06RX64", Ctx.rsp.u, TrapFrame.Ctx.rsp.u); 2292 if (TrapFrame.Ctx.rbp.u != Ctx.rbp.u) 2293 Bs3TestFailedF("Expected RBP = %#06RX64, got %#06RX64", Ctx.rbp.u, TrapFrame.Ctx.rbp.u); 2294 if (TrapFrame.Ctx.rsi.u != Ctx.rsi.u) 2295 Bs3TestFailedF("Expected RSI = %#06RX64, got %#06RX64", Ctx.rsi.u, TrapFrame.Ctx.rsi.u); 2296 if (TrapFrame.Ctx.rdi.u != Ctx.rdi.u) 2297 Bs3TestFailedF("Expected RDI = %#06RX64, got %#06RX64", Ctx.rdi.u, TrapFrame.Ctx.rdi.u); 2298 if (uMemSrc1 != uMemSrc1Expect) 2299 Bs3TestFailedF("Expected uMemSrc1 = %#06RX64, got %#06RX64", (uint64_t)uMemSrc1Expect, (uint64_t)uMemSrc1); 2300 } 2301 } 2302 Ctx.rflags.u16 &= ~X86_EFL_STATUS_BITS; 2303 } 2304 2305 return 0; 2306 } 2307 2308 /* 2309 * 2310 */ 2143 2311 # if ARCH_BITS == 64 2144 2312 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2-template.mac
r95342 r95346 436 436 437 437 ; 438 ; 438 ; MULX 439 ; 440 BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_RAX_RCX_RBX_RDX_icebp, BS3_PBC_NEAR 441 %if TMPL_BITS == 64 442 mulx rax, rcx, rbx ; C4E2F3F6C3 443 %else 444 db 0C4h,0E2h,0F3h,0F6h,0C3h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe) 445 %endif 446 .again: 447 icebp 448 jmp .again 449 BS3_PROC_END_CMN bs3CpuInstr2_mulx_RAX_RCX_RBX_RDX_icebp 450 451 BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_RCX_RCX_RBX_RDX_icebp, BS3_PBC_NEAR 452 %if TMPL_BITS == 64 453 mulx rcx, rcx, rbx ; C4E2F3F6CB 454 %else 455 db 0C4h,0E2h,0F3h,0F6h,0CBh ; 32-bit & 16-bit ignores VEX.W=1 (10980xe) 456 %endif 457 .again: 458 icebp 459 jmp .again 460 BS3_PROC_END_CMN bs3CpuInstr2_mulx_RCX_RCX_RBX_RDX_icebp 461 462 BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_RAX_RCX_FSxBX_RDX_icebp, BS3_PBC_NEAR 463 %if TMPL_BITS == 64 464 mulx rax, rcx, [fs:rbx] ; 64C4E2F3F603 465 %elif TMPL_BITS == 32 466 db 064h,0C4h,0E2h,0F3h,0F6h,003h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe) 467 %else 468 db 064h,0C4h,0E2h,0F3h,0F6h,007h ; 32-bit & 16-bit ignores VEX.W=1 (10980xe) 469 %endif 470 .again: 471 icebp 472 jmp .again 473 BS3_PROC_END_CMN bs3CpuInstr2_mulx_RAX_RCX_FSxBX_RDX_icebp 474 475 BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_EAX_ECX_EBX_EDX_icebp, BS3_PBC_NEAR 476 mulx eax, ecx, ebx 477 .again: 478 icebp 479 jmp .again 480 BS3_PROC_END_CMN bs3CpuInstr2_mulx_EAX_ECX_EBX_EDX_icebp 481 482 BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_ECX_ECX_EBX_EDX_icebp, BS3_PBC_NEAR 483 mulx ecx, ecx, ebx 484 .again: 485 icebp 486 jmp .again 487 BS3_PROC_END_CMN bs3CpuInstr2_mulx_ECX_ECX_EBX_EDX_icebp 488 489 BS3_PROC_BEGIN_CMN bs3CpuInstr2_mulx_EAX_ECX_FSxBX_EDX_icebp, BS3_PBC_NEAR 490 mulx eax, ecx, [fs:xBX] 491 .again: 492 icebp 493 jmp .again 494 BS3_PROC_END_CMN bs3CpuInstr2_mulx_EAX_ECX_FSxBX_EDX_icebp 495 496 ; 497 ; CMPXCHG16B 439 498 ; 440 499 %if TMPL_BITS == 64 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2.c
r95342 r95346 53 53 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_sarx); 54 54 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_shrx); 55 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_mulx); 55 56 BS3TESTMODE_PROTOTYPES_CMN_64(bs3CpuInstr2_cmpxchg16b); 56 57 BS3TESTMODE_PROTOTYPES_CMN_64(bs3CpuInstr2_wrfsbase); … … 90 91 BS3TESTMODEENTRY_CMN("sarx", bs3CpuInstr2_sarx), 91 92 BS3TESTMODEENTRY_CMN("shrx", bs3CpuInstr2_shrx), 93 BS3TESTMODEENTRY_CMN("mulx", bs3CpuInstr2_mulx), 92 94 #endif 93 95 #if 1
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