Changeset 95422 in vbox
- Timestamp:
- Jun 29, 2022 2:42:16 AM (3 years ago)
- svn:sync-xref-src-repo-rev:
- 152024
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
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trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp
r95410 r95422 8278 8278 IEM_CIMPL_DEF_1(iemCImpl_finit, bool, fCheckXcpts) 8279 8279 { 8280 /* 8281 * Exceptions. 8282 */ 8280 8283 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0); 8281 8284 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) … … 8285 8288 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_X87); 8286 8289 8287 NOREF(fCheckXcpts); /** @todo trigger pending exceptions:8288 if (fCheckXcpts && TODO)8290 /* FINIT: Raise #MF on pending exception(s): */ 8291 if (fCheckXcpts && (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES)) 8289 8292 return iemRaiseMathFault(pVCpu); 8290 */ 8291 8293 8294 /* 8295 * Reset the state. 8296 */ 8292 8297 PX86XSAVEAREA pXState = &pVCpu->cpum.GstCtx.XState; 8293 pXState->x87.FCW = 0x37f; 8294 pXState->x87.FSW = 0; 8295 pXState->x87.FTW = 0x00; /* 0 - empty. */ 8296 pXState->x87.FPUDP = 0; 8297 pXState->x87.DS = 0; //?? 8298 pXState->x87.Rsrvd2= 0; 8299 pXState->x87.FPUIP = 0; 8300 pXState->x87.CS = 0; //?? 8301 pXState->x87.Rsrvd1= 0; 8302 pXState->x87.FOP = 0; 8298 pXState->x87.FCW = 0x37f; 8299 pXState->x87.FSW = 0; 8300 pXState->x87.FTW = 0x00; /* 0 - empty. */ 8301 /** @todo Intel says the instruction and data pointers are not cleared on 8302 * 387, presume that 8087 and 287 doesn't do so either. */ 8303 /** @todo test this stuff. */ 8304 if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_386) 8305 { 8306 pXState->x87.FPUDP = 0; 8307 pXState->x87.DS = 0; //?? 8308 pXState->x87.Rsrvd2 = 0; 8309 pXState->x87.FPUIP = 0; 8310 pXState->x87.CS = 0; //?? 8311 pXState->x87.Rsrvd1 = 0; 8312 } 8313 pXState->x87.FOP = 0; 8303 8314 8304 8315 iemHlpUsedFpu(pVCpu);
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