Changeset 95431 in vbox for trunk/src/VBox
- Timestamp:
- Jun 29, 2022 2:26:40 PM (3 years ago)
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 2 edited
-
bs3-cpu-basic-2-template.mac (modified) (2 diffs)
-
bs3-cpu-basic-2-x0.c (modified) (42 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-template.mac
r93115 r95431 356 356 357 357 ; 358 ; #PF 358 ; #PF & #AC 359 359 ; 360 360 … … 407 407 AssertCompile(.again - BS3_LAST_LABEL == 2 + (TMPL_BITS == 64)) 408 408 BS3_PROC_END_CMN bs3CpuBasic2_div_ds_bx__ud2 409 410 ; For testing FLD m80 alignment (#AC). 411 BS3_CPUBAS2_UD_OFF bs3CpuBasic2_fninit_fld_ds_bx__ud2 412 BS3_PROC_BEGIN_CMN bs3CpuBasic2_fninit_fld_ds_bx__ud2, BS3_PBC_NEAR 413 fninit ; make sure to not trigger a stack overflow. 414 .actual_test_instruction: 415 fld tword [xBX] 416 .again: ud2 417 jmp .again 418 AssertCompile(.actual_test_instruction - BS3_LAST_LABEL == 2) 419 BS3_PROC_END_CMN bs3CpuBasic2_fninit_fld_ds_bx__ud2 420 421 ; For testing FBLD m80 alignment (#AC). 422 BS3_CPUBAS2_UD_OFF bs3CpuBasic2_fninit_fbld_ds_bx__ud2 423 BS3_PROC_BEGIN_CMN bs3CpuBasic2_fninit_fbld_ds_bx__ud2, BS3_PBC_NEAR 424 fninit ; make sure to not trigger a stack overflow. 425 .actual_test_instruction: 426 fbld tword [xBX] 427 .again: ud2 428 jmp .again 429 AssertCompile(.actual_test_instruction - BS3_LAST_LABEL == 2) 430 BS3_PROC_END_CMN bs3CpuBasic2_fninit_fbld_ds_bx__ud2 431 432 ; For testing FST m80 alignment (#AC). 433 BS3_CPUBAS2_UD_OFF bs3CpuBasic2_fninit_fldz_fstp_ds_bx__ud2 434 BS3_PROC_BEGIN_CMN bs3CpuBasic2_fninit_fldz_fstp_ds_bx__ud2, BS3_PBC_NEAR 435 fninit ; make sure to not trigger a stack overflow. 436 fldz ; make sure we've got something to store 437 .actual_test_instruction: 438 fstp tword [xBX] 439 .again: ud2 440 jmp .again 441 AssertCompile(.actual_test_instruction - BS3_LAST_LABEL == 4) 442 BS3_PROC_END_CMN bs3CpuBasic2_fninit_fldz_fstp_ds_bx__ud2 443 444 ; For testing FXSAVE alignment (#AC/#GP). 445 BS3_CPUBAS2_UD_OFF bs3CpuBasic2_fxsave_ds_bx__ud2 446 BS3_PROC_BEGIN_CMN bs3CpuBasic2_fxsave_ds_bx__ud2, BS3_PBC_NEAR 447 fxsave [xBX] 448 .again: ud2 449 jmp .again 450 BS3_PROC_END_CMN bs3CpuBasic2_fxsave_ds_bx__ud2 409 451 410 452 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-x0.c
r95406 r95431 54 54 55 55 /** @name MYOP_XXX - Values for FNBS3CPUBASIC2ACTSTCODE::fOp. 56 * 57 * These are flags, though we've precombined a few shortening things down. 58 * 56 59 * @{ */ 57 #define MYOP_LD 0x1 58 #define MYOP_ST 0x2 59 #define MYOP_LD_ST 0x3 60 #define MYOP_EFL 0x4 61 #define MYOP_LD_DIV 0x5 60 #define MYOP_LD 0x1 /**< The instruction loads. */ 61 #define MYOP_ST 0x2 /**< The instruction stores */ 62 #define MYOP_EFL 0x4 /**< The instruction modifies EFLAGS. */ 63 #define MYOP_AC_GP 0x8 /**< The instruction may cause either \#AC or \#GP (FXSAVE). */ 64 65 #define MYOP_LD_ST 0x3 /**< Convenience: The instruction both loads and stores. */ 66 #define MYOP_LD_DIV 0x5 /**< Convenience: DIV instruction - loading and modifying flags. */ 62 67 /** @} */ 63 68 … … 89 94 FNBS3CPUBASIC2ACSNIPPET BS3_FAR *pfn; 90 95 uint8_t fOp; 91 uint8_t cbMem; 96 uint16_t cbMem; 97 uint8_t cbAlign; 98 uint8_t offFaultInstr; /**< For skipping fninit with the fld test. */ 92 99 } FNBS3CPUBASIC2ACTSTCODE; 93 100 typedef FNBS3CPUBASIC2ACTSTCODE const *PCFNBS3CPUBASIC2ACTSTCODE; … … 178 185 FNBS3CPUBASIC2ACSNIPPET bs3CpuBasic2_cmpxchg_ds_bx_cx__ud2_c16; 179 186 FNBS3CPUBASIC2ACSNIPPET bs3CpuBasic2_div_ds_bx__ud2_c16; 187 FNBS3CPUBASIC2ACSNIPPET bs3CpuBasic2_fninit_fld_ds_bx__ud2_c16; 188 FNBS3CPUBASIC2ACSNIPPET bs3CpuBasic2_fninit_fbld_ds_bx__ud2_c16; 189 FNBS3CPUBASIC2ACSNIPPET bs3CpuBasic2_fninit_fldz_fstp_ds_bx__ud2_c16; 190 FNBS3CPUBASIC2ACSNIPPET bs3CpuBasic2_fxsave_ds_bx__ud2_c16; 180 191 181 192 FNBS3CPUBASIC2ACSNIPPET bs3CpuBasic2_mov_ax_ds_bx__ud2_c32; … … 184 195 FNBS3CPUBASIC2ACSNIPPET bs3CpuBasic2_cmpxchg_ds_bx_cx__ud2_c32; 185 196 FNBS3CPUBASIC2ACSNIPPET bs3CpuBasic2_div_ds_bx__ud2_c32; 197 FNBS3CPUBASIC2ACSNIPPET bs3CpuBasic2_fninit_fld_ds_bx__ud2_c32; 198 FNBS3CPUBASIC2ACSNIPPET bs3CpuBasic2_fninit_fbld_ds_bx__ud2_c32; 199 FNBS3CPUBASIC2ACSNIPPET bs3CpuBasic2_fninit_fldz_fstp_ds_bx__ud2_c32; 200 FNBS3CPUBASIC2ACSNIPPET bs3CpuBasic2_fxsave_ds_bx__ud2_c32; 186 201 187 202 FNBS3CPUBASIC2ACSNIPPET bs3CpuBasic2_mov_ax_ds_bx__ud2_c64; … … 190 205 FNBS3CPUBASIC2ACSNIPPET bs3CpuBasic2_cmpxchg_ds_bx_cx__ud2_c64; 191 206 FNBS3CPUBASIC2ACSNIPPET bs3CpuBasic2_div_ds_bx__ud2_c64; 207 FNBS3CPUBASIC2ACSNIPPET bs3CpuBasic2_fninit_fld_ds_bx__ud2_c64; 208 FNBS3CPUBASIC2ACSNIPPET bs3CpuBasic2_fninit_fbld_ds_bx__ud2_c64; 209 FNBS3CPUBASIC2ACSNIPPET bs3CpuBasic2_fninit_fldz_fstp_ds_bx__ud2_c64; 210 FNBS3CPUBASIC2ACSNIPPET bs3CpuBasic2_fxsave_ds_bx__ud2_c64; 192 211 193 212 … … 334 353 static const FNBS3CPUBASIC2ACTSTCODE g_aCmn16[] = 335 354 { 336 { bs3CpuBasic2_mov_ax_ds_bx__ud2_c16, MYOP_LD, 2 }, 337 { bs3CpuBasic2_mov_ds_bx_ax__ud2_c16, MYOP_ST, 2 }, 338 { bs3CpuBasic2_xchg_ds_bx_ax__ud2_c16, MYOP_LD_ST, 2 }, 339 { bs3CpuBasic2_cmpxchg_ds_bx_cx__ud2_c16, MYOP_LD_ST | MYOP_EFL, 2 }, 340 { bs3CpuBasic2_div_ds_bx__ud2_c16, MYOP_LD_DIV, 2 }, 355 { bs3CpuBasic2_mov_ax_ds_bx__ud2_c16, MYOP_LD, 2, 2 }, 356 { bs3CpuBasic2_mov_ds_bx_ax__ud2_c16, MYOP_ST, 2, 2 }, 357 { bs3CpuBasic2_xchg_ds_bx_ax__ud2_c16, MYOP_LD_ST, 2, 2 }, 358 { bs3CpuBasic2_cmpxchg_ds_bx_cx__ud2_c16, MYOP_LD_ST | MYOP_EFL, 2, 2 }, 359 { bs3CpuBasic2_div_ds_bx__ud2_c16, MYOP_LD_DIV, 2, 2 }, 360 { bs3CpuBasic2_fninit_fld_ds_bx__ud2_c16, MYOP_LD, 10, 8, 2 /*fninit*/ }, 361 { bs3CpuBasic2_fninit_fbld_ds_bx__ud2_c16, MYOP_LD, 10, 8, 2 /*fninit*/ }, 362 { bs3CpuBasic2_fninit_fldz_fstp_ds_bx__ud2_c16, MYOP_ST, 10, 8, 4 /*fninit+fldz*/ }, 363 { bs3CpuBasic2_fxsave_ds_bx__ud2_c16, MYOP_ST | MYOP_AC_GP, 512, 16 }, 341 364 }; 342 365 343 366 static const FNBS3CPUBASIC2ACTSTCODE g_aCmn32[] = 344 367 { 345 { bs3CpuBasic2_mov_ax_ds_bx__ud2_c32, MYOP_LD, 4 }, 346 { bs3CpuBasic2_mov_ds_bx_ax__ud2_c32, MYOP_ST, 4 }, 347 { bs3CpuBasic2_xchg_ds_bx_ax__ud2_c32, MYOP_LD_ST, 4 }, 348 { bs3CpuBasic2_cmpxchg_ds_bx_cx__ud2_c32, MYOP_LD_ST | MYOP_EFL, 4 }, 349 { bs3CpuBasic2_div_ds_bx__ud2_c32, MYOP_LD_DIV, 4 }, 368 { bs3CpuBasic2_mov_ax_ds_bx__ud2_c32, MYOP_LD, 4, 4 }, 369 { bs3CpuBasic2_mov_ds_bx_ax__ud2_c32, MYOP_ST, 4, 4 }, 370 { bs3CpuBasic2_xchg_ds_bx_ax__ud2_c32, MYOP_LD_ST, 4, 4 }, 371 { bs3CpuBasic2_cmpxchg_ds_bx_cx__ud2_c32, MYOP_LD_ST | MYOP_EFL, 4, 4 }, 372 { bs3CpuBasic2_div_ds_bx__ud2_c32, MYOP_LD_DIV, 4, 4 }, 373 { bs3CpuBasic2_fninit_fld_ds_bx__ud2_c32, MYOP_LD, 10, 8, 2 /*fninit*/ }, 374 { bs3CpuBasic2_fninit_fbld_ds_bx__ud2_c32, MYOP_LD, 10, 8, 2 /*fninit*/ }, 375 { bs3CpuBasic2_fninit_fldz_fstp_ds_bx__ud2_c32, MYOP_ST, 10, 8, 4 /*fninit+fldz*/ }, 376 { bs3CpuBasic2_fxsave_ds_bx__ud2_c32, MYOP_ST | MYOP_AC_GP, 512, 16 }, 350 377 }; 351 378 352 379 static const FNBS3CPUBASIC2ACTSTCODE g_aCmn64[] = 353 380 { 354 { bs3CpuBasic2_mov_ax_ds_bx__ud2_c64, MYOP_LD, 8 }, 355 { bs3CpuBasic2_mov_ds_bx_ax__ud2_c64, MYOP_ST, 8 }, 356 { bs3CpuBasic2_xchg_ds_bx_ax__ud2_c64, MYOP_LD_ST, 8 }, 357 { bs3CpuBasic2_cmpxchg_ds_bx_cx__ud2_c64, MYOP_LD_ST | MYOP_EFL, 8 }, 358 { bs3CpuBasic2_div_ds_bx__ud2_c64, MYOP_LD_DIV, 8 }, 381 { bs3CpuBasic2_mov_ax_ds_bx__ud2_c64, MYOP_LD, 8, 8 }, 382 { bs3CpuBasic2_mov_ds_bx_ax__ud2_c64, MYOP_ST, 8, 8 }, 383 { bs3CpuBasic2_xchg_ds_bx_ax__ud2_c64, MYOP_LD_ST, 8, 8 }, 384 { bs3CpuBasic2_cmpxchg_ds_bx_cx__ud2_c64, MYOP_LD_ST | MYOP_EFL, 8, 8 }, 385 { bs3CpuBasic2_div_ds_bx__ud2_c64, MYOP_LD_DIV, 8, 8 }, 386 { bs3CpuBasic2_fninit_fld_ds_bx__ud2_c64, MYOP_LD, 10, 8, 2 /*fninit*/ }, 387 { bs3CpuBasic2_fninit_fbld_ds_bx__ud2_c64, MYOP_LD, 10, 8, 2 /*fninit*/ }, 388 { bs3CpuBasic2_fninit_fldz_fstp_ds_bx__ud2_c64, MYOP_ST, 10, 8, 4 /*fninit+fldz*/ }, 389 { bs3CpuBasic2_fxsave_ds_bx__ud2_c64, MYOP_ST | MYOP_AC_GP, 512, 16 }, 359 390 }; 360 391 … … 382 413 383 414 415 uint32_t ASMGetESP(void); 416 #pragma aux ASMGetESP = \ 417 ".386" \ 418 "mov ax, sp" \ 419 "mov edx, esp" \ 420 "shr edx, 16" \ 421 value [ax dx] \ 422 modify exact [ax dx]; 423 424 384 425 /** 385 426 * Wrapper around Bs3TestFailedF that prefixes the error with g_usBs3TestStep … … 450 491 */ 451 492 static void bs3CpuBasic2_CompareCpuTrapCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint16_t uErrCd, 452 uint8_t bXcpt, bool f486ResumeFlagHint )493 uint8_t bXcpt, bool f486ResumeFlagHint, uint8_t cbIpAdjust) 453 494 { 454 495 uint16_t const cErrorsBefore = Bs3TestSubErrorCount(); … … 458 499 CHECK_MEMBER("bErrCd", "%#06RX16", (uint16_t)pTrapCtx->uErrCd, (uint16_t)uErrCd); /* 486 only writes a word */ 459 500 460 fExtraEfl = X86_EFL_RF;461 501 if ( g_f16BitSys 462 502 || ( !f486ResumeFlagHint … … 468 508 fExtraEfl = pTrapCtx->Ctx.rflags.u32 & X86_EFL_RF; 469 509 #endif 470 Bs3TestCheckRegCtxEx(&pTrapCtx->Ctx, pStartCtx, 0 /*cbIpAdjust*/, 0 /*cbSpAdjust*/, fExtraEfl, g_pszTestMode, g_usBs3TestStep);510 Bs3TestCheckRegCtxEx(&pTrapCtx->Ctx, pStartCtx, cbIpAdjust, 0 /*cbSpAdjust*/, fExtraEfl, g_pszTestMode, g_usBs3TestStep); 471 511 if (Bs3TestSubErrorCount() != cErrorsBefore) 472 512 { … … 486 526 static void bs3CpuBasic2_CompareGpCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint16_t uErrCd) 487 527 { 488 bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_GP, true /*f486ResumeFlagHint*/ );528 bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_GP, true /*f486ResumeFlagHint*/, 0 /*cbIpAdjust*/); 489 529 } 490 530 … … 495 535 static void bs3CpuBasic2_CompareNpCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint16_t uErrCd) 496 536 { 497 bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_NP, true /*f486ResumeFlagHint*/ );537 bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_NP, true /*f486ResumeFlagHint*/, 0 /*cbIpAdjust*/); 498 538 } 499 539 #endif … … 504 544 static void bs3CpuBasic2_CompareSsCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint16_t uErrCd, bool f486ResumeFlagHint) 505 545 { 506 bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_SS, f486ResumeFlagHint );546 bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_SS, f486ResumeFlagHint, 0 /*cbIpAdjust*/); 507 547 } 508 548 … … 513 553 static void bs3CpuBasic2_CompareTsCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint16_t uErrCd) 514 554 { 515 bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_TS, false /*f486ResumeFlagHint*/ );555 bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_TS, false /*f486ResumeFlagHint*/, 0 /*cbIpAdjust*/); 516 556 } 517 557 #endif … … 520 560 * Compares \#PF trap. 521 561 */ 522 static void bs3CpuBasic2_ComparePfCtx(PCBS3TRAPFRAME pTrapCtx, PBS3REGCTX pStartCtx, uint16_t uErrCd, uint64_t uCr2Expected) 562 static void bs3CpuBasic2_ComparePfCtx(PCBS3TRAPFRAME pTrapCtx, PBS3REGCTX pStartCtx, uint16_t uErrCd, 563 uint64_t uCr2Expected, uint8_t cbIpAdjust) 523 564 { 524 565 uint64_t const uCr2Saved = pStartCtx->cr2.u; 525 566 pStartCtx->cr2.u = uCr2Expected; 526 bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_PF, true /*f486ResumeFlagHint*/ );567 bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_PF, true /*f486ResumeFlagHint*/, cbIpAdjust); 527 568 pStartCtx->cr2.u = uCr2Saved; 528 569 } … … 533 574 static void bs3CpuBasic2_CompareUdCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx) 534 575 { 535 bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, 0 /*no error code*/, X86_XCPT_UD, true /*f486ResumeFlagHint*/); 576 bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, 0 /*no error code*/, X86_XCPT_UD, 577 true /*f486ResumeFlagHint*/, 0 /*cbIpAdjust*/); 536 578 } 537 579 … … 539 581 * Compares \#AC trap. 540 582 */ 541 static void bs3CpuBasic2_CompareAcCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx )542 { 543 bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, 0 /*always zero*/, X86_XCPT_AC, true /*f486ResumeFlagHint*/ );583 static void bs3CpuBasic2_CompareAcCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint8_t cbIpAdjust) 584 { 585 bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, 0 /*always zero*/, X86_XCPT_AC, true /*f486ResumeFlagHint*/, cbIpAdjust); 544 586 } 545 587 … … 1540 1582 * one also using xDX, so make sure they make some sense. 1541 1583 */ 1542 Bs3RegCtxSaveEx(&Ctx, bMode, 256); 1543 1544 for (iRing = 0; iRing < cRings; iRing++) 1584 Bs3RegCtxSaveEx(&Ctx, bMode, 512); 1585 1586 Ctx.cr0.u32 &= ~(X86_CR0_MP | X86_CR0_EM | X86_CR0_TS); /* so fninit + fld works */ 1587 1588 for (iRing = BS3_MODE_IS_V86(bMode) ? 3 : 0; iRing < cRings; iRing++) 1545 1589 { 1546 1590 uint32_t uEbx; 1547 1591 uint8_t fAc; 1548 1592 1549 Bs3RegCtxConvertToRingX(&Ctx, iRing); 1593 if (!BS3_MODE_IS_RM_OR_V86(bMode)) 1594 Bs3RegCtxConvertToRingX(&Ctx, iRing); 1550 1595 1551 1596 if (!fPf || BS3_MODE_IS_32BIT_CODE(bMode) || BS3_MODE_IS_64BIT_CODE(bMode)) … … 1580 1625 for (iTest = 0; iTest < pCmn->cEntries; iTest++) 1581 1626 { 1582 uint8_t const fOp = pCmn->paEntries[iTest].fOp; 1583 uint8_t const cbMem = pCmn->paEntries[iTest].cbMem; 1584 uint16_t const cbMax = cbCacheLine + cbMem; 1627 uint8_t const fOp = pCmn->paEntries[iTest].fOp; 1628 uint16_t const cbMem = pCmn->paEntries[iTest].cbMem; 1629 uint8_t const cbAlign = pCmn->paEntries[iTest].cbAlign; 1630 uint16_t const cbMax = cbCacheLine + cbMem; 1585 1631 uint16_t offMem; 1586 1632 uint8_t BS3_FAR *poffUd = (uint8_t BS3_FAR *)Bs3SelLnkPtrToCurPtr(pCmn->paEntries[iTest].pfn); … … 1590 1636 CtxUdExpected.cs = Ctx.cs; 1591 1637 CtxUdExpected.rflags = Ctx.rflags; 1592 if (bMode == BS3_MODE_RM) CtxUdExpected.rflags.u32 &= ~X86_EFL_AC; /** @todo investigate. automatically cleared, or is it just our code? Observed with bs3-cpu-instr-3 too (10980xe). */ 1638 if (bMode == BS3_MODE_RM) 1639 CtxUdExpected.rflags.u32 &= ~X86_EFL_AC; /** @todo investigate. automatically cleared, or is it just our code? Observed with bs3-cpu-instr-3 too (10980xe), seems to be the CPU doing it. */ 1593 1640 CtxUdExpected.rdx = Ctx.rdx; 1594 1641 CtxUdExpected.rax = Ctx.rax; … … 1617 1664 for (offMem = 0; offMem < cbMax; offMem++) 1618 1665 { 1619 bool const fMisaligned = (offMem & (cb Mem - 1)) != 0; /** @todo assumes cbMem is a power of two! */1666 bool const fMisaligned = (offMem & (cbAlign - 1)) != 0; 1620 1667 unsigned offBuf = cbMax + cbMem * 2; 1621 1668 while (offBuf-- > 0) 1622 1669 pbBuf[offBuf] = 1; /* byte-by-byte to make sure it doesn't trigger AC. */ 1623 1670 1624 CtxUdExpected.rbx.u32 = Ctx.rbx.u32 = uEbx + offMem; /* ASSUMES memory in first 4GB (cur stack, so okay). */1671 CtxUdExpected.rbx.u32 = Ctx.rbx.u32 = uEbx + offMem; /* ASSUMES memory in first 4GB. */ 1625 1672 if (BS3_MODE_IS_16BIT_SYS(bMode)) 1626 1673 g_uBs3TrapEipHint = Ctx.rip.u32; 1627 1674 1628 //if (iRing == 3 && fPf && fAm) 1629 // Bs3TestPrintf("iRing=%d iTest=%d cs:rip=%04RX16:%08RX32 ds:rbx=%04RX16:%08RX32 bXcpt=%#x errcd=%#x fAm=%d fAc=%d\n", 1630 // iRing, iTest, Ctx.cs, Ctx.rip.u32, Ctx.ds, Ctx.rbx.u32, TrapCtx.bXcpt, (unsigned)TrapCtx.uErrCd, fAm, fAc); 1675 //Bs3TestPrintf("iRing=%d iTest=%d cs:rip=%04RX16:%08RX32 ds:rbx=%04RX16:%08RX32 ss:esp=%04RX16:%08RX32 bXcpt=%#x errcd=%#x fAm=%d fAc=%d ESP=%#RX32\n", 1676 // iRing, iTest, Ctx.cs, Ctx.rip.u32, Ctx.ds, Ctx.rbx.u32, Ctx.ss, Ctx.rsp.u32, TrapCtx.bXcpt, (unsigned)TrapCtx.uErrCd, fAm, fAc, ASMGetESP()); 1631 1677 1632 1678 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 1633 1679 1634 if (fPf && iRing == 3 && (!fAm || !fAc || !fMisaligned)) /* #AC beats #PF */ 1680 if ( (pCmn->paEntries[iTest].fOp & MYOP_AC_GP) 1681 && fMisaligned 1682 && (!fAm || iRing != 3 || !fAc || (offMem & 3 /* 10980XE */) == 0) ) 1683 { 1684 if (fAc && bMode == BS3_MODE_RM) 1685 TrapCtx.Ctx.rflags.u32 |= X86_EFL_AC; 1686 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 1687 } 1688 else if (fPf && iRing == 3 && (!fAm || !fAc || !fMisaligned)) /* #AC beats #PF */ 1635 1689 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, 1636 1690 X86_TRAP_PF_P | X86_TRAP_PF_US 1637 1691 | (pCmn->paEntries[iTest].fOp & MYOP_ST ? X86_TRAP_PF_RW : 0), 1638 uFlatBufPtr + offMem); 1692 uFlatBufPtr + offMem + (cbMem > 64 ? cbMem - 1 /*FXSAVE*/ : 0), 1693 pCmn->paEntries[iTest].offFaultInstr); 1639 1694 else if (!fAm || iRing != 3 || !fAc || !fMisaligned) 1640 1695 { … … 1652 1707 } 1653 1708 else 1654 bs3CpuBasic2_CompareAcCtx(&TrapCtx, &Ctx );1709 bs3CpuBasic2_CompareAcCtx(&TrapCtx, &Ctx, pCmn->paEntries[iTest].offFaultInstr); 1655 1710 1656 1711 g_usBs3TestStep++; … … 1674 1729 { 1675 1730 unsigned cbCacheLine = 128; /** @todo detect */ 1676 uint8_t abBuf[4096 /** @todo 512 - but that went crazy in real mode; now it's long mode going wrong. */];1731 uint8_t BS3_FAR *pbBufAlloc; 1677 1732 uint8_t BS3_FAR *pbBuf; 1678 1733 unsigned idxCmnModes; 1679 1734 uint32_t fCr0; 1680 Bs3MemZero(&abBuf, sizeof(abBuf));1681 1735 1682 1736 /* … … 1692 1746 1693 1747 /* Get us a 64-byte aligned buffer. */ 1694 pbBuf = abBuf; 1695 if (BS3_FP_OFF(pbBuf) & (cbCacheLine - 1)) 1696 pbBuf = &abBuf[cbCacheLine - (BS3_FP_OFF(pbBuf) & (cbCacheLine - 1))]; 1697 BS3_ASSERT(pbBuf - abBuf <= cbCacheLine); 1748 pbBufAlloc = pbBuf = Bs3MemAllocZ(BS3_MODE_IS_RM_OR_V86(bMode) ? BS3MEMKIND_REAL : BS3MEMKIND_TILED, X86_PAGE_SIZE * 2); 1749 if (!pbBufAlloc) 1750 return Bs3TestFailed("Failed to allocate 2 pages of real-mode memory"); 1751 if (BS3_FP_OFF(pbBuf) & (X86_PAGE_SIZE - 1)) 1752 pbBuf = &pbBufAlloc[X86_PAGE_SIZE - (BS3_FP_OFF(pbBuf) & X86_PAGE_OFFSET_MASK)]; 1753 BS3_ASSERT(pbBuf - pbBufAlloc <= X86_PAGE_SIZE); 1698 1754 //Bs3TestPrintf("pbBuf=%p\n", pbBuf); 1699 1755 … … 1705 1761 1706 1762 /* First round is w/o alignment checks enabled. */ 1763 //Bs3TestPrintf("round 1\n"); 1707 1764 fCr0 = Bs3RegGetCr0(); 1708 1765 BS3_ASSERT(!(fCr0 & X86_CR0_AM)); … … 1714 1771 /* The second round is with aligment checks enabled. */ 1715 1772 #if 1 1773 //Bs3TestPrintf("round 2\n"); 1716 1774 Bs3RegSetCr0(Bs3RegGetCr0() | X86_CR0_AM); 1717 1775 bs3CpuBasic2_RaiseXcpt11Worker(bMode, pbBuf, cbCacheLine, true /*fAm*/, false /*fPf*/, 0, &g_aCmnModes[idxCmnModes]); … … 1722 1780 accessible from ring-3. The third round has ACs disabled and the fourth 1723 1781 has them enabled. */ 1724 if (BS3_MODE_IS_PAGED(bMode) && !BS3_MODE_IS_V86(bMode)) //&& (BS3_MODE_IS_32BIT_CODE(bMode) || BS3_MODE_IS_64BIT_CODE(bMode)))1782 if (BS3_MODE_IS_PAGED(bMode) && !BS3_MODE_IS_V86(bMode)) 1725 1783 { 1726 1784 /* Alias the buffer as system memory so ring-3 access with AC+AM will cause #PF: */ 1785 /** @todo the aliasing is not necessary any more... */ 1727 1786 int rc; 1728 1787 RTCCUINTXREG uFlatBufPtr = Bs3SelPtrToFlat(pbBuf); … … 1732 1791 if (RT_SUCCESS(rc)) 1733 1792 { 1793 /* We 'misalign' the segment base here to make sure it's the final 1794 address that gets alignment checked and not just the operand value. */ 1734 1795 RTCCUINTXREG uAliasBufPtr = (RTCCUINTXREG)uAliasPgPtr + (uFlatBufPtr & X86_PAGE_OFFSET_MASK); 1735 uint8_t BS3_FAR *pbBufAlias = BS3_FP_MAKE(BS3_SEL_SPARE_00 | 3, uFlatBufPtr & X86_PAGE_OFFSET_MASK);;1736 Bs3SelSetup16BitData(&Bs3GdteSpare00, uAliasPgPtr );1737 1738 Bs3TestPrintf("round three\n");1796 uint8_t BS3_FAR *pbBufAlias = BS3_FP_MAKE(BS3_SEL_SPARE_00 | 3, (uFlatBufPtr & X86_PAGE_OFFSET_MASK) + 1); 1797 Bs3SelSetup16BitData(&Bs3GdteSpare00, uAliasPgPtr - 1); 1798 1799 //Bs3TestPrintf("round 3 pbBufAlias=%p\n", pbBufAlias); 1739 1800 Bs3RegSetCr0(Bs3RegGetCr0() & ~X86_CR0_AM); 1740 1801 bs3CpuBasic2_RaiseXcpt11Worker(bMode, pbBufAlias, cbCacheLine, false /*fAm*/, 1741 1802 true /*fPf*/, uAliasBufPtr, &g_aCmnModes[idxCmnModes]); 1742 1803 1743 Bs3TestPrintf("round four\n");1804 //Bs3TestPrintf("round 4\n"); 1744 1805 Bs3RegSetCr0(Bs3RegGetCr0() | X86_CR0_AM); 1745 1806 bs3CpuBasic2_RaiseXcpt11Worker(bMode, pbBufAlias, cbCacheLine, true /*fAm*/, 1746 1807 true /*fPf*/, uAliasBufPtr, &g_aCmnModes[idxCmnModes]); 1747 Bs3TestPrintf("done\n");1748 1808 1749 1809 Bs3PagingUnalias(uAliasPgPtr, X86_PAGE_SIZE * 2); … … 1754 1814 #endif 1755 1815 1816 Bs3MemFree(pbBufAlloc, X86_PAGE_SIZE * 2); 1756 1817 Bs3RegSetCr0(fCr0); 1757 1818 return 0; … … 2049 2110 { 2050 2111 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, X86_TRAP_PF_RW | (Ctx.bCpl == 3 ? X86_TRAP_PF_US : 0), 2051 uFlatTest + RT_MAX(off, X86_PAGE_SIZE) );2112 uFlatTest + RT_MAX(off, X86_PAGE_SIZE), 0 /*cbIpAdjust*/); 2052 2113 if ( off <= X86_PAGE_SIZE - 2 2053 2114 && Bs3MemCmp(&pbTest[off], pbExpected, 2) != 0) … … 2084 2145 else 2085 2146 { 2086 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, X86_TRAP_PF_RW | (Ctx.bCpl == 3 ? X86_TRAP_PF_US : 0), uFlatTest + off); 2147 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, X86_TRAP_PF_RW | (Ctx.bCpl == 3 ? X86_TRAP_PF_US : 0), 2148 uFlatTest + off, 0 /*cbIpAdjust*/); 2087 2149 if ( -off < cbIdtr 2088 2150 && !ASMMemIsAllU8(pbTest, cbIdtr + off, bFiller)) … … 2139 2201 { 2140 2202 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, X86_TRAP_PF_RW | (Ctx.bCpl == 3 ? X86_TRAP_PF_US : 0), 2141 uFlatTest + RT_MAX(off, X86_PAGE_SIZE) );2203 uFlatTest + RT_MAX(off, X86_PAGE_SIZE), 0 /*cbIpAdjust*/); 2142 2204 if ( off <= X86_PAGE_SIZE - 2 2143 2205 && Bs3MemCmp(&pbTest[off], pbExpected, 2) != 0) … … 2174 2236 { 2175 2237 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, X86_TRAP_PF_RW | (Ctx.bCpl == 3 ? X86_TRAP_PF_US : 0), 2176 uFlatTest + RT_MAX(off, X86_PAGE_SIZE) );2238 uFlatTest + RT_MAX(off, X86_PAGE_SIZE), 0 /*cbIpAdjust*/); 2177 2239 if ( off < X86_PAGE_SIZE 2178 2240 && !ASMMemIsAllU8(&pbTest[off], X86_PAGE_SIZE - off, bFiller)) … … 2245 2307 if (cbLimit < off && off < X86_PAGE_SIZE) 2246 2308 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, X86_TRAP_PF_RW | (Ctx.bCpl == 3 ? X86_TRAP_PF_US : 0), 2247 uFlatTest + off );2309 uFlatTest + off, 0 /*cbIpAdjust*/); 2248 2310 else if (pWorker->fSs) 2249 2311 bs3CpuBasic2_CompareSsCtx(&TrapCtx, &Ctx, 0, false /*f486ResumeFlagHint*/); … … 2870 2932 } 2871 2933 else 2872 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, 0, uFlatTest + RT_MAX(off, X86_PAGE_SIZE) );2934 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, 0, uFlatTest + RT_MAX(off, X86_PAGE_SIZE), 0 /*cbIpAdjust*/); 2873 2935 g_usBs3TestStep++; 2874 2936 … … 2889 2951 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2890 2952 else 2891 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, 0, uFlatTest + RT_MAX(off, X86_PAGE_SIZE) );2953 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, 0, uFlatTest + RT_MAX(off, X86_PAGE_SIZE), 0 /*cbIpAdjust*/); 2892 2954 g_usBs3TestStep++; 2893 2955 } … … 2919 2981 } 2920 2982 else 2921 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, 0, uFlatTest + off );2983 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, 0, uFlatTest + off, 0 /*cbIpAdjust*/); 2922 2984 g_usBs3TestStep++; 2923 2985 … … 2932 2994 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx, 0); 2933 2995 else 2934 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, 0, uFlatTest + off );2996 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, 0, uFlatTest + off, 0 /*cbIpAdjust*/); 2935 2997 g_usBs3TestStep++; 2936 2998 } … … 2988 3050 } 2989 3051 else 2990 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, 0, uFlatTest + RT_MAX(off, X86_PAGE_SIZE) );3052 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, 0, uFlatTest + RT_MAX(off, X86_PAGE_SIZE), 0 /*cbIpAdjust*/); 2991 3053 } 2992 3054 /* No #GP/#SS on limit, but instead #PF? */ … … 2994 3056 ? off < cbLimit && off >= 0xfff 2995 3057 : off + 2 < cbLimit && off >= 0xffd) 2996 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, 0, uFlatTest + RT_MAX(off, X86_PAGE_SIZE) );3058 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, 0, uFlatTest + RT_MAX(off, X86_PAGE_SIZE), 0 /*cbIpAdjust*/); 2997 3059 /* #GP/#SS on limit or base. */ 2998 3060 else if (pWorker->fSs) … … 3047 3109 } 3048 3110 else if (cbLimit < off && off < X86_PAGE_SIZE) 3049 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, 0, uFlatTest + off );3111 bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx, 0, uFlatTest + off, 0 /*cbIpAdjust*/); 3050 3112 else if (pWorker->fSs) 3051 3113 bs3CpuBasic2_CompareSsCtx(&TrapCtx, &Ctx, 0, false /*f486ResumeFlagHint*/); … … 3251 3313 } 3252 3314 3253 uint32_t ASMGetESP(void);3254 #pragma aux ASMGetESP = \3255 ".386" \3256 "mov ax, sp" \3257 "mov edx, esp" \3258 "shr edx, 16" \3259 value [ax dx] \3260 modify exact [ax dx];3261 3262 3315 3263 3316 static void bs3CpuBasic2_iret_Worker(uint8_t bTestMode, FPFNBS3FAR pfnIret, unsigned const cbPop,
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