Changeset 95439 in vbox
- Timestamp:
- Jun 29, 2022 10:35:28 PM (3 years ago)
- svn:sync-xref-src-repo-rev:
- 152044
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 3 edited
-
bs3-cpu-instr-3-template.c (modified) (3 diffs)
-
bs3-cpu-instr-3-template.mac (modified) (3 diffs)
-
bs3-cpu-instr-3.c (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.c
r95401 r95439 113 113 extern FNBS3FAR RT_CONCAT(a_BaseNm, _c64) 114 114 115 /* AND */ 116 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pand_MM1_MM2_icebp); 117 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pand_MM1_FSxBX_icebp); 118 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pand_XMM1_XMM2_icebp); 119 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pand_XMM1_FSxBX_icebp); 120 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpand_XMM1_XMM1_XMM2_icebp); 121 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpand_XMM1_XMM1_FSxBX_icebp); 122 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpand_YMM7_YMM2_YMM3_icebp); 123 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpand_YMM7_YMM2_FSxBX_icebp); 124 125 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andps_XMM1_XMM2_icebp); 126 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andps_XMM1_FSxBX_icebp); 127 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandps_XMM1_XMM1_XMM2_icebp); 128 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandps_XMM1_XMM1_FSxBX_icebp); 129 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandps_YMM1_YMM1_YMM2_icebp); 130 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandps_YMM1_YMM1_FSxBX_icebp); 131 132 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andpd_XMM1_XMM2_icebp); 133 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andpd_XMM1_FSxBX_icebp); 134 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandpd_XMM2_XMM1_XMM0_icebp); 135 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandpd_XMM2_XMM1_FSxBX_icebp); 136 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandpd_YMM2_YMM1_YMM0_icebp); 137 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandpd_YMM2_YMM1_FSxBX_icebp); 138 extern FNBS3FAR bs3CpuInstr3_vandpd_YMM10_YMM8_YMM15_icebp_c64; 139 140 /* ANDN */ 141 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pandn_MM1_MM2_icebp); 142 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pandn_MM1_FSxBX_icebp); 143 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pandn_XMM1_XMM2_icebp); 144 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pandn_XMM1_FSxBX_icebp); 145 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpandn_XMM1_XMM1_XMM2_icebp); 146 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpandn_XMM1_XMM1_FSxBX_icebp); 147 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpandn_YMM7_YMM2_YMM3_icebp); 148 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpandn_YMM7_YMM2_FSxBX_icebp); 149 150 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andnps_XMM1_XMM2_icebp); 151 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andnps_XMM1_FSxBX_icebp); 152 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnps_XMM1_XMM1_XMM2_icebp); 153 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnps_XMM1_XMM1_FSxBX_icebp); 154 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnps_YMM1_YMM1_YMM2_icebp); 155 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnps_YMM1_YMM1_FSxBX_icebp); 156 157 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andnpd_XMM1_XMM2_icebp); 158 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andnpd_XMM1_FSxBX_icebp); 159 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnpd_XMM2_XMM1_XMM0_icebp); 160 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnpd_XMM2_XMM1_FSxBX_icebp); 161 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnpd_YMM2_YMM1_YMM0_icebp); 162 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnpd_YMM2_YMM1_FSxBX_icebp); 163 extern FNBS3FAR bs3CpuInstr3_vandnpd_YMM10_YMM8_YMM15_icebp_c64; 164 165 /* OR */ 166 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_por_MM1_MM2_icebp); 167 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_por_MM1_FSxBX_icebp); 168 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_por_XMM1_XMM2_icebp); 169 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_por_XMM1_FSxBX_icebp); 170 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpor_XMM1_XMM1_XMM2_icebp); 171 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpor_XMM1_XMM1_FSxBX_icebp); 172 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpor_YMM7_YMM2_YMM3_icebp); 173 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpor_YMM7_YMM2_FSxBX_icebp); 174 175 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_orps_XMM1_XMM2_icebp); 176 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_orps_XMM1_FSxBX_icebp); 177 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorps_XMM1_XMM1_XMM2_icebp); 178 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorps_XMM1_XMM1_FSxBX_icebp); 179 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorps_YMM1_YMM1_YMM2_icebp); 180 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorps_YMM1_YMM1_FSxBX_icebp); 181 182 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_orpd_XMM1_XMM2_icebp); 183 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_orpd_XMM1_FSxBX_icebp); 184 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorpd_XMM2_XMM1_XMM0_icebp); 185 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorpd_XMM2_XMM1_FSxBX_icebp); 186 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorpd_YMM2_YMM1_YMM0_icebp); 187 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorpd_YMM2_YMM1_FSxBX_icebp); 188 extern FNBS3FAR bs3CpuInstr3_vorpd_YMM10_YMM8_YMM15_icebp_c64; 189 190 /* XOR */ 115 191 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pxor_MM1_MM2_icebp); 116 192 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pxor_MM1_FSxBX_icebp); … … 477 553 Bs3RegCtxSaveEx(&Ctx, bMode, 1024); 478 554 bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx); 555 //Bs3TestPrintf("FTW=%#x mm1/st1=%.16Rhxs\n", pExtCtx->Ctx.x87.FTW, &pExtCtx->Ctx.x87.aRegs[1]); 479 556 480 557 /* … … 678 755 } 679 756 757 680 758 /* 681 * XORPS, 128-bit VXORPS 759 * PAND, VPAND, ANDPS, VANDPS, ANDPD, VANDPD. 760 */ 761 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr3_v_andps_andpd_pand)(uint8_t bMode) 762 { 763 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] = 764 { 765 { RTUINT256_INIT_C(0, 0, 0, 0), 766 /* ^ */ RTUINT256_INIT_C(0, 0, 0, 0), 767 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, 768 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), 769 /* ^ */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), 770 /* = */ RTUINT256_INIT_C(0x5555666677770000, 0x1111222233334444, 0x1111222233334444, 0x5555666677770000) }, 771 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 772 /* ^ */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 773 /* = */ RTUINT256_INIT_C(0x0c09d02808403294, 0x385406c840621622, 0x8000290816080282, 0x0050c020030090b9) }, 774 }; 775 776 static BS3CPUINSTR3_TEST1_T const s_aTests16[] = 777 { 778 { bs3CpuInstr3_pand_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 779 { bs3CpuInstr3_pand_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 780 { bs3CpuInstr3_pand_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 781 { bs3CpuInstr3_pand_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 782 { bs3CpuInstr3_vpand_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 783 { bs3CpuInstr3_vpand_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 784 { bs3CpuInstr3_vpand_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, 785 { bs3CpuInstr3_vpand_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, 786 787 { bs3CpuInstr3_andps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 788 { bs3CpuInstr3_andps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 789 { bs3CpuInstr3_vandps_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 790 { bs3CpuInstr3_vandps_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 791 { bs3CpuInstr3_vandps_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 792 { bs3CpuInstr3_vandps_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 793 794 { bs3CpuInstr3_andpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 795 { bs3CpuInstr3_andpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 796 { bs3CpuInstr3_vandpd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, 797 { bs3CpuInstr3_vandpd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 798 { bs3CpuInstr3_vandpd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, 799 { bs3CpuInstr3_vandpd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 800 }; 801 802 # if ARCH_BITS >= 32 803 static BS3CPUINSTR3_TEST1_T const s_aTests32[] = 804 { 805 { bs3CpuInstr3_pand_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 806 { bs3CpuInstr3_pand_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 807 { bs3CpuInstr3_pand_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 808 { bs3CpuInstr3_pand_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 809 { bs3CpuInstr3_vpand_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 810 { bs3CpuInstr3_vpand_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 811 { bs3CpuInstr3_vpand_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, 812 { bs3CpuInstr3_vpand_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, 813 814 { bs3CpuInstr3_andps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 815 { bs3CpuInstr3_andps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 816 { bs3CpuInstr3_vandps_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 817 { bs3CpuInstr3_vandps_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 818 { bs3CpuInstr3_vandps_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 819 { bs3CpuInstr3_vandps_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 820 821 { bs3CpuInstr3_andpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 822 { bs3CpuInstr3_andpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 823 { bs3CpuInstr3_vandpd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, 824 { bs3CpuInstr3_vandpd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 825 { bs3CpuInstr3_vandpd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, 826 { bs3CpuInstr3_vandpd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 827 }; 828 # endif 829 # if ARCH_BITS >= 64 830 static BS3CPUINSTR3_TEST1_T const s_aTests64[] = 831 { 832 { bs3CpuInstr3_pand_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 833 { bs3CpuInstr3_pand_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 834 { bs3CpuInstr3_pand_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 835 { bs3CpuInstr3_pand_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 836 { bs3CpuInstr3_vpand_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 837 { bs3CpuInstr3_vpand_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 838 { bs3CpuInstr3_vpand_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, 839 { bs3CpuInstr3_vpand_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, 840 841 { bs3CpuInstr3_andps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 842 { bs3CpuInstr3_andps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 843 { bs3CpuInstr3_vandps_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 844 { bs3CpuInstr3_vandps_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 845 { bs3CpuInstr3_vandps_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 846 { bs3CpuInstr3_vandps_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 847 848 { bs3CpuInstr3_andpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 849 { bs3CpuInstr3_andpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 850 { bs3CpuInstr3_vandpd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, 851 { bs3CpuInstr3_vandpd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 852 { bs3CpuInstr3_vandpd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, 853 { bs3CpuInstr3_vandpd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 854 { bs3CpuInstr3_vandpd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValues), s_aValues }, 855 }; 856 # endif 857 858 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 859 unsigned const iTest = BS3CPUINSTR3_TEST1_MODES_INDEX(bMode); 860 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 861 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); 862 } 863 864 865 /* 866 * PANDN, VPANDN, ANDNPS, VANDNPS, ANDNPD, VANDNPD. 867 */ 868 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr3_v_andnps_andnpd_pandn)(uint8_t bMode) 869 { 870 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] = 871 { 872 { RTUINT256_INIT_C(0, 0, 0, 0), 873 /* ^ */ RTUINT256_INIT_C(0, 0, 0, 0), 874 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, 875 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), 876 /* ^ */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), 877 /* = */ RTUINT256_INIT_C(0x0000000000008888, 0x0000000000000000, 0x0000000000000000, 0x0000000000008888) }, 878 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 879 /* ^ */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 880 /* = */ RTUINT256_INIT_C(0x41002002649c4141, 0x06a01100260929c4, 0x342106a040449920, 0x9c0c205390090602) }, 881 }; 882 883 static BS3CPUINSTR3_TEST1_T const s_aTests16[] = 884 { 885 { bs3CpuInstr3_pandn_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 886 { bs3CpuInstr3_pandn_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 887 { bs3CpuInstr3_pandn_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 888 { bs3CpuInstr3_pandn_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 889 { bs3CpuInstr3_vpandn_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 890 { bs3CpuInstr3_vpandn_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 891 { bs3CpuInstr3_vpandn_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, 892 { bs3CpuInstr3_vpandn_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, 893 894 { bs3CpuInstr3_andnps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 895 { bs3CpuInstr3_andnps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 896 { bs3CpuInstr3_vandnps_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 897 { bs3CpuInstr3_vandnps_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 898 { bs3CpuInstr3_vandnps_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 899 { bs3CpuInstr3_vandnps_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 900 901 { bs3CpuInstr3_andnpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 902 { bs3CpuInstr3_andnpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 903 { bs3CpuInstr3_vandnpd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, 904 { bs3CpuInstr3_vandnpd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 905 { bs3CpuInstr3_vandnpd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, 906 { bs3CpuInstr3_vandnpd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 907 }; 908 909 # if ARCH_BITS >= 32 910 static BS3CPUINSTR3_TEST1_T const s_aTests32[] = 911 { 912 { bs3CpuInstr3_pandn_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 913 { bs3CpuInstr3_pandn_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 914 { bs3CpuInstr3_pandn_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 915 { bs3CpuInstr3_pandn_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 916 { bs3CpuInstr3_vpandn_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 917 { bs3CpuInstr3_vpandn_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 918 { bs3CpuInstr3_vpandn_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, 919 { bs3CpuInstr3_vpandn_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, 920 921 { bs3CpuInstr3_andnps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 922 { bs3CpuInstr3_andnps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 923 { bs3CpuInstr3_vandnps_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 924 { bs3CpuInstr3_vandnps_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 925 { bs3CpuInstr3_vandnps_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 926 { bs3CpuInstr3_vandnps_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 927 928 { bs3CpuInstr3_andnpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 929 { bs3CpuInstr3_andnpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 930 { bs3CpuInstr3_vandnpd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, 931 { bs3CpuInstr3_vandnpd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 932 { bs3CpuInstr3_vandnpd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, 933 { bs3CpuInstr3_vandnpd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 934 }; 935 # endif 936 # if ARCH_BITS >= 64 937 static BS3CPUINSTR3_TEST1_T const s_aTests64[] = 938 { 939 { bs3CpuInstr3_pandn_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 940 { bs3CpuInstr3_pandn_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 941 { bs3CpuInstr3_pandn_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 942 { bs3CpuInstr3_pandn_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 943 { bs3CpuInstr3_vpandn_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 944 { bs3CpuInstr3_vpandn_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 945 { bs3CpuInstr3_vpandn_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, 946 { bs3CpuInstr3_vpandn_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, 947 948 { bs3CpuInstr3_andnps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 949 { bs3CpuInstr3_andnps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 950 { bs3CpuInstr3_vandnps_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 951 { bs3CpuInstr3_vandnps_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 952 { bs3CpuInstr3_vandnps_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 953 { bs3CpuInstr3_vandnps_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 954 955 { bs3CpuInstr3_andnpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 956 { bs3CpuInstr3_andnpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 957 { bs3CpuInstr3_vandnpd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, 958 { bs3CpuInstr3_vandnpd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 959 { bs3CpuInstr3_vandnpd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, 960 { bs3CpuInstr3_vandnpd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 961 { bs3CpuInstr3_vandnpd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValues), s_aValues }, 962 }; 963 # endif 964 965 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 966 unsigned const iTest = BS3CPUINSTR3_TEST1_MODES_INDEX(bMode); 967 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 968 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); 969 } 970 971 972 973 /* 974 * POR, VPOR, PORPS, VORPS, PORPD, VPORPD. 975 */ 976 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr3_v_orps_orpd_por)(uint8_t bMode) 977 { 978 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] = 979 { 980 { RTUINT256_INIT_C(0, 0, 0, 0), 981 /* ^ */ RTUINT256_INIT_C(0, 0, 0, 0), 982 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, 983 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), 984 /* ^ */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), 985 /* = */ RTUINT256_INIT_C(0xDDDDEEEEFFFF8888, 0x9999AAAABBBBCCCC, 0x9999AAAABBBBCCCC, 0xddddeeeeffff8888) }, 986 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 987 /* ^ */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 988 /* = */ RTUINT256_INIT_C(0x5fddfdae6dff73d5, 0xfffc9fec667b7ff7, 0xbc21effbffddfbe3, 0xdfdfedf3b38d9fff) }, 989 }; 990 991 static BS3CPUINSTR3_TEST1_T const s_aTests16[] = 992 { 993 { bs3CpuInstr3_por_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 994 { bs3CpuInstr3_por_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 995 { bs3CpuInstr3_por_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 996 { bs3CpuInstr3_por_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 997 { bs3CpuInstr3_vpor_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 998 { bs3CpuInstr3_vpor_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 999 { bs3CpuInstr3_vpor_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, 1000 { bs3CpuInstr3_vpor_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1001 1002 { bs3CpuInstr3_orps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 1003 { bs3CpuInstr3_orps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1004 { bs3CpuInstr3_vorps_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 1005 { bs3CpuInstr3_vorps_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1006 { bs3CpuInstr3_vorps_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 1007 { bs3CpuInstr3_vorps_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1008 1009 { bs3CpuInstr3_orpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 1010 { bs3CpuInstr3_orpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1011 { bs3CpuInstr3_vorpd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, 1012 { bs3CpuInstr3_vorpd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1013 { bs3CpuInstr3_vorpd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, 1014 { bs3CpuInstr3_vorpd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1015 }; 1016 1017 # if ARCH_BITS >= 32 1018 static BS3CPUINSTR3_TEST1_T const s_aTests32[] = 1019 { 1020 { bs3CpuInstr3_por_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 1021 { bs3CpuInstr3_por_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1022 { bs3CpuInstr3_por_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 1023 { bs3CpuInstr3_por_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1024 { bs3CpuInstr3_vpor_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 1025 { bs3CpuInstr3_vpor_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1026 { bs3CpuInstr3_vpor_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, 1027 { bs3CpuInstr3_vpor_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1028 1029 { bs3CpuInstr3_orps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 1030 { bs3CpuInstr3_orps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1031 { bs3CpuInstr3_vorps_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 1032 { bs3CpuInstr3_vorps_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1033 { bs3CpuInstr3_vorps_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 1034 { bs3CpuInstr3_vorps_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1035 1036 { bs3CpuInstr3_orpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 1037 { bs3CpuInstr3_orpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1038 { bs3CpuInstr3_vorpd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, 1039 { bs3CpuInstr3_vorpd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1040 { bs3CpuInstr3_vorpd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, 1041 { bs3CpuInstr3_vorpd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1042 }; 1043 # endif 1044 # if ARCH_BITS >= 64 1045 static BS3CPUINSTR3_TEST1_T const s_aTests64[] = 1046 { 1047 { bs3CpuInstr3_por_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 1048 { bs3CpuInstr3_por_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1049 { bs3CpuInstr3_por_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 1050 { bs3CpuInstr3_por_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1051 { bs3CpuInstr3_vpor_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 1052 { bs3CpuInstr3_vpor_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1053 { bs3CpuInstr3_vpor_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, 1054 { bs3CpuInstr3_vpor_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1055 1056 { bs3CpuInstr3_orps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 1057 { bs3CpuInstr3_orps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1058 { bs3CpuInstr3_vorps_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 1059 { bs3CpuInstr3_vorps_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1060 { bs3CpuInstr3_vorps_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 1061 { bs3CpuInstr3_vorps_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1062 1063 { bs3CpuInstr3_orpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 1064 { bs3CpuInstr3_orpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1065 { bs3CpuInstr3_vorpd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, 1066 { bs3CpuInstr3_vorpd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1067 { bs3CpuInstr3_vorpd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, 1068 { bs3CpuInstr3_vorpd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 1069 { bs3CpuInstr3_vorpd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValues), s_aValues }, 1070 }; 1071 # endif 1072 1073 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 1074 unsigned const iTest = BS3CPUINSTR3_TEST1_MODES_INDEX(bMode); 1075 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 1076 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); 1077 } 1078 1079 1080 /* 1081 * PXOR, VPXOR, XORPS, VXORPS, XORPD, VXORPD. 682 1082 */ 683 1083 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr3_v_xorps_xorpd_pxor)(uint8_t bMode) -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac
r95401 r95439 60 60 %endif 61 61 62 63 %macro EMIT_TYPE1_INSTR 6 62 64 ; 63 65 ; PXOR (SSE2) & VPXOR (AVX2) 64 66 ; 65 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ pxor_MM1_MM2_icebp66 pxormm1, mm267 .again: 68 icebp 69 jmp .again 70 BS3_PROC_END_CMN bs3CpuInstr3_ pxor_MM1_MM2_icebp71 72 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ pxor_MM1_FSxBX_icebp73 pxormm1, [fs:xBX]74 .again: 75 icebp 76 jmp .again 77 BS3_PROC_END_CMN bs3CpuInstr3_ pxor_MM1_FSxBX_icebp78 79 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ pxor_XMM1_XMM2_icebp80 pxorxmm1, xmm281 .again: 82 icebp 83 jmp .again 84 BS3_PROC_END_CMN bs3CpuInstr3_ pxor_XMM1_XMM2_icebp85 86 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ pxor_XMM1_FSxBX_icebp87 pxorxmm1, [fs:xBX]88 .again: 89 icebp 90 jmp .again 91 BS3_PROC_END_CMN bs3CpuInstr3_ pxor_XMM1_FSxBX_icebp92 93 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ vpxor_XMM1_XMM1_XMM2_icebp94 vpxorxmm1, xmm1, xmm295 .again: 96 icebp 97 jmp .again 98 BS3_PROC_END_CMN bs3CpuInstr3_ vpxor_XMM1_XMM1_XMM2_icebp99 100 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ vpxor_XMM1_XMM1_FSxBX_icebp101 vpxorxmm1, xmm1, [fs:xBX]102 .again: 103 icebp 104 jmp .again 105 BS3_PROC_END_CMN bs3CpuInstr3_ vpxor_XMM1_XMM1_FSxBX_icebp106 107 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ vpxor_YMM7_YMM2_YMM3_icebp108 vpxorymm7, ymm2, ymm3109 .again: 110 icebp 111 jmp .again 112 BS3_PROC_END_CMN bs3CpuInstr3_ vpxor_YMM7_YMM2_YMM3_icebp113 114 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ vpxor_YMM7_YMM2_FSxBX_icebp115 vpxorymm7, ymm2, [fs:xBX]116 .again: 117 icebp 118 jmp .again 119 BS3_PROC_END_CMN bs3CpuInstr3_ vpxor_YMM7_YMM2_FSxBX_icebp67 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _MM1_MM2_icebp 68 %1 mm1, mm2 69 .again: 70 icebp 71 jmp .again 72 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _MM1_MM2_icebp 73 74 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _MM1_FSxBX_icebp 75 %1 mm1, [fs:xBX] 76 .again: 77 icebp 78 jmp .again 79 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _MM1_FSxBX_icebp 80 81 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _XMM1_XMM2_icebp 82 %1 xmm1, xmm2 83 .again: 84 icebp 85 jmp .again 86 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _XMM1_XMM2_icebp 87 88 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _XMM1_FSxBX_icebp 89 %1 xmm1, [fs:xBX] 90 .again: 91 icebp 92 jmp .again 93 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _XMM1_FSxBX_icebp 94 95 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %2 %+ _XMM1_XMM1_XMM2_icebp 96 %2 xmm1, xmm1, xmm2 97 .again: 98 icebp 99 jmp .again 100 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %2 %+ _XMM1_XMM1_XMM2_icebp 101 102 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %2 %+ _XMM1_XMM1_FSxBX_icebp 103 %2 xmm1, xmm1, [fs:xBX] 104 .again: 105 icebp 106 jmp .again 107 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %2 %+ _XMM1_XMM1_FSxBX_icebp 108 109 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %2 %+ _YMM7_YMM2_YMM3_icebp 110 %2 ymm7, ymm2, ymm3 111 .again: 112 icebp 113 jmp .again 114 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %2 %+ _YMM7_YMM2_YMM3_icebp 115 116 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %2 %+ _YMM7_YMM2_FSxBX_icebp 117 %2 ymm7, ymm2, [fs:xBX] 118 .again: 119 icebp 120 jmp .again 121 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %2 %+ _YMM7_YMM2_FSxBX_icebp 120 122 121 123 … … 123 125 ; XORPS (SSE2) & VXORPS (AVX) 124 126 ; 125 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ xorps_XMM1_XMM2_icebp126 xorpsxmm1, xmm2127 .again: 128 icebp 129 jmp .again 130 BS3_PROC_END_CMN bs3CpuInstr3_ xorps_XMM1_XMM2_icebp131 132 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ xorps_XMM1_FSxBX_icebp133 xorpsxmm1, [fs:xBX]134 .again: 135 icebp 136 jmp .again 137 BS3_PROC_END_CMN bs3CpuInstr3_ xorps_XMM1_FSxBX_icebp138 139 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ vxorps_XMM1_XMM1_XMM2_icebp140 vxorpsxmm1, xmm1, xmm2141 .again: 142 icebp 143 jmp .again 144 BS3_PROC_END_CMN bs3CpuInstr3_ vxorps_XMM1_XMM1_XMM2_icebp145 146 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ vxorps_XMM1_XMM1_FSxBX_icebp147 vxorpsxmm1, xmm1, [fs:xBX]148 .again: 149 icebp 150 jmp .again 151 BS3_PROC_END_CMN bs3CpuInstr3_ vxorps_XMM1_XMM1_FSxBX_icebp152 153 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ vxorps_YMM1_YMM1_YMM2_icebp154 vxorpsymm1, ymm1, ymm2155 .again: 156 icebp 157 jmp .again 158 BS3_PROC_END_CMN bs3CpuInstr3_ vxorps_YMM1_YMM1_YMM2_icebp159 160 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ vxorps_YMM1_YMM1_FSxBX_icebp161 vxorpsymm1, ymm1, [fs:xBX]162 .again: 163 icebp 164 jmp .again 165 BS3_PROC_END_CMN bs3CpuInstr3_ vxorps_YMM1_YMM1_FSxBX_icebp127 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %3 %+ _XMM1_XMM2_icebp 128 %3 xmm1, xmm2 129 .again: 130 icebp 131 jmp .again 132 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %3 %+ _XMM1_XMM2_icebp 133 134 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %3 %+ _XMM1_FSxBX_icebp 135 %3 xmm1, [fs:xBX] 136 .again: 137 icebp 138 jmp .again 139 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %3 %+ _XMM1_FSxBX_icebp 140 141 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %4 %+ _XMM1_XMM1_XMM2_icebp 142 %4 xmm1, xmm1, xmm2 143 .again: 144 icebp 145 jmp .again 146 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %4 %+ _XMM1_XMM1_XMM2_icebp 147 148 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %4 %+ _XMM1_XMM1_FSxBX_icebp 149 %4 xmm1, xmm1, [fs:xBX] 150 .again: 151 icebp 152 jmp .again 153 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %4 %+ _XMM1_XMM1_FSxBX_icebp 154 155 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %4 %+ _YMM1_YMM1_YMM2_icebp 156 %4 ymm1, ymm1, ymm2 157 .again: 158 icebp 159 jmp .again 160 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %4 %+ _YMM1_YMM1_YMM2_icebp 161 162 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %4 %+ _YMM1_YMM1_FSxBX_icebp 163 %4 ymm1, ymm1, [fs:xBX] 164 .again: 165 icebp 166 jmp .again 167 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %4 %+ _YMM1_YMM1_FSxBX_icebp 166 168 167 169 … … 170 172 ; XORPD (SSE2) & VXORPD (AVX) 171 173 ; 172 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ xorpd_XMM1_XMM2_icebp173 xorpdxmm1, xmm2174 .again: 175 icebp 176 jmp .again 177 BS3_PROC_END_CMN bs3CpuInstr3_ xorpd_XMM1_XMM2_icebp178 179 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ xorpd_XMM1_FSxBX_icebp180 xorpdxmm1, [fs:xBX]181 .again: 182 icebp 183 jmp .again 184 BS3_PROC_END_CMN bs3CpuInstr3_ xorpd_XMM1_FSxBX_icebp185 186 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ vxorpd_XMM2_XMM1_XMM0_icebp187 vxorpdxmm2, xmm1, xmm0188 .again: 189 icebp 190 jmp .again 191 BS3_PROC_END_CMN bs3CpuInstr3_ vxorpd_XMM2_XMM1_XMM0_icebp192 193 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ vxorpd_XMM2_XMM1_FSxBX_icebp194 vxorpdxmm2, xmm1, [fs:xBX]195 .again: 196 icebp 197 jmp .again 198 BS3_PROC_END_CMN bs3CpuInstr3_ vxorpd_XMM2_XMM1_FSxBX_icebp199 200 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ vxorpd_YMM2_YMM1_YMM0_icebp201 vxorpdymm2, ymm1, ymm0202 .again: 203 icebp 204 jmp .again 205 BS3_PROC_END_CMN bs3CpuInstr3_ vxorpd_YMM2_YMM1_YMM0_icebp206 207 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ vxorpd_YMM2_YMM1_FSxBX_icebp208 vxorpdymm2, ymm1, [fs:xBX]209 .again: 210 icebp 211 jmp .again 212 BS3_PROC_END_CMN bs3CpuInstr3_ vxorpd_YMM2_YMM1_FSxBX_icebp174 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %5 %+ _XMM1_XMM2_icebp 175 %5 xmm1, xmm2 176 .again: 177 icebp 178 jmp .again 179 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %5 %+ _XMM1_XMM2_icebp 180 181 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %5 %+ _XMM1_FSxBX_icebp 182 %5 xmm1, [fs:xBX] 183 .again: 184 icebp 185 jmp .again 186 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %5 %+ _XMM1_FSxBX_icebp 187 188 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %6 %+ _XMM2_XMM1_XMM0_icebp 189 %6 xmm2, xmm1, xmm0 190 .again: 191 icebp 192 jmp .again 193 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %6 %+ _XMM2_XMM1_XMM0_icebp 194 195 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %6 %+ _XMM2_XMM1_FSxBX_icebp 196 %6 xmm2, xmm1, [fs:xBX] 197 .again: 198 icebp 199 jmp .again 200 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %6 %+ _XMM2_XMM1_FSxBX_icebp 201 202 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %6 %+ _YMM2_YMM1_YMM0_icebp 203 %6 ymm2, ymm1, ymm0 204 .again: 205 icebp 206 jmp .again 207 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %6 %+ _YMM2_YMM1_YMM0_icebp 208 209 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %6 %+ _YMM2_YMM1_FSxBX_icebp 210 %6 ymm2, ymm1, [fs:xBX] 211 .again: 212 icebp 213 jmp .again 214 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %6 %+ _YMM2_YMM1_FSxBX_icebp 213 215 214 216 %if TMPL_BITS == 64 215 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ vxorpd_YMM10_YMM8_YMM15_icebp216 vxorpdymm10, ymm8, ymm15217 .again: 218 icebp 219 jmp .again 220 BS3_PROC_END_CMN bs3CpuInstr3_ vxorpd_YMM10_YMM8_YMM15_icebp217 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %6 %+ _YMM10_YMM8_YMM15_icebp 218 %6 ymm10, ymm8, ymm15 219 .again: 220 icebp 221 jmp .again 222 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %6 %+ _YMM10_YMM8_YMM15_icebp 221 223 %endif 222 224 225 %endmacro ; EMIT_TYPE1_INSTR 226 227 EMIT_TYPE1_INSTR pand, vpand, andps, vandps, andpd, vandpd 228 EMIT_TYPE1_INSTR pandn, vpandn, andnps, vandnps, andnpd, vandnpd 229 EMIT_TYPE1_INSTR por, vpor, orps, vorps, orpd, vorpd 230 EMIT_TYPE1_INSTR pxor, vpxor, xorps, vxorps, xorpd, vxorpd 231 232 233 223 234 %endif ; BS3_INSTANTIATING_CMN 224 235 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c
r95400 r95439 35 35 * Internal Functions * 36 36 *********************************************************************************************************************************/ 37 BS3TESTMODEBYMAX_PROTOTYPES_CMN(bs3CpuInstr3_v_andps_andpd_pand); 38 BS3TESTMODEBYMAX_PROTOTYPES_CMN(bs3CpuInstr3_v_andnps_andnpd_pandn); 39 BS3TESTMODEBYMAX_PROTOTYPES_CMN(bs3CpuInstr3_v_orps_orpd_por); 37 40 BS3TESTMODEBYMAX_PROTOTYPES_CMN(bs3CpuInstr3_v_xorps_xorpd_pxor); 38 41 … … 43 46 static const BS3TESTMODEBYMAXENTRY g_aTests[] = 44 47 { 45 BS3TESTMODEBYMAXENTRY_CMN("[v]xorps/[v]xorpd/[v]pxor", bs3CpuInstr3_v_xorps_xorpd_pxor), 48 BS3TESTMODEBYMAXENTRY_CMN("[v]andps/[v]andpd/[v]pand", bs3CpuInstr3_v_andps_andpd_pand), 49 BS3TESTMODEBYMAXENTRY_CMN("[v]andnps/[v]andnpd/[v]pandn", bs3CpuInstr3_v_andnps_andnpd_pandn), 50 BS3TESTMODEBYMAXENTRY_CMN("[v]orps/[v]orpd/[v]or", bs3CpuInstr3_v_orps_orpd_por), 51 BS3TESTMODEBYMAXENTRY_CMN("[v]xorps/[v]xorpd/[v]pxor", bs3CpuInstr3_v_xorps_xorpd_pxor), 46 52 }; 47 53
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