Changeset 95443 in vbox
- Timestamp:
- Jun 30, 2022 12:48:58 AM (3 years ago)
- svn:sync-xref-src-repo-rev:
- 152049
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 3 edited
-
bs3-cpu-instr-3-template.c (modified) (2 diffs)
-
bs3-cpu-instr-3-template.mac (modified) (5 diffs)
-
bs3-cpu-instr-3.c (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.c
r95439 r95443 212 212 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorpd_YMM2_YMM1_FSxBX_icebp); 213 213 extern FNBS3FAR bs3CpuInstr3_vxorpd_YMM10_YMM8_YMM15_icebp_c64; 214 215 /* [V]PCMPGT[BWD] */ 216 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtb_MM1_MM2_icebp); 217 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtb_MM1_FSxBX_icebp); 218 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtb_XMM1_XMM2_icebp); 219 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtb_XMM1_FSxBX_icebp); 220 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_XMM2_icebp); 221 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_FSxBX_icebp); 222 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_YMM3_icebp); 223 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_FSxBX_icebp); 224 225 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtw_MM1_MM2_icebp); 226 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtw_MM1_FSxBX_icebp); 227 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtw_XMM1_XMM2_icebp); 228 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtw_XMM1_FSxBX_icebp); 229 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_XMM2_icebp); 230 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_FSxBX_icebp); 231 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_YMM2_icebp); 232 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_FSxBX_icebp); 233 234 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtd_MM1_MM2_icebp); 235 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtd_MM1_FSxBX_icebp); 236 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtd_XMM1_XMM2_icebp); 237 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtd_XMM1_FSxBX_icebp); 238 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_XMM0_icebp); 239 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_FSxBX_icebp); 240 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_YMM0_icebp); 241 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_FSxBX_icebp); 242 extern FNBS3FAR bs3CpuInstr3_vpcmpgtd_YMM10_YMM8_YMM15_icebp_c64; 243 244 /* [V]PCMPEQ[BWD] */ 245 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqb_MM1_MM2_icebp); 246 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqb_MM1_FSxBX_icebp); 247 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqb_XMM1_XMM2_icebp); 248 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqb_XMM1_FSxBX_icebp); 249 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_XMM2_icebp); 250 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_FSxBX_icebp); 251 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_YMM3_icebp); 252 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_FSxBX_icebp); 253 254 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqw_MM1_MM2_icebp); 255 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqw_MM1_FSxBX_icebp); 256 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqw_XMM1_XMM2_icebp); 257 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqw_XMM1_FSxBX_icebp); 258 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_XMM2_icebp); 259 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_FSxBX_icebp); 260 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_YMM2_icebp); 261 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_FSxBX_icebp); 262 263 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqd_MM1_MM2_icebp); 264 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqd_MM1_FSxBX_icebp); 265 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqd_XMM1_XMM2_icebp); 266 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqd_XMM1_FSxBX_icebp); 267 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_XMM0_icebp); 268 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_FSxBX_icebp); 269 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_YMM0_icebp); 270 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_FSxBX_icebp); 271 extern FNBS3FAR bs3CpuInstr3_vpcmpeqd_YMM10_YMM8_YMM15_icebp_c64; 272 214 273 215 274 #endif … … 1185 1244 1186 1245 1246 1247 /* 1248 * PCMPGTB, VPCMPGTB, PCMPGTW, VPCMPGTW, PCMPGTD, VPCMPGTD. 1249 */ 1250 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr3_v_pcmpgtb_pcmpgtw_pcmpgtd)(uint8_t bMode) 1251 { 1252 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] = 1253 { 1254 { RTUINT256_INIT_C(0, 0, 0, 0), 1255 /* < */ RTUINT256_INIT_C(0, 0, 0, 0), 1256 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, 1257 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), 1258 /* < */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), 1259 /* = */ RTUINT256_INIT_C(0x000000000000ffff, 0x0000000000000000, 0x0000000000000000, 0x000000000000ffff) }, 1260 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 1261 /* < */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 1262 /* = */ RTUINT256_INIT_C(0x0000000000ff0000, 0x00ff00ff00ffffff, 0x000000ff0000ffff, 0xff000000ff00ffff) }, 1263 }; 1264 1265 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = 1266 { 1267 { RTUINT256_INIT_C(0, 0, 0, 0), 1268 /* < */ RTUINT256_INIT_C(0, 0, 0, 0), 1269 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, 1270 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), 1271 /* < */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), 1272 /* = */ RTUINT256_INIT_C(0x000000000000ffff, 0x0000000000000000, 0x0000000000000000, 0x000000000000ffff) }, 1273 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 1274 /* ^ */ RTUINT256_INIT_C(0x1eddddac77733294, 0xf95c8eec40725633, 0x3333e95bbf9962c3, 0x43d3cda0238499fd), /* modified 1st and 3rd value */ 1275 /* = */ RTUINT256_INIT_C(0x00000000ffff0000, 0x000000000000ffff, 0xffff00000000ffff, 0xffff0000ffffffff) }, 1276 }; 1277 1278 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = 1279 { 1280 { RTUINT256_INIT_C(0, 0, 0, 0), 1281 /* < */ RTUINT256_INIT_C(0, 0, 0, 0), 1282 /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, 1283 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), 1284 /* < */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), 1285 /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, 1286 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 1287 /* < */ RTUINT256_INIT_C(0x555dddac09633294, 0xf95c8eec77725633, 0x7770e95bbf9962c3, 0x43d3cda0238499fd), /* modified 1st, 2nd and 3rd value */ 1288 /* = */ RTUINT256_INIT_C(0xffffffff00000000, 0x00000000ffffffff, 0xffffffff00000000, 0xffffffffffffffff) }, 1289 }; 1290 1291 static BS3CPUINSTR3_TEST1_T const s_aTests16[] = 1292 { 1293 { bs3CpuInstr3_pcmpgtb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1294 { bs3CpuInstr3_pcmpgtb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1295 { bs3CpuInstr3_pcmpgtb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1296 { bs3CpuInstr3_pcmpgtb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1297 { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1298 { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1299 { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1300 { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1301 1302 { bs3CpuInstr3_pcmpgtw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1303 { bs3CpuInstr3_pcmpgtw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1304 { bs3CpuInstr3_pcmpgtw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1305 { bs3CpuInstr3_pcmpgtw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1306 { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1307 { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1308 { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1309 { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1310 1311 { bs3CpuInstr3_pcmpgtd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1312 { bs3CpuInstr3_pcmpgtd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1313 { bs3CpuInstr3_pcmpgtd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1314 { bs3CpuInstr3_pcmpgtd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1315 { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1316 { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1317 { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1318 { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1319 }; 1320 1321 # if ARCH_BITS >= 32 1322 static BS3CPUINSTR3_TEST1_T const s_aTests32[] = 1323 { 1324 { bs3CpuInstr3_pcmpgtb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1325 { bs3CpuInstr3_pcmpgtb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1326 { bs3CpuInstr3_pcmpgtb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1327 { bs3CpuInstr3_pcmpgtb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1328 { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1329 { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1330 { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1331 { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1332 1333 { bs3CpuInstr3_pcmpgtw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1334 { bs3CpuInstr3_pcmpgtw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1335 { bs3CpuInstr3_pcmpgtw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1336 { bs3CpuInstr3_pcmpgtw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1337 { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1338 { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1339 { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1340 { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1341 1342 { bs3CpuInstr3_pcmpgtd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1343 { bs3CpuInstr3_pcmpgtd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1344 { bs3CpuInstr3_pcmpgtd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1345 { bs3CpuInstr3_pcmpgtd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1346 { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1347 { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1348 { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1349 { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1350 }; 1351 # endif 1352 # if ARCH_BITS >= 64 1353 static BS3CPUINSTR3_TEST1_T const s_aTests64[] = 1354 { 1355 { bs3CpuInstr3_pcmpgtb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1356 { bs3CpuInstr3_pcmpgtb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1357 { bs3CpuInstr3_pcmpgtb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1358 { bs3CpuInstr3_pcmpgtb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1359 { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1360 { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1361 { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1362 { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1363 1364 { bs3CpuInstr3_pcmpgtw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1365 { bs3CpuInstr3_pcmpgtw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1366 { bs3CpuInstr3_pcmpgtw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1367 { bs3CpuInstr3_pcmpgtw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1368 { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1369 { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1370 { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1371 { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1372 1373 { bs3CpuInstr3_pcmpgtd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1374 { bs3CpuInstr3_pcmpgtd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1375 { bs3CpuInstr3_pcmpgtd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1376 { bs3CpuInstr3_pcmpgtd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1377 { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1378 { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1379 { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1380 { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1381 { bs3CpuInstr3_vpcmpgtd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1382 }; 1383 # endif 1384 1385 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 1386 unsigned const iTest = BS3CPUINSTR3_TEST1_MODES_INDEX(bMode); 1387 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 1388 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); 1389 } 1390 1391 1392 /* 1393 * PCMPEQB, VPCMPEQB, PCMPEQW, VPCMPEQW, PCMPEQD, VPCMPEQD. 1394 */ 1395 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr3_v_pcmpeqb_pcmpeqw_pcmpeqd)(uint8_t bMode) 1396 { 1397 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] = 1398 { 1399 { RTUINT256_INIT_C(0, 0, 0, 0), 1400 /* ==*/ RTUINT256_INIT_C(0, 0, 0, 0), 1401 /* = */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, 1402 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), 1403 /* ==*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), 1404 /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, 1405 { RTUINT256_INIT_C(0x4dddf02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 1406 /* ==*/ RTUINT256_INIT_C(0x1eddddac09dc3294, 0xf95c17ec667256e6, 0xb400e95bbf999bc3, 0x9cd3cda0230999fd), /* modified all to get some matches */ 1407 /* = */ RTUINT256_INIT_C(0x00ff000000ff0000, 0x0000ff00ff0000ff, 0xff0000000000ff00, 0xff00000000ff0000) }, 1408 }; 1409 1410 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = 1411 { 1412 { RTUINT256_INIT_C(0, 0, 0, 0), 1413 /* ==*/ RTUINT256_INIT_C(0, 0, 0, 0), 1414 /* = */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, 1415 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), 1416 /* ==*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), 1417 /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, 1418 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 1419 /* ==*/ RTUINT256_INIT_C(0x1eddf02a6cdc3294, 0x3ef48eec666b5633, 0x88002fa8bf999ba2, 0x9c5ccda0238496bb), /* modified all to get some matches */ 1420 /* = */ RTUINT256_INIT_C(0x0000ffffffff0000, 0xffff0000ffff0000, 0x0000ffff0000ffff, 0xffff00000000ffff) }, 1421 }; 1422 1423 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = 1424 { 1425 { RTUINT256_INIT_C(0, 0, 0, 0), 1426 /* ==*/ RTUINT256_INIT_C(0, 0, 0, 0), 1427 /* = */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, 1428 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), 1429 /* ==*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), 1430 /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, 1431 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 1432 /* ==*/ RTUINT256_INIT_C(0x4d09f02a09633294, 0x3ef417c8666b3fe6, 0x8800e95b564c9ba2, 0x9c5ce073238499fd), /* modified all to get some matches */ 1433 /* = */ RTUINT256_INIT_C(0xffffffff00000000, 0xffffffffffffffff, 0x00000000ffffffff, 0xffffffff00000000) }, 1434 }; 1435 1436 static BS3CPUINSTR3_TEST1_T const s_aTests16[] = 1437 { 1438 { bs3CpuInstr3_pcmpeqb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1439 { bs3CpuInstr3_pcmpeqb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1440 { bs3CpuInstr3_pcmpeqb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1441 { bs3CpuInstr3_pcmpeqb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1442 { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1443 { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1444 { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1445 { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1446 1447 { bs3CpuInstr3_pcmpeqw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1448 { bs3CpuInstr3_pcmpeqw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1449 { bs3CpuInstr3_pcmpeqw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1450 { bs3CpuInstr3_pcmpeqw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1451 { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1452 { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1453 { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1454 { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1455 1456 { bs3CpuInstr3_pcmpeqd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1457 { bs3CpuInstr3_pcmpeqd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1458 { bs3CpuInstr3_pcmpeqd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1459 { bs3CpuInstr3_pcmpeqd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1460 { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1461 { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1462 { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1463 { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1464 }; 1465 1466 # if ARCH_BITS >= 32 1467 static BS3CPUINSTR3_TEST1_T const s_aTests32[] = 1468 { 1469 { bs3CpuInstr3_pcmpeqb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1470 { bs3CpuInstr3_pcmpeqb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1471 { bs3CpuInstr3_pcmpeqb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1472 { bs3CpuInstr3_pcmpeqb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1473 { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1474 { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1475 { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1476 { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1477 1478 { bs3CpuInstr3_pcmpeqw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1479 { bs3CpuInstr3_pcmpeqw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1480 { bs3CpuInstr3_pcmpeqw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1481 { bs3CpuInstr3_pcmpeqw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1482 { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1483 { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1484 { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1485 { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1486 1487 { bs3CpuInstr3_pcmpeqd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1488 { bs3CpuInstr3_pcmpeqd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1489 { bs3CpuInstr3_pcmpeqd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1490 { bs3CpuInstr3_pcmpeqd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1491 { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1492 { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1493 { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1494 { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1495 }; 1496 # endif 1497 # if ARCH_BITS >= 64 1498 static BS3CPUINSTR3_TEST1_T const s_aTests64[] = 1499 { 1500 { bs3CpuInstr3_pcmpeqb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1501 { bs3CpuInstr3_pcmpeqb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1502 { bs3CpuInstr3_pcmpeqb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1503 { bs3CpuInstr3_pcmpeqb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1504 { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1505 { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1506 { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1507 { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, 1508 1509 { bs3CpuInstr3_pcmpeqw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1510 { bs3CpuInstr3_pcmpeqw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1511 { bs3CpuInstr3_pcmpeqw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1512 { bs3CpuInstr3_pcmpeqw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1513 { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1514 { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1515 { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1516 { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, 1517 1518 { bs3CpuInstr3_pcmpeqd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1519 { bs3CpuInstr3_pcmpeqd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1520 { bs3CpuInstr3_pcmpeqd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1521 { bs3CpuInstr3_pcmpeqd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1522 { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1523 { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1524 { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1525 { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1526 { bs3CpuInstr3_vpcmpeqd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 1527 }; 1528 # endif 1529 1530 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 1531 unsigned const iTest = BS3CPUINSTR3_TEST1_MODES_INDEX(bMode); 1532 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 1533 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); 1534 } 1535 1536 1187 1537 #endif /* BS3_INSTANTIATING_CMN */ 1188 1538 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac
r95439 r95443 61 61 62 62 63 %macro EMIT_TYPE1_INSTR 6 63 %ifndef EMIT_TYPE1_INSTR_DEFINED 64 %define EMIT_TYPE1_INSTR_DEFINED 65 ;; @param 7 Indicates whether the 2nd and 3rd pair has MMX variants. 66 %macro EMIT_TYPE1_INSTR 7 64 67 ; 65 68 ; PXOR (SSE2) & VPXOR (AVX2) … … 125 128 ; XORPS (SSE2) & VXORPS (AVX) 126 129 ; 130 %if %7 != 0 131 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %3 %+ _MM1_MM2_icebp 132 %3 mm1, mm2 133 .again: 134 icebp 135 jmp .again 136 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %3 %+ _MM1_MM2_icebp 137 138 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %3 %+ _MM1_FSxBX_icebp 139 %3 mm1, [fs:xBX] 140 .again: 141 icebp 142 jmp .again 143 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %3 %+ _MM1_FSxBX_icebp 144 %endif 145 127 146 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %3 %+ _XMM1_XMM2_icebp 128 147 %3 xmm1, xmm2 … … 172 191 ; XORPD (SSE2) & VXORPD (AVX) 173 192 ; 193 %if %7 != 0 194 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %5 %+ _MM1_MM2_icebp 195 %5 mm1, mm2 196 .again: 197 icebp 198 jmp .again 199 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %5 %+ _MM1_MM2_icebp 200 201 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %5 %+ _MM1_FSxBX_icebp 202 %5 mm1, [fs:xBX] 203 .again: 204 icebp 205 jmp .again 206 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %5 %+ _MM1_FSxBX_icebp 207 %endif 208 174 209 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %5 %+ _XMM1_XMM2_icebp 175 210 %5 xmm1, xmm2 … … 214 249 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %6 %+ _YMM2_YMM1_FSxBX_icebp 215 250 216 %if TMPL_BITS == 64251 %if TMPL_BITS == 64 217 252 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %6 %+ _YMM10_YMM8_YMM15_icebp 218 253 %6 ymm10, ymm8, ymm15 … … 221 256 jmp .again 222 257 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %6 %+ _YMM10_YMM8_YMM15_icebp 223 %endif 224 225 %endmacro ; EMIT_TYPE1_INSTR 226 227 EMIT_TYPE1_INSTR pand, vpand, andps, vandps, andpd, vandpd 228 EMIT_TYPE1_INSTR pandn, vpandn, andnps, vandnps, andnpd, vandnpd 229 EMIT_TYPE1_INSTR por, vpor, orps, vorps, orpd, vorpd 230 EMIT_TYPE1_INSTR pxor, vpxor, xorps, vxorps, xorpd, vxorpd 258 %endif 259 260 %endmacro ; EMIT_TYPE1_INSTR 261 %endif 262 263 EMIT_TYPE1_INSTR pand, vpand, andps, vandps, andpd, vandpd, 0 264 EMIT_TYPE1_INSTR pandn, vpandn, andnps, vandnps, andnpd, vandnpd, 0 265 EMIT_TYPE1_INSTR por, vpor, orps, vorps, orpd, vorpd, 0 266 EMIT_TYPE1_INSTR pxor, vpxor, xorps, vxorps, xorpd, vxorpd, 0 267 268 EMIT_TYPE1_INSTR pcmpgtb, vpcmpgtb, pcmpgtw, vpcmpgtw, pcmpgtd, vpcmpgtd, 1 269 EMIT_TYPE1_INSTR pcmpeqb, vpcmpeqb, pcmpeqw, vpcmpeqw, pcmpeqd, vpcmpeqd, 1 231 270 232 271 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c
r95439 r95443 39 39 BS3TESTMODEBYMAX_PROTOTYPES_CMN(bs3CpuInstr3_v_orps_orpd_por); 40 40 BS3TESTMODEBYMAX_PROTOTYPES_CMN(bs3CpuInstr3_v_xorps_xorpd_pxor); 41 BS3TESTMODEBYMAX_PROTOTYPES_CMN(bs3CpuInstr3_v_pcmpgtb_pcmpgtw_pcmpgtd); 42 BS3TESTMODEBYMAX_PROTOTYPES_CMN(bs3CpuInstr3_v_pcmpeqb_pcmpeqw_pcmpeqd); 41 43 42 44 … … 46 48 static const BS3TESTMODEBYMAXENTRY g_aTests[] = 47 49 { 50 #if 1 48 51 BS3TESTMODEBYMAXENTRY_CMN("[v]andps/[v]andpd/[v]pand", bs3CpuInstr3_v_andps_andpd_pand), 49 52 BS3TESTMODEBYMAXENTRY_CMN("[v]andnps/[v]andnpd/[v]pandn", bs3CpuInstr3_v_andnps_andnpd_pandn), 50 53 BS3TESTMODEBYMAXENTRY_CMN("[v]orps/[v]orpd/[v]or", bs3CpuInstr3_v_orps_orpd_por), 51 54 BS3TESTMODEBYMAXENTRY_CMN("[v]xorps/[v]xorpd/[v]pxor", bs3CpuInstr3_v_xorps_xorpd_pxor), 55 #endif 56 #if 1 57 BS3TESTMODEBYMAXENTRY_CMN("[v]pcmpgtb/[v]pcmpgtw/[v]pcmpgtd", bs3CpuInstr3_v_pcmpgtb_pcmpgtw_pcmpgtd), 58 BS3TESTMODEBYMAXENTRY_CMN("[v]pcmpeqb/[v]pcmpeqw/[v]pcmpeqd", bs3CpuInstr3_v_pcmpeqb_pcmpeqw_pcmpeqd), 59 #endif 52 60 }; 53 61
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