Changeset 95485 in vbox for trunk/src/VBox/ValidationKit/bootsectors
- Timestamp:
- Jul 3, 2022 1:58:25 PM (3 years ago)
- svn:sync-xref-src-repo-rev:
- 152099
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 5 edited
-
bs3-cpu-instr-3-template.c (modified) (7 diffs)
-
bs3-cpu-instr-3-template.mac (modified) (2 diffs)
-
bs3-cpu-instr-3.c (modified) (3 diffs)
-
bs3kit/bs3-cmn-ExtCtxSetMm.c (modified) (2 diffs)
-
bs3kit/bs3kit.h (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.c
r95481 r95485 378 378 extern FNBS3FAR bs3CpuInstr3_vpmovmskb_RAX_YMM9_icebp_c64; 379 379 380 381 /* PSHUFW */ 382 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufw_MM1_MM2_0FFh_icebp); 383 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufw_MM1_FSxBX_0FFh_icebp); 384 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufw_MM1_MM2_01Bh_icebp); 385 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufw_MM1_FSxBX_01Bh_icebp); 386 387 /* [V]PSHUFHW */ 388 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufhw_XMM1_XMM2_0FFh_icebp); 389 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufhw_XMM1_FSxBX_0FFh_icebp); 390 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufhw_XMM1_XMM2_01Bh_icebp); 391 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufhw_XMM1_FSxBX_01Bh_icebp); 392 393 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_XMM1_XMM2_0FFh_icebp); 394 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_XMM1_FSxBX_0FFh_icebp); 395 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_XMM1_XMM2_01Bh_icebp); 396 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_XMM1_FSxBX_01Bh_icebp); 397 398 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_YMM1_YMM2_0FFh_icebp); 399 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_YMM1_FSxBX_0FFh_icebp); 400 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_YMM1_YMM2_01Bh_icebp); 401 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_YMM1_FSxBX_01Bh_icebp); 402 extern FNBS3FAR bs3CpuInstr3_vpshufhw_YMM12_YMM7_0FFh_icebp_c64; 403 extern FNBS3FAR bs3CpuInstr3_vpshufhw_YMM9_YMM12_01Bh_icebp_c64; 404 405 /* [V]PSHUFLW */ 406 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshuflw_XMM1_XMM2_0FFh_icebp); 407 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshuflw_XMM1_FSxBX_0FFh_icebp); 408 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshuflw_XMM1_XMM2_01Bh_icebp); 409 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshuflw_XMM1_FSxBX_01Bh_icebp); 410 411 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_XMM1_XMM2_0FFh_icebp); 412 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_XMM1_FSxBX_0FFh_icebp); 413 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_XMM1_XMM2_01Bh_icebp); 414 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_XMM1_FSxBX_01Bh_icebp); 415 416 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_YMM1_YMM2_0FFh_icebp); 417 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_YMM1_FSxBX_0FFh_icebp); 418 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_YMM1_YMM2_01Bh_icebp); 419 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_YMM1_FSxBX_01Bh_icebp); 420 extern FNBS3FAR bs3CpuInstr3_vpshuflw_YMM12_YMM7_0FFh_icebp_c64; 421 extern FNBS3FAR bs3CpuInstr3_vpshuflw_YMM9_YMM12_01Bh_icebp_c64; 422 423 /* [V]PSHUFD */ 424 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufd_XMM1_XMM2_0FFh_icebp); 425 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufd_XMM1_FSxBX_0FFh_icebp); 426 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufd_XMM1_XMM2_01Bh_icebp); 427 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufd_XMM1_FSxBX_01Bh_icebp); 428 429 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_XMM1_XMM2_0FFh_icebp); 430 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_XMM1_FSxBX_0FFh_icebp); 431 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_XMM1_XMM2_01Bh_icebp); 432 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_XMM1_FSxBX_01Bh_icebp); 433 434 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_YMM1_YMM2_0FFh_icebp); 435 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_YMM1_FSxBX_0FFh_icebp); 436 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_YMM1_YMM2_01Bh_icebp); 437 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_YMM1_FSxBX_01Bh_icebp); 438 extern FNBS3FAR bs3CpuInstr3_vpshufd_YMM12_YMM7_0FFh_icebp_c64; 439 extern FNBS3FAR bs3CpuInstr3_vpshufd_YMM9_YMM12_01Bh_icebp_c64; 380 440 381 441 #endif … … 801 861 uMemOpExpect = *puMemOp; 802 862 } 863 else if (fMmxInstr) 864 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc2, ~paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_ZERO); 803 865 804 866 /* source #1 (/ destination for MMX and SSE) */ … … 813 875 } 814 876 else if (fMmxInstr) 815 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc1, paValues[iVal].uSrc1.QWords.qw0 );877 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc1, paValues[iVal].uSrc1.QWords.qw0, BS3EXTCTXTOPMM_ZERO); 816 878 else if (fSseInstr) 817 879 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1.DQWords.dqw0); … … 828 890 } 829 891 else if (fMmxInstr) 830 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc2, paValues[iVal].uSrc2.QWords.qw0 );892 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc2, paValues[iVal].uSrc2.QWords.qw0, BS3EXTCTXTOPMM_ZERO); 831 893 else if (fSseInstr) 832 894 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2.DQWords.dqw0); … … 855 917 cErrors = Bs3TestSubErrorCount(); 856 918 919 if (bXcptExpect == X86_XCPT_DB) 920 { 921 uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx); 922 Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff); /* Observed on 10980xe after pxor mm1, mm2. */ 923 } 857 924 if (bXcptExpect == X86_XCPT_DB && paTests[iTest].iRegDst != UINT8_MAX) 858 925 { 859 926 if (fMmxInstr) 860 { 861 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegDst, paValues[iVal].uDstOut.QWords.qw0); 862 uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx); 863 Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff); /* Observed on 10980xe after pxor mm1, mm2. */ 864 } 927 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegDst, paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_SET); 865 928 else if (fSseInstr) 866 929 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut.DQWords.dqw0); … … 2262 2325 } 2263 2326 else if (fMmxInstr) 2264 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc, paValues[iVal].uSrc.QWords.qw0 );2327 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc, paValues[iVal].uSrc.QWords.qw0, BS3EXTCTXTOPMM_ZERO); 2265 2328 else if (fSseInstr) 2266 2329 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc, &paValues[iVal].uSrc.DQWords.dqw0); … … 2412 2475 2413 2476 2477 /* 2478 * Test type #3. 2479 */ 2480 2481 typedef struct BS3CPUINSTR3_TEST3_VALUES_T 2482 { 2483 RTUINT256U uSrc; 2484 RTUINT256U uDstOut; 2485 } BS3CPUINSTR3_TEST3_VALUES_T; 2486 2487 typedef struct BS3CPUINSTR3_TEST3_T 2488 { 2489 FPFNBS3FAR pfnWorker; 2490 uint8_t bAvxMisalignXcpt; 2491 uint8_t enmRm; 2492 uint8_t enmType; 2493 uint8_t iRegDst; 2494 uint8_t iRegSrc; 2495 uint8_t cValues; 2496 BS3CPUINSTR3_TEST3_VALUES_T const BS3_FAR *paValues; 2497 } BS3CPUINSTR3_TEST3_T; 2498 2499 typedef struct BS3CPUINSTR3_TEST3_MODE_T 2500 { 2501 BS3CPUINSTR3_TEST3_T const BS3_FAR *paTests; 2502 unsigned cTests; 2503 } BS3CPUINSTR3_TEST3_MODE_T; 2504 2505 /** Initializer for a BS3CPUINSTR3_TEST3_MODE_T array (three entries). */ 2506 #if ARCH_BITS == 16 2507 # define BS3CPUINSTR3_TEST3_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \ 2508 { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { NULL, 0 }, { NULL, 0 } } 2509 #elif ARCH_BITS == 32 2510 # define BS3CPUINSTR3_TEST3_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \ 2511 { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { NULL, 0 } } 2512 #else 2513 # define BS3CPUINSTR3_TEST3_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \ 2514 { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } } 2515 #endif 2516 2517 /** Converts an execution mode (BS3_MODE_XXX) into an index into an array 2518 * initialized by BS3CPUINSTR3_TEST3_MODES_INIT. */ 2519 #define BS3CPUINSTR3_TEST3_MODES_INDEX(a_bMode) \ 2520 (BS3_MODE_IS_16BIT_CODE(bMode) ? 0 : BS3_MODE_IS_32BIT_CODE(bMode) ? 1 : 2) 2521 2522 2523 /** 2524 * Test type #1 worker. 2525 */ 2526 static uint8_t bs3CpuInstr3_WorkerTestType3(uint8_t bMode, BS3CPUINSTR3_TEST3_T const BS3_FAR *paTests, unsigned cTests, 2527 PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs) 2528 { 2529 const char BS3_FAR * const pszMode = Bs3GetModeName(bMode); 2530 BS3REGCTX Ctx; 2531 BS3TRAPFRAME TrapFrame; 2532 uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0; 2533 PBS3EXTCTX pExtCtxOut; 2534 PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut); 2535 if (!pExtCtx) 2536 return 0; 2537 2538 /* Ensure the structures are allocated before we sample the stack pointer. */ 2539 Bs3MemSet(&Ctx, 0, sizeof(Ctx)); 2540 Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); 2541 2542 /* Ensure that the globals we use here have been initialized. */ 2543 bs3CpuInstr3InitGlobals(); 2544 2545 /* 2546 * Create test context. 2547 */ 2548 Bs3RegCtxSaveEx(&Ctx, bMode, 1024); 2549 bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx); 2550 2551 /* 2552 * Run the tests in all rings since alignment issues may behave 2553 * differently in ring-3 compared to ring-0. 2554 */ 2555 for (;;) 2556 { 2557 unsigned iCfg; 2558 for (iCfg = 0; iCfg < cConfigs; iCfg++) 2559 { 2560 unsigned iTest; 2561 BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg; 2562 if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode)) 2563 continue; /* unsupported config */ 2564 2565 /* 2566 * Iterate the tests. 2567 */ 2568 for (iTest = 0; iTest < cTests; iTest++) 2569 { 2570 BS3CPUINSTR3_TEST3_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues; 2571 uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1]; 2572 unsigned const cValues = paTests[iTest].cValues; 2573 bool const fMmxInstr = paTests[iTest].enmType < T_SSE; 2574 bool const fSseInstr = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128; 2575 bool const fAvxInstr = paTests[iTest].enmType >= T_AVX_128; 2576 uint8_t const cbOperand = paTests[iTest].enmType < T_128BITS ? 64/8 2577 : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8; 2578 uint8_t const cbAlign = RT_MIN(cbOperand, 16); 2579 uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType] ? X86_XCPT_UD 2580 : fMmxInstr ? paConfigs[iCfg].bXcptMmx 2581 : fSseInstr ? paConfigs[iCfg].bXcptSse 2582 : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx; 2583 uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10; 2584 unsigned iVal; 2585 uint8_t abPadding[sizeof(RTUINT256U) * 2]; 2586 unsigned const offPadding = (BS3_FP_OFF(&abPadding[sizeof(RTUINT256U)]) & ~(size_t)(cbAlign - 1)) 2587 - BS3_FP_OFF(&abPadding[0]); 2588 PRTUINT256U puMemOp = (PRTUINT256U)&abPadding[offPadding - !paConfigs[iCfg].fAligned]; 2589 BS3_ASSERT((uint8_t BS3_FAR *)puMemOp - &abPadding[0] <= sizeof(RTUINT256U)); 2590 2591 /* If testing unaligned memory accesses, skip register-only tests. This allows 2592 setting bXcptMmx, bXcptSse and bXcptAvx to reflect the misaligned exceptions. */ 2593 if (!paConfigs[iCfg].fAligned && paTests[iTest].enmRm != RM_MEM) 2594 continue; 2595 2596 /* #AC is only raised in ring-3.: */ 2597 if (bXcptExpect == X86_XCPT_AC) 2598 { 2599 if (bRing != 3) 2600 bXcptExpect = X86_XCPT_DB; 2601 else if (fAvxInstr) 2602 bXcptExpect = paTests[iTest].bAvxMisalignXcpt; /* they generally don't raise #AC */ 2603 } 2604 2605 Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker); 2606 2607 /* 2608 * Iterate the test values and do the actual testing. 2609 */ 2610 for (iVal = 0; iVal < cValues; iVal++, idTestStep++) 2611 { 2612 uint16_t cErrors; 2613 uint16_t uSavedFtw = 0xff; 2614 RTUINT256U uMemOpExpect; 2615 2616 /* 2617 * Set up the context and some expectations. 2618 */ 2619 /* dest */ 2620 if (paTests[iTest].iRegDst == UINT8_MAX) 2621 { 2622 BS3_ASSERT(paTests[iTest].enmRm == RM_MEM); 2623 Bs3MemSet(puMemOp, sizeof(*puMemOp), 0xcc); 2624 if (bXcptExpect == X86_XCPT_DB) 2625 uMemOpExpect = paValues[iVal].uDstOut; 2626 else 2627 uMemOpExpect = *puMemOp; 2628 } 2629 else if (fMmxInstr) 2630 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc, ~paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_ZERO); 2631 2632 /* source */ 2633 if (paTests[iTest].iRegSrc == UINT8_MAX) 2634 { 2635 BS3_ASSERT(paTests[iTest].enmRm == RM_MEM); 2636 BS3_ASSERT(paTests[iTest].iRegDst != UINT8_MAX); 2637 *puMemOp = uMemOpExpect = paValues[iVal].uSrc; 2638 uMemOpExpect = paValues[iVal].uSrc; 2639 } 2640 else if (fMmxInstr) 2641 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc, paValues[iVal].uSrc.QWords.qw0, BS3EXTCTXTOPMM_ZERO); 2642 else if (fSseInstr) 2643 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc, &paValues[iVal].uSrc.DQWords.dqw0); 2644 else 2645 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc, &paValues[iVal].uSrc, 32); 2646 2647 /* Memory pointer. */ 2648 if (paTests[iTest].enmRm == RM_MEM) 2649 { 2650 BS3_ASSERT( paTests[iTest].iRegDst == UINT8_MAX 2651 || paTests[iTest].iRegSrc == UINT8_MAX); 2652 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp); 2653 } 2654 2655 /* 2656 * Execute. 2657 */ 2658 Bs3ExtCtxRestore(pExtCtx); 2659 Bs3TrapSetJmpAndRestore(&Ctx, &TrapFrame); 2660 Bs3ExtCtxSave(pExtCtxOut); 2661 2662 /* 2663 * Check the result: 2664 */ 2665 cErrors = Bs3TestSubErrorCount(); 2666 2667 if (bXcptExpect == X86_XCPT_DB && fMmxInstr) 2668 { 2669 uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx); 2670 Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff); 2671 } 2672 if (bXcptExpect == X86_XCPT_DB && paTests[iTest].iRegDst != UINT8_MAX) 2673 { 2674 if (fMmxInstr) 2675 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegDst, paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_SET); 2676 else if (fSseInstr) 2677 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut.DQWords.dqw0); 2678 else 2679 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut, cbOperand); 2680 } 2681 Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep); 2682 2683 if (TrapFrame.bXcpt != bXcptExpect) 2684 Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt); 2685 2686 /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */ 2687 if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC)) 2688 { 2689 if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC) 2690 Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt); 2691 TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC; 2692 } 2693 Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0, 2694 bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF, 2695 pszMode, idTestStep); 2696 2697 if ( paTests[iTest].enmRm == RM_MEM 2698 && Bs3MemCmp(puMemOp, &uMemOpExpect, cbOperand) != 0) 2699 Bs3TestFailedF("Expected uMemOp %*.Rhxs, got %*.Rhxs", cbOperand, &uMemOpExpect, cbOperand, puMemOp); 2700 2701 if (cErrors != Bs3TestSubErrorCount()) 2702 { 2703 if (paConfigs[iCfg].fAligned) 2704 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x)", 2705 bRing, iCfg, iTest, iVal, bXcptExpect); 2706 else 2707 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)", 2708 bRing, iCfg, iTest, iVal, bXcptExpect, puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0); 2709 Bs3TestPrintf("\n"); 2710 } 2711 2712 if (uSavedFtw != 0xff) 2713 Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw); 2714 } 2715 } 2716 2717 bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx); 2718 } 2719 2720 /* 2721 * Next ring. 2722 */ 2723 bRing++; 2724 if (bRing > 3 || bMode == BS3_MODE_RM) 2725 break; 2726 Bs3RegCtxConvertToRingX(&Ctx, bRing); 2727 } 2728 2729 /* 2730 * Cleanup. 2731 */ 2732 bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut); 2733 return 0; 2734 } 2735 2736 2737 /* 2738 * PSHUFW 2739 */ 2740 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr3_pshufw)(uint8_t bMode) 2741 { 2742 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesFF[] = 2743 { 2744 { RTUINT256_INIT_C(0, 0, 0, 0), 2745 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 2746 { RTUINT256_INIT_C(0, 0, 0, 0xffffffffffffffff), 2747 /* => */ RTUINT256_INIT_C(0, 0, 0, 0xffffffffffffffff) }, 2748 { RTUINT256_INIT_C(0, 0, 0, 0x5555666677778888), 2749 /* => */ RTUINT256_INIT_C(0, 0, 0, 0x5555555555555555) }, 2750 { RTUINT256_INIT_C(0, 0, 0, 0x9c5ce073930996bb), 2751 /* => */ RTUINT256_INIT_C(0, 0, 0, 0x9c5c9c5c9c5c9c5c) }, 2752 }; 2753 2754 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues1B[] = 2755 { 2756 { RTUINT256_INIT_C(0, 0, 0, 0), 2757 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 2758 { RTUINT256_INIT_C(0, 0, 0, 0xffffffffffffffff), 2759 /* => */ RTUINT256_INIT_C(0, 0, 0, 0xffffffffffffffff) }, 2760 { RTUINT256_INIT_C(0, 0, 0, 0x5555666677778888), 2761 /* => */ RTUINT256_INIT_C(0, 0, 0, 0x8888777766665555) }, 2762 { RTUINT256_INIT_C(0, 0, 0, 0x9c5ce073930996bb), 2763 /* => */ RTUINT256_INIT_C(0, 0, 0, 0x96bb9309e0739c5c) }, 2764 }; 2765 2766 static BS3CPUINSTR3_TEST3_T const s_aTests16[] = 2767 { 2768 { bs3CpuInstr3_pshufw_MM1_MM2_0FFh_icebp_c16, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2769 { bs3CpuInstr3_pshufw_MM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2770 { bs3CpuInstr3_pshufw_MM1_MM2_01Bh_icebp_c16, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2771 { bs3CpuInstr3_pshufw_MM1_FSxBX_01Bh_icebp_c16, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2772 }; 2773 # if ARCH_BITS >= 32 2774 static BS3CPUINSTR3_TEST3_T const s_aTests32[] = 2775 { 2776 { bs3CpuInstr3_pshufw_MM1_MM2_0FFh_icebp_c32, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2777 { bs3CpuInstr3_pshufw_MM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2778 { bs3CpuInstr3_pshufw_MM1_MM2_01Bh_icebp_c32, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2779 { bs3CpuInstr3_pshufw_MM1_FSxBX_01Bh_icebp_c32, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2780 }; 2781 # endif 2782 # if ARCH_BITS >= 64 2783 static BS3CPUINSTR3_TEST3_T const s_aTests64[] = 2784 { 2785 { bs3CpuInstr3_pshufw_MM1_MM2_0FFh_icebp_c64, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2786 { bs3CpuInstr3_pshufw_MM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2787 { bs3CpuInstr3_pshufw_MM1_MM2_01Bh_icebp_c64, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2788 { bs3CpuInstr3_pshufw_MM1_FSxBX_01Bh_icebp_c64, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2789 }; 2790 # endif 2791 2792 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 2793 unsigned const iTest = BS3CPUINSTR3_TEST3_MODES_INDEX(bMode); 2794 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 2795 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); 2796 } 2797 2798 2799 /* 2800 * PSHUFHW 2801 */ 2802 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr3_v_pshufhw)(uint8_t bMode) 2803 { 2804 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesFF[] = 2805 { 2806 { RTUINT256_INIT_C(0, 0, 0, 0), 2807 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 2808 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 2809 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, 2810 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), 2811 /* => */ RTUINT256_INIT_C(0x5555555555555555, 0x1111222233334444, 0x1111111111111111, 0x5555666677778888) }, 2812 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 2813 /* => */ RTUINT256_INIT_C(0x4d094d094d094d09, 0x3ef417c8666b3fe6, 0xb421b421b421b421, 0x9c5ce073930996bb) }, 2814 }; 2815 2816 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues1B[] = 2817 { 2818 { RTUINT256_INIT_C(0, 0, 0, 0), 2819 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 2820 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 2821 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, 2822 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), 2823 /* => */ RTUINT256_INIT_C(0x8888777766665555, 0x1111222233334444, 0x4444333322221111, 0x5555666677778888) }, 2824 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 2825 /* => */ RTUINT256_INIT_C(0x73d56cdcf02a4d09, 0x3ef417c8666b3fe6, 0x9ba2564c2fa8b421, 0x9c5ce073930996bb) }, 2826 }; 2827 2828 static BS3CPUINSTR3_TEST3_T const s_aTests16[] = 2829 { 2830 { bs3CpuInstr3_pshufhw_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2831 { bs3CpuInstr3_pshufhw_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2832 { bs3CpuInstr3_pshufhw_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2833 { bs3CpuInstr3_pshufhw_XMM1_FSxBX_01Bh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2834 2835 { bs3CpuInstr3_vpshufhw_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2836 { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2837 { bs3CpuInstr3_vpshufhw_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2838 { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2839 2840 { bs3CpuInstr3_vpshufhw_YMM1_YMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2841 { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2842 { bs3CpuInstr3_vpshufhw_YMM1_YMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2843 { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2844 }; 2845 # if ARCH_BITS >= 32 2846 static BS3CPUINSTR3_TEST3_T const s_aTests32[] = 2847 { 2848 { bs3CpuInstr3_pshufhw_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2849 { bs3CpuInstr3_pshufhw_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2850 { bs3CpuInstr3_pshufhw_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2851 { bs3CpuInstr3_pshufhw_XMM1_FSxBX_01Bh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2852 2853 { bs3CpuInstr3_vpshufhw_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2854 { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2855 { bs3CpuInstr3_vpshufhw_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2856 { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2857 2858 { bs3CpuInstr3_vpshufhw_YMM1_YMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2859 { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2860 { bs3CpuInstr3_vpshufhw_YMM1_YMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2861 { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2862 }; 2863 # endif 2864 # if ARCH_BITS >= 64 2865 static BS3CPUINSTR3_TEST3_T const s_aTests64[] = 2866 { 2867 { bs3CpuInstr3_pshufhw_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2868 { bs3CpuInstr3_pshufhw_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2869 { bs3CpuInstr3_pshufhw_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2870 { bs3CpuInstr3_pshufhw_XMM1_FSxBX_01Bh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2871 2872 { bs3CpuInstr3_vpshufhw_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2873 { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2874 { bs3CpuInstr3_vpshufhw_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2875 { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2876 2877 { bs3CpuInstr3_vpshufhw_YMM1_YMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2878 { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2879 { bs3CpuInstr3_vpshufhw_YMM1_YMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2880 { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2881 { bs3CpuInstr3_vpshufhw_YMM12_YMM7_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 12, 7, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2882 { bs3CpuInstr3_vpshufhw_YMM9_YMM12_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 9, 12, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2883 }; 2884 # endif 2885 2886 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 2887 unsigned const iTest = BS3CPUINSTR3_TEST3_MODES_INDEX(bMode); 2888 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 2889 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); 2890 } 2891 2892 2893 /* 2894 * PSHUFLW 2895 */ 2896 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr3_v_pshuflw)(uint8_t bMode) 2897 { 2898 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesFF[] = 2899 { 2900 { RTUINT256_INIT_C(0, 0, 0, 0), 2901 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 2902 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 2903 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, 2904 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), 2905 /* => */ RTUINT256_INIT_C(0x5555666677778888, 0x1111111111111111, 0x1111222233334444, 0x5555555555555555) }, 2906 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 2907 /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef43ef43ef43ef4, 0xb4212fa8564c9ba2, 0x9c5c9c5c9c5c9c5c) }, 2908 }; 2909 2910 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues1B[] = 2911 { 2912 { RTUINT256_INIT_C(0, 0, 0, 0), 2913 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 2914 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 2915 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, 2916 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), 2917 /* => */ RTUINT256_INIT_C(0x5555666677778888, 0x4444333322221111, 0x1111222233334444, 0x8888777766665555) }, 2918 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 2919 /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3fe6666b17c83ef4, 0xb4212fa8564c9ba2, 0x96bb9309e0739c5c) }, 2920 }; 2921 2922 static BS3CPUINSTR3_TEST3_T const s_aTests16[] = 2923 { 2924 { bs3CpuInstr3_pshuflw_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2925 { bs3CpuInstr3_pshuflw_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2926 { bs3CpuInstr3_pshuflw_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2927 { bs3CpuInstr3_pshuflw_XMM1_FSxBX_01Bh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2928 2929 { bs3CpuInstr3_vpshuflw_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2930 { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2931 { bs3CpuInstr3_vpshuflw_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2932 { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2933 2934 { bs3CpuInstr3_vpshuflw_YMM1_YMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2935 { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2936 { bs3CpuInstr3_vpshuflw_YMM1_YMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2937 { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2938 }; 2939 # if ARCH_BITS >= 32 2940 static BS3CPUINSTR3_TEST3_T const s_aTests32[] = 2941 { 2942 { bs3CpuInstr3_pshuflw_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2943 { bs3CpuInstr3_pshuflw_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2944 { bs3CpuInstr3_pshuflw_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2945 { bs3CpuInstr3_pshuflw_XMM1_FSxBX_01Bh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2946 2947 { bs3CpuInstr3_vpshuflw_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2948 { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2949 { bs3CpuInstr3_vpshuflw_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2950 { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2951 2952 { bs3CpuInstr3_vpshuflw_YMM1_YMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2953 { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2954 { bs3CpuInstr3_vpshuflw_YMM1_YMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2955 { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2956 }; 2957 # endif 2958 # if ARCH_BITS >= 64 2959 static BS3CPUINSTR3_TEST3_T const s_aTests64[] = 2960 { 2961 { bs3CpuInstr3_pshuflw_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2962 { bs3CpuInstr3_pshuflw_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2963 { bs3CpuInstr3_pshuflw_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2964 { bs3CpuInstr3_pshuflw_XMM1_FSxBX_01Bh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2965 2966 { bs3CpuInstr3_vpshuflw_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2967 { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2968 { bs3CpuInstr3_vpshuflw_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2969 { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2970 2971 { bs3CpuInstr3_vpshuflw_YMM1_YMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2972 { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2973 { bs3CpuInstr3_vpshuflw_YMM1_YMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2974 { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2975 { bs3CpuInstr3_vpshuflw_YMM12_YMM7_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 12, 7, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 2976 { bs3CpuInstr3_vpshuflw_YMM9_YMM12_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 9, 12, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 2977 }; 2978 # endif 2979 2980 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 2981 unsigned const iTest = BS3CPUINSTR3_TEST3_MODES_INDEX(bMode); 2982 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 2983 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); 2984 } 2985 2986 2987 /* 2988 * PSHUFHD 2989 */ 2990 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr3_v_pshufd)(uint8_t bMode) 2991 { 2992 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesFF[] = 2993 { 2994 { RTUINT256_INIT_C(0, 0, 0, 0), 2995 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 2996 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 2997 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, 2998 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), 2999 /* => */ RTUINT256_INIT_C(0x5555666655556666, 0x5555666655556666, 0x1111222211112222, 0x1111222211112222) }, 3000 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 3001 /* => */ RTUINT256_INIT_C(0x4d09f02a4d09f02a, 0x4d09f02a4d09f02a, 0xb4212fa8b4212fa8, 0xb4212fa8b4212fa8) }, 3002 }; 3003 3004 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues1B[] = 3005 { 3006 { RTUINT256_INIT_C(0, 0, 0, 0), 3007 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 3008 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 3009 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, 3010 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), 3011 /* => */ RTUINT256_INIT_C(0x3333444411112222, 0x7777888855556666, 0x7777888855556666, 0x3333444411112222) }, 3012 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 3013 /* => */ RTUINT256_INIT_C(0x666b3fe63ef417c8, 0x6cdc73d54d09f02a, 0x930996bb9c5ce073, 0x564c9ba2b4212fa8) }, 3014 }; 3015 3016 static BS3CPUINSTR3_TEST3_T const s_aTests16[] = 3017 { 3018 { bs3CpuInstr3_pshufd_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 3019 { bs3CpuInstr3_pshufd_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 3020 { bs3CpuInstr3_pshufd_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 3021 { bs3CpuInstr3_pshufd_XMM1_FSxBX_01Bh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 3022 3023 { bs3CpuInstr3_vpshufd_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 3024 { bs3CpuInstr3_vpshufd_XMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 3025 { bs3CpuInstr3_vpshufd_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 3026 { bs3CpuInstr3_vpshufd_XMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 3027 3028 { bs3CpuInstr3_vpshufd_YMM1_YMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 3029 { bs3CpuInstr3_vpshufd_YMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 3030 { bs3CpuInstr3_vpshufd_YMM1_YMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 3031 { bs3CpuInstr3_vpshufd_YMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 3032 }; 3033 # if ARCH_BITS >= 32 3034 static BS3CPUINSTR3_TEST3_T const s_aTests32[] = 3035 { 3036 { bs3CpuInstr3_pshufd_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 3037 { bs3CpuInstr3_pshufd_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 3038 { bs3CpuInstr3_pshufd_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 3039 { bs3CpuInstr3_pshufd_XMM1_FSxBX_01Bh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 3040 3041 { bs3CpuInstr3_vpshufd_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 3042 { bs3CpuInstr3_vpshufd_XMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 3043 { bs3CpuInstr3_vpshufd_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 3044 { bs3CpuInstr3_vpshufd_XMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 3045 3046 { bs3CpuInstr3_vpshufd_YMM1_YMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 3047 { bs3CpuInstr3_vpshufd_YMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 3048 { bs3CpuInstr3_vpshufd_YMM1_YMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 3049 { bs3CpuInstr3_vpshufd_YMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 3050 }; 3051 # endif 3052 # if ARCH_BITS >= 64 3053 static BS3CPUINSTR3_TEST3_T const s_aTests64[] = 3054 { 3055 { bs3CpuInstr3_pshufd_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 3056 { bs3CpuInstr3_pshufd_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 3057 { bs3CpuInstr3_pshufd_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 3058 { bs3CpuInstr3_pshufd_XMM1_FSxBX_01Bh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 3059 3060 { bs3CpuInstr3_vpshufd_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 3061 { bs3CpuInstr3_vpshufd_XMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 3062 { bs3CpuInstr3_vpshufd_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 3063 { bs3CpuInstr3_vpshufd_XMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 3064 3065 { bs3CpuInstr3_vpshufd_YMM1_YMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 3066 { bs3CpuInstr3_vpshufd_YMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 3067 { bs3CpuInstr3_vpshufd_YMM1_YMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 3068 { bs3CpuInstr3_vpshufd_YMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 3069 { bs3CpuInstr3_vpshufd_YMM12_YMM7_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 12, 7, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 3070 { bs3CpuInstr3_vpshufd_YMM9_YMM12_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 9, 12, RT_ELEMENTS(s_aValues1B), s_aValues1B }, 3071 }; 3072 # endif 3073 3074 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 3075 unsigned const iTest = BS3CPUINSTR3_TEST3_MODES_INDEX(bMode); 3076 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 3077 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); 3078 } 3079 3080 3081 2414 3082 #endif /* BS3_INSTANTIATING_CMN */ 2415 3083 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac
r95481 r95485 51 51 ; ASSUMES the length is between the start of the function and the .again label. 52 52 ; 53 %ifndef BS3CPUINSTR3_PROC_BEGIN_CMN_DEFINED54 %define BS3CPUINSTR3_PROC_BEGIN_CMN_DEFINED55 %macro BS3CPUINSTR3_PROC_BEGIN_CMN 153 %ifndef BS3CPUINSTR3_PROC_BEGIN_CMN_DEFINED 54 %define BS3CPUINSTR3_PROC_BEGIN_CMN_DEFINED 55 %macro BS3CPUINSTR3_PROC_BEGIN_CMN 1 56 56 align 8, db 0cch 57 57 db BS3_CMN_NM(%1).again - BS3_CMN_NM(%1) 58 58 BS3_PROC_BEGIN_CMN %1, BS3_PBC_NEAR 59 %endmacro 60 %endif 59 %endmacro 60 %endif 61 62 ;; 63 ; The EMIT_INSTR_PLUS_ICEBP macros is for creating a common function for and 64 ; named after a single instruction, followed by a looping ICEBP. 65 ; 66 ; This works like a prefix to the instruction invocation, only exception is that 67 ; instead of [fs:xBX] you write FSxBS as that's what is wanted in the name. 68 ; 69 %ifndef EMIT_INSTR_PLUS_ICEBP_DEFINED 70 %define EMIT_INSTR_PLUS_ICEBP_DEFINED 71 72 %macro EMIT_INSTR_PLUS_ICEBP 2 73 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _ %+ %2 %+ _icebp 74 %define FSxBX [fs:xBX] 75 %1 %2 76 %undef FSxBX 77 .again: 78 icebp 79 jmp .again 80 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _ %+ %2 %+ _icebp 81 %endmacro 82 83 %macro EMIT_INSTR_PLUS_ICEBP 3 84 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _ %+ %2 %+ _ %+ %3 %+ _icebp 85 %define FSxBX [fs:xBX] 86 %1 %2, %3 87 %undef FSxBX 88 .again: 89 icebp 90 jmp .again 91 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _ %+ %2 %+ _ %+ %3 %+ _icebp 92 %endmacro 93 94 %macro EMIT_INSTR_PLUS_ICEBP 4 95 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _ %+ %2 %+ _ %+ %3 %+ _ %+ %4 %+ _icebp 96 %define FSxBX [fs:xBX] 97 %1 %2, %3, %4 98 %undef FSxBX 99 .again: 100 icebp 101 jmp .again 102 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _ %+ %2 %+ _ %+ %3 %+ _ %+ %4 %+ _icebp 103 %endmacro 104 105 %macro EMIT_INSTR_PLUS_ICEBP 5 106 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _ %+ %2 %+ _ %+ %3 %+ _ %+ %4 %+ _ %+ %5 %+ _icebp 107 %define FSxBX [fs:xBX] 108 %1 %2, %3, %4, %5 109 %undef FSxBX 110 .again: 111 icebp 112 jmp .again 113 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _ %+ %2 %+ _ %+ %3 %+ _ %+ %4 %+ _ %+ %5 %+ _icebp 114 %endmacro 115 116 %endif 117 61 118 62 119 … … 445 502 EMIT_TYPE2_ONE_INSTR pmovmskb, vpmovmskb, 1, 0d7h 446 503 504 ; 505 ; PSHUFW 506 ; 507 EMIT_INSTR_PLUS_ICEBP pshufw, MM1, MM2, 0FFh ; FF = top src word in all destination words 508 EMIT_INSTR_PLUS_ICEBP pshufw, MM1, FSxBX, 0FFh 509 EMIT_INSTR_PLUS_ICEBP pshufw, MM1, MM2, 01Bh ; 1B = word swap (like bswap but for words) 510 EMIT_INSTR_PLUS_ICEBP pshufw, MM1, FSxBX, 01Bh 511 512 ; 513 ; [V]PSHUFHW 514 ; 515 EMIT_INSTR_PLUS_ICEBP pshufhw, XMM1, XMM2, 0FFh 516 EMIT_INSTR_PLUS_ICEBP pshufhw, XMM1, FSxBX, 0FFh 517 EMIT_INSTR_PLUS_ICEBP pshufhw, XMM1, XMM2, 01Bh 518 EMIT_INSTR_PLUS_ICEBP pshufhw, XMM1, FSxBX, 01Bh 519 520 EMIT_INSTR_PLUS_ICEBP vpshufhw, XMM1, XMM2, 0FFh 521 EMIT_INSTR_PLUS_ICEBP vpshufhw, XMM1, FSxBX, 0FFh 522 EMIT_INSTR_PLUS_ICEBP vpshufhw, XMM1, XMM2, 01Bh 523 EMIT_INSTR_PLUS_ICEBP vpshufhw, XMM1, FSxBX, 01Bh 524 525 EMIT_INSTR_PLUS_ICEBP vpshufhw, YMM1, YMM2, 0FFh 526 EMIT_INSTR_PLUS_ICEBP vpshufhw, YMM1, FSxBX, 0FFh 527 EMIT_INSTR_PLUS_ICEBP vpshufhw, YMM1, YMM2, 01Bh 528 EMIT_INSTR_PLUS_ICEBP vpshufhw, YMM1, FSxBX, 01Bh 529 530 %if TMPL_BITS == 64 531 EMIT_INSTR_PLUS_ICEBP vpshufhw, YMM12, YMM7, 0FFh 532 EMIT_INSTR_PLUS_ICEBP vpshufhw, YMM9, YMM12, 01Bh 533 %endif 534 535 ; 536 ; [V]PSHUFLW 537 ; 538 EMIT_INSTR_PLUS_ICEBP pshuflw, XMM1, XMM2, 0FFh 539 EMIT_INSTR_PLUS_ICEBP pshuflw, XMM1, FSxBX, 0FFh 540 EMIT_INSTR_PLUS_ICEBP pshuflw, XMM1, XMM2, 01Bh 541 EMIT_INSTR_PLUS_ICEBP pshuflw, XMM1, FSxBX, 01Bh 542 543 EMIT_INSTR_PLUS_ICEBP vpshuflw, XMM1, XMM2, 0FFh 544 EMIT_INSTR_PLUS_ICEBP vpshuflw, XMM1, FSxBX, 0FFh 545 EMIT_INSTR_PLUS_ICEBP vpshuflw, XMM1, XMM2, 01Bh 546 EMIT_INSTR_PLUS_ICEBP vpshuflw, XMM1, FSxBX, 01Bh 547 548 EMIT_INSTR_PLUS_ICEBP vpshuflw, YMM1, YMM2, 0FFh 549 EMIT_INSTR_PLUS_ICEBP vpshuflw, YMM1, FSxBX, 0FFh 550 EMIT_INSTR_PLUS_ICEBP vpshuflw, YMM1, YMM2, 01Bh 551 EMIT_INSTR_PLUS_ICEBP vpshuflw, YMM1, FSxBX, 01Bh 552 553 %if TMPL_BITS == 64 554 EMIT_INSTR_PLUS_ICEBP vpshuflw, YMM12, YMM7, 0FFh 555 EMIT_INSTR_PLUS_ICEBP vpshuflw, YMM9, YMM12, 01Bh 556 %endif 557 558 ; 559 ; [V]PSHUFD 560 ; 561 EMIT_INSTR_PLUS_ICEBP pshufd, XMM1, XMM2, 0FFh 562 EMIT_INSTR_PLUS_ICEBP pshufd, XMM1, FSxBX, 0FFh 563 EMIT_INSTR_PLUS_ICEBP pshufd, XMM1, XMM2, 01Bh 564 EMIT_INSTR_PLUS_ICEBP pshufd, XMM1, FSxBX, 01Bh 565 566 EMIT_INSTR_PLUS_ICEBP vpshufd, XMM1, XMM2, 0FFh 567 EMIT_INSTR_PLUS_ICEBP vpshufd, XMM1, FSxBX, 0FFh 568 EMIT_INSTR_PLUS_ICEBP vpshufd, XMM1, XMM2, 01Bh 569 EMIT_INSTR_PLUS_ICEBP vpshufd, XMM1, FSxBX, 01Bh 570 571 EMIT_INSTR_PLUS_ICEBP vpshufd, YMM1, YMM2, 0FFh 572 EMIT_INSTR_PLUS_ICEBP vpshufd, YMM1, FSxBX, 0FFh 573 EMIT_INSTR_PLUS_ICEBP vpshufd, YMM1, YMM2, 01Bh 574 EMIT_INSTR_PLUS_ICEBP vpshufd, YMM1, FSxBX, 01Bh 575 576 %if TMPL_BITS == 64 577 EMIT_INSTR_PLUS_ICEBP vpshufd, YMM12, YMM7, 0FFh 578 EMIT_INSTR_PLUS_ICEBP vpshufd, YMM9, YMM12, 01Bh 579 %endif 447 580 448 581 %endif ; BS3_INSTANTIATING_CMN -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c
r95481 r95485 44 44 BS3TESTMODEBYMAX_PROTOTYPES_CMN(bs3CpuInstr3_v_psubb_psubw_psubd_psubq); 45 45 BS3TESTMODEBYMAX_PROTOTYPES_CMN(bs3CpuInstr3_v_pmovmskb); 46 BS3TESTMODEBYMAX_PROTOTYPES_CMN(bs3CpuInstr3_pshufw); 47 BS3TESTMODEBYMAX_PROTOTYPES_CMN(bs3CpuInstr3_v_pshufhw); 48 BS3TESTMODEBYMAX_PROTOTYPES_CMN(bs3CpuInstr3_v_pshuflw); 49 BS3TESTMODEBYMAX_PROTOTYPES_CMN(bs3CpuInstr3_v_pshufd); 46 50 47 51 … … 51 55 static const BS3TESTMODEBYMAXENTRY g_aTests[] = 52 56 { 53 #if 157 #if 0 54 58 BS3TESTMODEBYMAXENTRY_CMN("[v]andps/[v]andpd/[v]pand", bs3CpuInstr3_v_andps_andpd_pand), 55 59 BS3TESTMODEBYMAXENTRY_CMN("[v]andnps/[v]andnpd/[v]pandn", bs3CpuInstr3_v_andnps_andnpd_pandn), … … 57 61 BS3TESTMODEBYMAXENTRY_CMN("[v]xorps/[v]xorpd/[v]pxor", bs3CpuInstr3_v_xorps_xorpd_pxor), 58 62 #endif 59 #if 163 #if 0 60 64 BS3TESTMODEBYMAXENTRY_CMN("[v]pcmpgtb/[v]pcmpgtw/[v]pcmpgtd/[v]pcmpgtq", bs3CpuInstr3_v_pcmpgtb_pcmpgtw_pcmpgtd_pcmpgtq), 61 65 BS3TESTMODEBYMAXENTRY_CMN("[v]pcmpeqb/[v]pcmpeqw/[v]pcmpeqd/[v]pcmpeqq", bs3CpuInstr3_v_pcmpeqb_pcmpeqw_pcmpeqd_pcmpeqq), 62 66 #endif 63 #if 167 #if 0 64 68 BS3TESTMODEBYMAXENTRY_CMN("[v]paddb/[v]paddw/[v]paddd/[v]paddq", bs3CpuInstr3_v_paddb_paddw_paddd_paddq), 65 69 BS3TESTMODEBYMAXENTRY_CMN("[v]psubb/[v]psubw/[v]psubd/[v]psubq", bs3CpuInstr3_v_psubb_psubw_psubd_psubq), 66 70 #endif 67 71 #if 1 68 BS3TESTMODEBYMAXENTRY_CMN("[v]pmovmskb", bs3CpuInstr3_v_pmovmskb),72 // BS3TESTMODEBYMAXENTRY_CMN("[v]pmovmskb", bs3CpuInstr3_v_pmovmskb), 69 73 #endif 74 BS3TESTMODEBYMAXENTRY_CMN("pshufw", bs3CpuInstr3_pshufw), 75 BS3TESTMODEBYMAXENTRY_CMN("[v]pshufhw", bs3CpuInstr3_v_pshufhw), 76 BS3TESTMODEBYMAXENTRY_CMN("[v]pshuflw", bs3CpuInstr3_v_pshuflw), 77 BS3TESTMODEBYMAXENTRY_CMN("[v]pshufd", bs3CpuInstr3_v_pshufd), 70 78 }; 71 79 -
trunk/src/VBox/ValidationKit/bootsectors/bs3kit/bs3-cmn-ExtCtxSetMm.c
r95399 r95485 33 33 34 34 #undef Bs3ExtCtxSetMm 35 BS3_CMN_DEF(bool, Bs3ExtCtxSetMm,(PBS3EXTCTX pExtCtx, uint8_t iReg, uint64_t uValue ))35 BS3_CMN_DEF(bool, Bs3ExtCtxSetMm,(PBS3EXTCTX pExtCtx, uint8_t iReg, uint64_t uValue, BS3EXTCTXTOPMM enmTop)) 36 36 { 37 37 AssertCompileMembersAtSameOffset(BS3EXTCTX, Ctx.x87.aRegs, BS3EXTCTX, Ctx.x.x87.aRegs); … … 41 41 case BS3EXTCTXMETHOD_FXSAVE: 42 42 case BS3EXTCTXMETHOD_XSAVE: 43 /* pxor mm1, mm2 on 10980XE sets mm1's sign and exponent to all 1's. */44 pExtCtx->Ctx.x87.aRegs[iReg].au16[4] = UINT16_MAX;45 pExtCtx->Ctx.x87.aRegs[iReg].mmx = uValue;43 pExtCtx->Ctx.x87.aRegs[iReg].mmx = uValue; 44 if (enmTop == BS3EXTCTXTOPMM_SET || enmTop == BS3EXTCTXTOPMM_ZERO) 45 pExtCtx->Ctx.x87.aRegs[iReg].au16[4] = enmTop == BS3EXTCTXTOPMM_SET ? UINT16_MAX : 0; 46 46 return true; 47 47 48 48 case BS3EXTCTXMETHOD_ANCIENT: 49 pExtCtx->Ctx.Ancient.regs[iReg].au16[4] = UINT16_MAX; /* see above */ 50 pExtCtx->Ctx.Ancient.regs[iReg].mmx = uValue; 49 pExtCtx->Ctx.Ancient.regs[iReg].mmx = uValue; 50 if (enmTop == BS3EXTCTXTOPMM_SET || enmTop == BS3EXTCTXTOPMM_ZERO) 51 pExtCtx->Ctx.Ancient.regs[iReg].au16[4] = enmTop == BS3EXTCTXTOPMM_SET ? UINT16_MAX : 0; 51 52 return true; 52 53 } -
trunk/src/VBox/ValidationKit/bootsectors/bs3kit/bs3kit.h
r95481 r95485 2989 2989 BS3_CMN_PROTO_STUB(uint64_t, Bs3ExtCtxGetMm,(PCBS3EXTCTX pExtCtx, uint8_t iReg)); 2990 2990 2991 /** What to do about the 16-bit above the MM QWORD. */ 2992 typedef enum BS3EXTCTXTOPMM 2993 { 2994 /** Invalid zero value. */ 2995 BS3EXTCTXTOPMM_INVALID = 0, 2996 /** Set to 0FFFFh like real CPUs typically does when updating an MM register. */ 2997 BS3EXTCTXTOPMM_SET, 2998 /** Set to zero. */ 2999 BS3EXTCTXTOPMM_ZERO, 3000 /** Don't change the value, leaving it as-is. */ 3001 BS3EXTCTXTOPMM_AS_IS, 3002 /** End of valid values. */ 3003 BS3EXTCTXTOPMM_END 3004 } BS3EXTCTXTOPMM; 3005 2991 3006 /** 2992 3007 * Sets the value of YMM register number @a iReg in @a pExtCtx to @a pValue. … … 2996 3011 * @param iReg The register to set. 2997 3012 * @param uValue The new register value. 2998 */ 2999 BS3_CMN_PROTO_STUB(bool, Bs3ExtCtxSetMm,(PBS3EXTCTX pExtCtx, uint8_t iReg, uint64_t uValue)); 3013 * @param enmTop What to do about the 16-bit value above the MM 3014 * QWord. 3015 */ 3016 BS3_CMN_PROTO_STUB(bool, Bs3ExtCtxSetMm,(PBS3EXTCTX pExtCtx, uint8_t iReg, uint64_t uValue, BS3EXTCTXTOPMM enmTop)); 3000 3017 3001 3018 /**
Note:
See TracChangeset
for help on using the changeset viewer.
