Changeset 95532 in vbox for trunk/src/VBox/ValidationKit/bootsectors

Timestamp:

Jul 6, 2022 6:10:43 PM (3 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

152156

Message:

ValKit/bs3-cpu-instr-3: Simple [v]movlps tests. bugref:9898

Location:

trunk/src/VBox/ValidationKit/bootsectors

Files:

• bs3-cpu-instr-3-template.mac (modified) (1 diff)
• bs3-cpu-instr-3.c32 (modified) (3 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac

@@ -1017 +1017 @@
  %endif
 
+;
+; [V]MOVLPS - not testing the 2nd register variant.
+;
+EMIT_INSTR_PLUS_ICEBP movlps,  XMM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP movlps,  FSxBX, XMM1
+EMIT_INSTR_PLUS_ICEBP vmovlps, XMM1, XMM2, FSxBX
+EMIT_INSTR_PLUS_ICEBP vmovlps, FSxBX, XMM1
+ %if TMPL_BITS == 64
+EMIT_INSTR_PLUS_ICEBP movlps,  XMM8, FSxBX
+EMIT_INSTR_PLUS_ICEBP movlps,  FSxBX, XMM11
+EMIT_INSTR_PLUS_ICEBP vmovlps, XMM10, XMM14, FSxBX
+EMIT_INSTR_PLUS_ICEBP vmovlps, FSxBX, XMM9
+ %endif
+
+
 %endif ; BS3_INSTANTIATING_CMN
 

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32

@@ -3536 +3536 @@
                                         g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5));
 }
+
+
+/*
+ * [V]MOVLPS - Merge a low qword (two single precision floating-point values)
+ *             from memory with the high qword from a register (SSE destination
+ *             or VEX 2nd source).
+ *             The store variant just stores the lower qword.
+ */
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movlps_XMM1_FSxBX_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movlps_FSxBX_XMM1_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovlps_XMM1_XMM2_FSxBX_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovlps_FSxBX_XMM1_icebp);
+extern FNBS3FAR             bs3CpuInstr3_movlps_XMM8_FSxBX_icebp_c64;
+extern FNBS3FAR             bs3CpuInstr3_movlps_FSxBX_XMM11_icebp_c64;
+extern FNBS3FAR             bs3CpuInstr3_vmovlps_XMM10_XMM14_FSxBX_icebp_c64;
+extern FNBS3FAR             bs3CpuInstr3_vmovlps_FSxBX_XMM9_icebp_c64;
+
+BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movlps(uint8_t bMode)
+{
+    static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesLd[] =
+    {
+        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
+            /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
+            /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
+        {   /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
+            /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
+            /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9192939495969798, 0xc1c2c3c4c5c6c7c8) },
+        {   /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x81828384c5c6c7c8),
+            /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
+            /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9999aaaabbbbcccc, 0x81828384c5c6c7c8) },
+        {   /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
+            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
+            /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x8800e95bbf9962c3, 0x9c5ce073930996bb) },
+    };
+    static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSt[] =
+    {
+        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
+            /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
+            /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
+        {   /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
+            /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
+            /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9192939495969798, 0xc1c2c3c4c5c6c7c8) },
+        {   /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x81828384c5c6c7c8),
+            /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
+            /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9999aaaabbbbcccc, 0x81828384c5c6c7c8) },
+        {   /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
+            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
+            /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x8800e95bbf9962c3, 0x9c5ce073930996bb) },
+    };
+
+    static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
+    {
+        {  bs3CpuInstr3_movlps_XMM1_FSxBX_icebp_c16,        X86_XCPT_AC, RM_MEM64, T_SSE,         1,   1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
+        {  bs3CpuInstr3_movlps_FSxBX_XMM1_icebp_c16,        X86_XCPT_AC, RM_MEM64, T_SSE,       255, 128,   1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt },
+
+        {  bs3CpuInstr3_vmovlps_XMM1_XMM2_FSxBX_icebp_c16,  X86_XCPT_AC, RM_MEM64, T_AVX_128,     1,   2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
+        {  bs3CpuInstr3_vmovlps_FSxBX_XMM1_icebp_c16,       X86_XCPT_AC, RM_MEM64, T_AVX_128,   255, 128,   1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt},
+    };
+    static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
+    {
+        {  bs3CpuInstr3_movlps_XMM1_FSxBX_icebp_c32,        X86_XCPT_AC, RM_MEM64, T_SSE,         1,   1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
+        {  bs3CpuInstr3_movlps_FSxBX_XMM1_icebp_c32,        X86_XCPT_AC, RM_MEM64, T_SSE,       255, 128,   1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt },
+
+        {  bs3CpuInstr3_vmovlps_XMM1_XMM2_FSxBX_icebp_c32,  X86_XCPT_AC, RM_MEM64, T_AVX_128,     1,   2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
+        {  bs3CpuInstr3_vmovlps_FSxBX_XMM1_icebp_c32,       X86_XCPT_AC, RM_MEM64, T_AVX_128,   255, 128,   1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt},
+    };
+    static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
+    {
+        {  bs3CpuInstr3_movlps_XMM1_FSxBX_icebp_c64,        X86_XCPT_AC, RM_MEM64, T_SSE,         1,   1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
+        {  bs3CpuInstr3_movlps_XMM8_FSxBX_icebp_c64,        X86_XCPT_AC, RM_MEM64, T_SSE,         8,   8, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
+        {  bs3CpuInstr3_movlps_FSxBX_XMM1_icebp_c64,        X86_XCPT_AC, RM_MEM64, T_SSE,       255, 128,   1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt },
+        {  bs3CpuInstr3_movlps_FSxBX_XMM11_icebp_c64,       X86_XCPT_AC, RM_MEM64, T_SSE,       255, 128,  11, RT_ELEMENTS(s_aValuesSt), s_aValuesSt },
+
+        {  bs3CpuInstr3_vmovlps_XMM1_XMM2_FSxBX_icebp_c64,  X86_XCPT_AC, RM_MEM64, T_AVX_128,     1,   2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
+        {  bs3CpuInstr3_vmovlps_XMM10_XMM14_FSxBX_icebp_c64,X86_XCPT_AC, RM_MEM64, T_AVX_128,    10,  14, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd },
+        {  bs3CpuInstr3_vmovlps_FSxBX_XMM1_icebp_c64,       X86_XCPT_AC, RM_MEM64, T_AVX_128,   255, 128,   1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt},
+        {  bs3CpuInstr3_vmovlps_FSxBX_XMM9_icebp_c64,       X86_XCPT_AC, RM_MEM64, T_AVX_128,   255, 128,   9, RT_ELEMENTS(s_aValuesSt), s_aValuesSt},
+    };
+    static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
+    unsigned const                         iTest       = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
+    return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+                                        g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5));
+}
+
 
 
@@ -4718 +4802 @@
     static const BS3TESTMODEBYONEENTRY g_aTests[] =
     {
-#define ALL_TESTS
+//#define ALL_TESTS
 #if defined(ALL_TESTS)
         { "[v]andps/[v]andpd/[v]pand",                      bs3CpuInstr3_v_andps_andpd_pand, 0 },
@@ -4765 +4849 @@
         { "[v]movss",                                       bs3CpuInstr3_v_movss, 0 },
         { "[v]movsd",                                       bs3CpuInstr3_v_movsd, 0 },
+        { "[v]movlps",                                      bs3CpuInstr3_v_movlps, 0 },
 #endif
     };