Changeset 95536 in vbox for trunk/src/VBox/ValidationKit/bootsectors
- Timestamp:
- Jul 6, 2022 7:42:19 PM (3 years ago)
- svn:sync-xref-src-repo-rev:
- 152160
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 2 edited
-
bs3-cpu-instr-3-template.mac (modified) (1 diff)
-
bs3-cpu-instr-3.c32 (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac
r95535 r95536 1055 1055 %endif 1056 1056 1057 ; 1058 ; [V]MOVSLDUP 1059 ; 1060 EMIT_INSTR_PLUS_ICEBP movsldup, XMM1, XMM2 1061 EMIT_INSTR_PLUS_ICEBP movsldup, XMM1, FSxBX 1062 EMIT_INSTR_PLUS_ICEBP vmovsldup, XMM1, XMM2 1063 EMIT_INSTR_PLUS_ICEBP vmovsldup, XMM1, FSxBX 1064 EMIT_INSTR_PLUS_ICEBP vmovsldup, YMM1, YMM2 1065 EMIT_INSTR_PLUS_ICEBP vmovsldup, YMM1, FSxBX 1066 %if TMPL_BITS == 64 1067 EMIT_INSTR_PLUS_ICEBP movsldup, XMM8, XMM12 1068 EMIT_INSTR_PLUS_ICEBP movsldup, XMM10, FSxBX 1069 EMIT_INSTR_PLUS_ICEBP vmovsldup, XMM7, XMM14 1070 EMIT_INSTR_PLUS_ICEBP vmovsldup, XMM11, FSxBX 1071 EMIT_INSTR_PLUS_ICEBP vmovsldup, YMM12, YMM8 1072 EMIT_INSTR_PLUS_ICEBP vmovsldup, YMM12, FSxBX 1073 %endif 1074 1075 ; 1076 ; [V]MOVDDUP 1077 ; 1078 EMIT_INSTR_PLUS_ICEBP movddup, XMM1, XMM2 1079 EMIT_INSTR_PLUS_ICEBP movddup, XMM1, FSxBX 1080 EMIT_INSTR_PLUS_ICEBP vmovddup, XMM1, XMM2 1081 EMIT_INSTR_PLUS_ICEBP vmovddup, XMM1, FSxBX 1082 EMIT_INSTR_PLUS_ICEBP vmovddup, YMM1, YMM2 1083 EMIT_INSTR_PLUS_ICEBP vmovddup, YMM1, FSxBX 1084 %if TMPL_BITS == 64 1085 EMIT_INSTR_PLUS_ICEBP movddup, XMM8, XMM12 1086 EMIT_INSTR_PLUS_ICEBP movddup, XMM10, FSxBX 1087 EMIT_INSTR_PLUS_ICEBP vmovddup, XMM7, XMM14 1088 EMIT_INSTR_PLUS_ICEBP vmovddup, XMM11, FSxBX 1089 EMIT_INSTR_PLUS_ICEBP vmovddup, YMM12, YMM8 1090 EMIT_INSTR_PLUS_ICEBP vmovddup, YMM12, FSxBX 1091 %endif 1092 1093 1057 1094 1058 1095 %endif ; BS3_INSTANTIATING_CMN -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32
r95535 r95536 4863 4863 4864 4864 4865 /* 4866 * [V]MOVSLDUP - Duplicate even single precision floating-point values. 4867 */ 4868 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movsldup_XMM1_XMM2_icebp); 4869 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movsldup_XMM1_FSxBX_icebp); 4870 extern FNBS3FAR bs3CpuInstr3_movsldup_XMM8_XMM12_icebp_c64; 4871 extern FNBS3FAR bs3CpuInstr3_movsldup_XMM10_FSxBX_icebp_c64; 4872 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovsldup_XMM1_XMM2_icebp); 4873 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovsldup_XMM1_FSxBX_icebp); 4874 extern FNBS3FAR bs3CpuInstr3_vmovsldup_XMM7_XMM14_icebp_c64; 4875 extern FNBS3FAR bs3CpuInstr3_vmovsldup_XMM11_FSxBX_icebp_c64; 4876 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovsldup_YMM1_YMM2_icebp); 4877 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovsldup_YMM1_FSxBX_icebp); 4878 extern FNBS3FAR bs3CpuInstr3_vmovsldup_YMM12_YMM8_icebp_c64; 4879 extern FNBS3FAR bs3CpuInstr3_vmovsldup_YMM12_FSxBX_icebp_c64; 4880 4881 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movsldup(uint8_t bMode) 4882 { 4883 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues[] = 4884 { 4885 { RTUINT256_INIT_C(0, 0, 0, 0), 4886 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 4887 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 4888 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, 4889 { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), 4890 /* => */ RTUINT256_INIT_C(0xbbbbccccbbbbcccc, 0xffff2121ffff2121, 0x3333444433334444, 0x7777888877778888) }, 4891 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 4892 /* => */ RTUINT256_INIT_C(0x6cdc73d56cdc73d5, 0x666b3fe6666b3fe6, 0x564c9ba2564c9ba2, 0x930996bb930996bb) }, 4893 }; 4894 4895 static BS3CPUINSTR3_TEST3_T const s_aTests16[] = 4896 { 4897 { bs3CpuInstr3_movsldup_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4898 { bs3CpuInstr3_movsldup_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4899 4900 { bs3CpuInstr3_vmovsldup_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4901 { bs3CpuInstr3_vmovsldup_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4902 4903 { bs3CpuInstr3_vmovsldup_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4904 { bs3CpuInstr3_vmovsldup_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4905 }; 4906 static BS3CPUINSTR3_TEST3_T const s_aTests32[] = 4907 { 4908 { bs3CpuInstr3_movsldup_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4909 { bs3CpuInstr3_movsldup_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4910 4911 { bs3CpuInstr3_vmovsldup_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4912 { bs3CpuInstr3_vmovsldup_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4913 4914 { bs3CpuInstr3_vmovsldup_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4915 { bs3CpuInstr3_vmovsldup_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4916 }; 4917 static BS3CPUINSTR3_TEST3_T const s_aTests64[] = 4918 { 4919 { bs3CpuInstr3_movsldup_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4920 { bs3CpuInstr3_movsldup_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE3, 8, 12, RT_ELEMENTS(s_aValues), s_aValues }, 4921 { bs3CpuInstr3_movsldup_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4922 { bs3CpuInstr3_movsldup_XMM10_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 10, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4923 4924 { bs3CpuInstr3_vmovsldup_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4925 { bs3CpuInstr3_vmovsldup_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(s_aValues), s_aValues }, 4926 { bs3CpuInstr3_vmovsldup_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4927 { bs3CpuInstr3_vmovsldup_XMM11_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4928 4929 { bs3CpuInstr3_vmovsldup_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4930 { bs3CpuInstr3_vmovsldup_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(s_aValues), s_aValues }, 4931 { bs3CpuInstr3_vmovsldup_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4932 { bs3CpuInstr3_vmovsldup_YMM12_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4933 }; 4934 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 4935 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); 4936 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 4937 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), 0 /*cbMaxAlign*/); 4938 } 4939 4940 4941 /* 4942 * [V]MOVDDUP - Duplicate even single precision floating-point values. 4943 * 4944 * Similar to MOVSLDUP, but different exception class and unit size. 4945 */ 4946 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movddup_XMM1_XMM2_icebp); 4947 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movddup_XMM1_FSxBX_icebp); 4948 extern FNBS3FAR bs3CpuInstr3_movddup_XMM8_XMM12_icebp_c64; 4949 extern FNBS3FAR bs3CpuInstr3_movddup_XMM10_FSxBX_icebp_c64; 4950 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovddup_XMM1_XMM2_icebp); 4951 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovddup_XMM1_FSxBX_icebp); 4952 extern FNBS3FAR bs3CpuInstr3_vmovddup_XMM7_XMM14_icebp_c64; 4953 extern FNBS3FAR bs3CpuInstr3_vmovddup_XMM11_FSxBX_icebp_c64; 4954 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovddup_YMM1_YMM2_icebp); 4955 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovddup_YMM1_FSxBX_icebp); 4956 extern FNBS3FAR bs3CpuInstr3_vmovddup_YMM12_YMM8_icebp_c64; 4957 extern FNBS3FAR bs3CpuInstr3_vmovddup_YMM12_FSxBX_icebp_c64; 4958 4959 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movddup(uint8_t bMode) 4960 { 4961 static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues[] = 4962 { 4963 { RTUINT256_INIT_C(0, 0, 0, 0), 4964 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 4965 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 4966 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, 4967 { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), 4968 /* => */ RTUINT256_INIT_C(0xddddeeeeffff2121, 0xddddeeeeffff2121, 0x5555666677778888, 0x5555666677778888) }, 4969 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 4970 /* => */ RTUINT256_INIT_C(0x3ef417c8666b3fe6, 0x3ef417c8666b3fe6, 0x9c5ce073930996bb, 0x9c5ce073930996bb) }, 4971 }; 4972 4973 /* Note! Seems the 256-bit variants doesn't generate \#ACs on a 10980XE. WEIRD! */ 4974 static BS3CPUINSTR3_TEST3_T const s_aTests16[] = 4975 { 4976 { bs3CpuInstr3_movddup_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4977 { bs3CpuInstr3_movddup_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4978 4979 { bs3CpuInstr3_vmovddup_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4980 { bs3CpuInstr3_vmovddup_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4981 4982 { bs3CpuInstr3_vmovddup_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4983 { bs3CpuInstr3_vmovddup_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4984 }; 4985 static BS3CPUINSTR3_TEST3_T const s_aTests32[] = 4986 { 4987 { bs3CpuInstr3_movddup_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4988 { bs3CpuInstr3_movddup_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4989 4990 { bs3CpuInstr3_vmovddup_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4991 { bs3CpuInstr3_vmovddup_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4992 4993 { bs3CpuInstr3_vmovddup_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4994 { bs3CpuInstr3_vmovddup_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4995 }; 4996 static BS3CPUINSTR3_TEST3_T const s_aTests64[] = 4997 { 4998 { bs3CpuInstr3_movddup_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4999 { bs3CpuInstr3_movddup_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE3, 8, 12, RT_ELEMENTS(s_aValues), s_aValues }, 5000 { bs3CpuInstr3_movddup_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 5001 { bs3CpuInstr3_movddup_XMM10_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 10, 255, RT_ELEMENTS(s_aValues), s_aValues }, 5002 5003 { bs3CpuInstr3_vmovddup_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 5004 { bs3CpuInstr3_vmovddup_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(s_aValues), s_aValues }, 5005 { bs3CpuInstr3_vmovddup_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 5006 { bs3CpuInstr3_vmovddup_XMM11_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(s_aValues), s_aValues }, 5007 5008 { bs3CpuInstr3_vmovddup_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 5009 { bs3CpuInstr3_vmovddup_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(s_aValues), s_aValues }, 5010 { bs3CpuInstr3_vmovddup_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 5011 { bs3CpuInstr3_vmovddup_YMM12_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(s_aValues), s_aValues }, 5012 }; 5013 static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 5014 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); 5015 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 5016 g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5), 0 /*cbMaxAlign*/); 5017 } 5018 5019 4865 5020 /** 4866 5021 * The 32-bit protected mode main function. … … 4878 5033 static const BS3TESTMODEBYONEENTRY g_aTests[] = 4879 5034 { 4880 #define ALL_TESTS5035 //#define ALL_TESTS 4881 5036 #if defined(ALL_TESTS) 4882 5037 { "[v]andps/[v]andpd/[v]pand", bs3CpuInstr3_v_andps_andpd_pand, 0 }, … … 4928 5083 { "[v]movlps/[v]movlpd", bs3CpuInstr3_v_movlps_movlpd, 0 }, 4929 5084 #endif 5085 { "[v]movsldup", bs3CpuInstr3_v_movsldup, 0 }, 5086 { "[v]movddup", bs3CpuInstr3_v_movddup, 0 }, 4930 5087 }; 4931 5088 Bs3TestInit("bs3-cpu-instr-3");
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