Changeset 95548 in vbox for trunk/src/VBox/ValidationKit/bootsectors
- Timestamp:
- Jul 7, 2022 12:29:09 PM (3 years ago)
- svn:sync-xref-src-repo-rev:
- 152173
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 2 edited
-
bs3-cpu-instr-3-template.mac (modified) (2 diffs)
-
bs3-cpu-instr-3.c32 (modified) (15 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac
r95545 r95548 114 114 %endmacro 115 115 116 %endif 117 118 ;; 119 ; Companion to EMIT_INSTR_PLUS_ICEBP for dealing stuff that the assmbler does 120 ; not want to emit. 121 ; 122 ; @param 1 The function name (omitting bs3CpuInstr3_ and _icebp). 123 ; @param 2+ The opcode bytes. FSxBX_PFX and FSxBX_MODRM are defined locally. 124 ; 125 %ifndef EMIT_INSTR_PLUS_ICEBP_BYTES_DEFINED 126 %define EMIT_INSTR_PLUS_ICEBP_BYTES_DEFINED 127 128 %macro EMIT_INSTR_PLUS_ICEBP_BYTES 2+ 129 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_ %+ %1 %+ _icebp 130 %define FSxBX_PFX 64h 131 %if TMPL_BITS == 16 132 %define FSxBX_MODRM 07h 133 %else 134 %define FSxBX_MODRM 03h 135 %endif 136 db %2 137 %undef FSxBX_MODRM 138 %undef FSxBX_PFX 139 .again: 140 icebp 141 jmp .again 142 BS3_PROC_END_CMN bs3CpuInstr3_ %+ %1 %+ _icebp 143 %endmacro 116 144 %endif 117 145 … … 1194 1222 %endif 1195 1223 1224 ; 1225 ; [V]MOVD 1226 ; 1227 EMIT_INSTR_PLUS_ICEBP movd, MM1, EDX 1228 EMIT_INSTR_PLUS_ICEBP movd, MM1, FSxBX 1229 EMIT_INSTR_PLUS_ICEBP movd, EAX, MM1 1230 EMIT_INSTR_PLUS_ICEBP movd, FSxBX, MM1 1231 %if TMPL_BITS == 64 1232 EMIT_INSTR_PLUS_ICEBP movd, MM1, R9D 1233 EMIT_INSTR_PLUS_ICEBP movd, R10D, MM0 1234 %endif 1235 1236 EMIT_INSTR_PLUS_ICEBP movd, XMM1, EAX 1237 EMIT_INSTR_PLUS_ICEBP movd, XMM1, FSxBX 1238 EMIT_INSTR_PLUS_ICEBP movd, FSxBX, XMM1 1239 EMIT_INSTR_PLUS_ICEBP movd, EAX, XMM1 1240 %if TMPL_BITS == 64 1241 EMIT_INSTR_PLUS_ICEBP movd, XMM9, R8D 1242 EMIT_INSTR_PLUS_ICEBP movd, R8D, XMM9 1243 EMIT_INSTR_PLUS_ICEBP movd, XMM9, FSxBX 1244 EMIT_INSTR_PLUS_ICEBP movd, FSxBX, XMM9 1245 %endif 1246 1247 EMIT_INSTR_PLUS_ICEBP vmovd, XMM1, EAX 1248 EMIT_INSTR_PLUS_ICEBP vmovd, XMM1, FSxBX 1249 EMIT_INSTR_PLUS_ICEBP vmovd, FSxBX, XMM1 1250 EMIT_INSTR_PLUS_ICEBP vmovd, EDX, XMM1 1251 %if TMPL_BITS == 64 1252 EMIT_INSTR_PLUS_ICEBP vmovd, XMM9, R9D 1253 EMIT_INSTR_PLUS_ICEBP vmovd, R8D, XMM9 1254 EMIT_INSTR_PLUS_ICEBP vmovd, XMM9, FSxBX 1255 EMIT_INSTR_PLUS_ICEBP vmovd, FSxBX, XMM9 1256 %endif 1257 1258 ; 1259 ; [V]MOVQ - some hand coded stuff here as the assembler prefers the 7f/6f variants. 1260 ; 1261 EMIT_INSTR_PLUS_ICEBP movq, MM1, MM2 1262 EMIT_INSTR_PLUS_ICEBP movq, MM1, FSxBX 1263 EMIT_INSTR_PLUS_ICEBP movq, FSxBX, MM1 1264 %if TMPL_BITS == 64 1265 EMIT_INSTR_PLUS_ICEBP movq, R9, MM1 1266 EMIT_INSTR_PLUS_ICEBP movq, MM1, R9 1267 EMIT_INSTR_PLUS_ICEBP_BYTES 06e_movq_MM1_FSxBX, FSxBX_PFX, 48h, 0fh, 06eh, FSxBX_MODRM | (1 << X86_MODRM_REG_SHIFT) 1268 EMIT_INSTR_PLUS_ICEBP_BYTES 07e_movq_FSxBX_MM1, FSxBX_PFX, 48h, 0fh, 07eh, FSxBX_MODRM | (1 << X86_MODRM_REG_SHIFT) 1269 %endif 1270 1271 EMIT_INSTR_PLUS_ICEBP movq, XMM1, XMM2 1272 EMIT_INSTR_PLUS_ICEBP movq, XMM1, FSxBX 1273 EMIT_INSTR_PLUS_ICEBP movq, FSxBX, XMM1 1274 %if TMPL_BITS == 64 1275 EMIT_INSTR_PLUS_ICEBP movq, XMM9, R8 1276 EMIT_INSTR_PLUS_ICEBP movq, R8, XMM9 1277 EMIT_INSTR_PLUS_ICEBP movq, XMM9, FSxBX 1278 EMIT_INSTR_PLUS_ICEBP movq, FSxBX, XMM9 1279 EMIT_INSTR_PLUS_ICEBP_BYTES 06e_movq_XMM1_FSxBX, FSxBX_PFX, 66h, 48h, 0fh, 06eh, FSxBX_MODRM | (1 << X86_MODRM_REG_SHIFT) 1280 EMIT_INSTR_PLUS_ICEBP_BYTES 06e_movq_XMM9_FSxBX, FSxBX_PFX, 66h, 4ch, 0fh, 06eh, FSxBX_MODRM | (1 << X86_MODRM_REG_SHIFT) 1281 EMIT_INSTR_PLUS_ICEBP_BYTES 07e_movq_FSxBX_XMM1, FSxBX_PFX, 66h, 48h, 0fh, 07eh, FSxBX_MODRM | (1 << X86_MODRM_REG_SHIFT) 1282 EMIT_INSTR_PLUS_ICEBP_BYTES 07e_movq_FSxBX_XMM9, FSxBX_PFX, 66h, 4ch, 0fh, 07eh, FSxBX_MODRM | (1 << X86_MODRM_REG_SHIFT) 1283 %endif 1284 1285 EMIT_INSTR_PLUS_ICEBP vmovq, XMM1, XMM2 1286 EMIT_INSTR_PLUS_ICEBP vmovq, XMM1, FSxBX 1287 EMIT_INSTR_PLUS_ICEBP_BYTES 06e_vmovq_XMM1_FSxBX, FSxBX_PFX, 0c4h, 0e1h, 0f9h, 06eh, FSxBX_MODRM | (1 << X86_MODRM_REG_SHIFT) 1288 EMIT_INSTR_PLUS_ICEBP vmovq, FSxBX, XMM1 1289 EMIT_INSTR_PLUS_ICEBP_BYTES 07e_vmovq_FSxBX_XMM1, FSxBX_PFX, 0c4h, 0e1h, 0f9h, 07eh, FSxBX_MODRM | (1 << X86_MODRM_REG_SHIFT) 1290 %if TMPL_BITS == 64 1291 EMIT_INSTR_PLUS_ICEBP vmovq, XMM9, R8 1292 EMIT_INSTR_PLUS_ICEBP vmovq, R8, XMM9 1293 EMIT_INSTR_PLUS_ICEBP vmovq, XMM9, FSxBX 1294 EMIT_INSTR_PLUS_ICEBP vmovq, FSxBX, XMM9 1295 EMIT_INSTR_PLUS_ICEBP_BYTES 06e_vmovq_XMM9_FSxBX, FSxBX_PFX, 0c4h, 061h, 0f9h, 06eh, FSxBX_MODRM | (1 << X86_MODRM_REG_SHIFT) 1296 EMIT_INSTR_PLUS_ICEBP_BYTES 07e_vmovq_FSxBX_XMM9, FSxBX_PFX, 0c4h, 061h, 0f9h, 07eh, FSxBX_MODRM | (1 << X86_MODRM_REG_SHIFT) 1297 %endif 1298 1196 1299 1197 1300 %endif ; BS3_INSTANTIATING_CMN -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32
r95545 r95548 3815 3815 typedef struct BS3CPUINSTR3_TEST2_VALUES_T 3816 3816 { 3817 RTUINT256U u Src;3818 uint64_t u DstOut;3817 RTUINT256U uMedia; 3818 uint64_t uGpr; 3819 3819 } BS3CPUINSTR3_TEST2_VALUES_T; 3820 3820 … … 3825 3825 uint8_t enmRm; 3826 3826 uint8_t enmType; 3827 uint8_t cb Dst;3828 uint8_t cBits DstValMask;3827 uint8_t cbGpr; 3828 uint8_t cBitsGprValMask; 3829 3829 bool fInvalidEncoding; 3830 uint8_t iRegDst; 3831 uint8_t iRegSrc; 3830 bool fGprDst; 3831 uint8_t iGprReg; 3832 uint8_t iMediaReg; 3832 3833 uint8_t cValues; 3833 3834 BS3CPUINSTR3_TEST2_VALUES_T const BS3_FAR *paValues; … … 3872 3873 Bs3RegCtxSaveForMode(&Ctx, bMode, 1024); 3873 3874 bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx); 3874 //Bs3TestPrintf("FTW=%#x mm1/st1=%.16Rhxs\n", pExtCtx->Ctx.x87.FTW, &pExtCtx->Ctx.x87.aRegs[1]);3875 3875 3876 3876 /* … … 3896 3896 uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1]; 3897 3897 unsigned const cValues = paTests[iTest].cValues; 3898 bool const fGprDst = paTests[iTest].fGprDst; 3898 3899 bool const fMmxInstr = paTests[iTest].enmType < T_SSE; 3899 3900 bool const fSseInstr = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128; … … 3901 3902 uint8_t const cbOperand = paTests[iTest].enmType < T_128BITS ? 64/8 3902 3903 : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8; 3903 uint8_t const cbMemOp = cbOperand;3904 uint8_t const cbMemOp = bs3CpuInstr3MemOpSize(cbOperand, paTests[iTest].enmRm); 3904 3905 uint8_t const cbAlign = RT_MIN(cbOperand, 16); 3905 3906 PRTUINT256U puMemOp = bs3CpuInstr3BufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg]); … … 3909 3910 : fSseInstr ? paConfigs[iCfg].bXcptSse 3910 3911 : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx; 3911 uint64_t const f DstValMask = paTests[iTest].cBitsDstValMask == 64 ? UINT64_MAX3912 : RT_BIT_64(paTests[iTest].cBits DstValMask) - 1;3912 uint64_t const fGprValMask = paTests[iTest].cBitsGprValMask == 64 ? UINT64_MAX 3913 : RT_BIT_64(paTests[iTest].cBitsGprValMask) - 1; 3913 3914 uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10; 3914 3915 unsigned iVal; … … 3942 3943 * Set up the context and some expectations. 3943 3944 */ 3944 /* dest */ 3945 if (paTests[iTest].iRegDst == UINT8_MAX) 3945 if (fGprDst) 3946 3946 { 3947 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); 3948 Bs3MemSet(puMemOp, 0xcc, cbMemOp); 3949 Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect)); 3950 if (bXcptExpect == X86_XCPT_DB) 3951 switch (paTests[iTest].cbDst) 3947 /* dest - gpr/mem */ 3948 if (paTests[iTest].iGprReg == UINT8_MAX) 3949 { 3950 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); 3951 Bs3MemSet(puMemOp, 0xcc, cbMemOp); 3952 if (bXcptExpect != X86_XCPT_DB) 3953 Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect)); 3954 else 3952 3955 { 3953 case 1: uMemOpExpect.au8[0] = (uint8_t) (paValues[iVal].uDstOut & fDstValMask); break; 3954 case 2: uMemOpExpect.au16[0] = (uint16_t)(paValues[iVal].uDstOut & fDstValMask); break; 3955 case 4: uMemOpExpect.au32[0] = (uint32_t)(paValues[iVal].uDstOut & fDstValMask); break; 3956 case 8: uMemOpExpect.au64[0] = (paValues[iVal].uDstOut & fDstValMask); break; 3957 default: BS3_ASSERT(0); 3956 Bs3MemSet(&uMemOpExpect, 0xaa, sizeof(uMemOpExpect)); 3957 switch (paTests[iTest].cbGpr) 3958 { 3959 case 1: uMemOpExpect.au8[0] = (uint8_t) (paValues[iVal].uGpr & fGprValMask); break; 3960 case 2: uMemOpExpect.au16[0] = (uint16_t)(paValues[iVal].uGpr & fGprValMask); break; 3961 case 4: uMemOpExpect.au32[0] = (uint32_t)(paValues[iVal].uGpr & fGprValMask); break; 3962 case 8: uMemOpExpect.au64[0] = (paValues[iVal].uGpr & fGprValMask); break; 3963 default: BS3_ASSERT(0); 3964 } 3958 3965 } 3966 } 3967 else 3968 Bs3RegCtxSetGpr(&Ctx, paTests[iTest].iGprReg, UINT64_C(0xcccccccccccccccc), 3969 BS3_MODE_IS_64BIT_CODE(bMode) ? 8 : 4); /* we only restore 63:32 when bMode==LM64 */ 3970 3971 /* source - media/mem */ 3972 if (paTests[iTest].iMediaReg == UINT8_MAX) 3973 { 3974 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); 3975 BS3_ASSERT(paTests[iTest].iGprReg != UINT8_MAX); 3976 Bs3MemCpy(puMemOp, &paValues[iVal].uMedia, cbMemOp); 3977 uMemOpExpect = paValues[iVal].uMedia; 3978 } 3979 else if (fMmxInstr) 3980 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iMediaReg, paValues[iVal].uMedia.QWords.qw0, BS3EXTCTXTOPMM_ZERO); 3981 else if (fSseInstr) 3982 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iMediaReg, &paValues[iVal].uMedia.DQWords.dqw0); 3983 else 3984 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMediaReg, &paValues[iVal].uMedia, 32); 3959 3985 } 3960 3961 /* source */ 3962 if (paTests[iTest].iRegSrc == UINT8_MAX) 3986 else 3963 3987 { 3964 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); 3965 BS3_ASSERT(paTests[iTest].iRegDst != UINT8_MAX); 3966 Bs3MemCpy(puMemOp, &paValues[iVal].uSrc, cbMemOp); 3967 uMemOpExpect = paValues[iVal].uSrc; 3988 /* dest - media */ 3989 if (paTests[iTest].iMediaReg == UINT8_MAX) 3990 { 3991 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); 3992 Bs3MemSet(puMemOp, 0xcc, cbMemOp); 3993 if (bXcptExpect == X86_XCPT_DB) 3994 uMemOpExpect = paValues[iVal].uMedia; 3995 else 3996 Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect)); 3997 } 3998 3999 /* source - gpr/mem */ 4000 if (paTests[iTest].iGprReg == UINT8_MAX) 4001 { 4002 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); 4003 Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect)); 4004 if (bXcptExpect == X86_XCPT_DB) 4005 switch (paTests[iTest].cbGpr) 4006 { 4007 case 1: uMemOpExpect.au8[0] = (uint8_t) (paValues[iVal].uGpr & fGprValMask); break; 4008 case 2: uMemOpExpect.au16[0] = (uint16_t)(paValues[iVal].uGpr & fGprValMask); break; 4009 case 4: uMemOpExpect.au32[0] = (uint32_t)(paValues[iVal].uGpr & fGprValMask); break; 4010 case 8: uMemOpExpect.au64[0] = (paValues[iVal].uGpr & fGprValMask); break; 4011 default: BS3_ASSERT(0); 4012 } 4013 Bs3MemCpy(puMemOp, &uMemOpExpect, cbMemOp); 4014 } 4015 else 4016 Bs3RegCtxSetGpr(&Ctx, paTests[iTest].iGprReg, paValues[iVal].uGpr & fGprValMask, paTests[iTest].cbGpr); 3968 4017 } 3969 else if (fMmxInstr)3970 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc, paValues[iVal].uSrc.QWords.qw0, BS3EXTCTXTOPMM_ZERO);3971 else if (fSseInstr)3972 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc, &paValues[iVal].uSrc.DQWords.dqw0);3973 else3974 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc, &paValues[iVal].uSrc, 32);3975 4018 3976 4019 /* Memory pointer. */ 3977 4020 if (paTests[iTest].enmRm >= RM_MEM) 3978 4021 { 3979 BS3_ASSERT(paTests[iTest].i RegDst == UINT8_MAX || paTests[iTest].iRegSrc== UINT8_MAX);4022 BS3_ASSERT(paTests[iTest].iGprReg == UINT8_MAX || paTests[iTest].iMediaReg == UINT8_MAX); 3980 4023 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp); 3981 4024 } … … 3996 4039 Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff); 3997 4040 } 4041 if (!fGprDst && bXcptExpect == X86_XCPT_DB && paTests[iTest].iMediaReg != UINT8_MAX) 4042 { 4043 if (fMmxInstr) 4044 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iMediaReg, paValues[iVal].uMedia.QWords.qw0, BS3EXTCTXTOPMM_SET); 4045 else if (fSseInstr) 4046 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iMediaReg, &paValues[iVal].uMedia.DQWords.dqw0); 4047 else 4048 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMediaReg, &paValues[iVal].uMedia, 32); 4049 } 3998 4050 Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep); 3999 4051 … … 4001 4053 Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt); 4002 4054 4003 if (bXcptExpect == X86_XCPT_DB && paTests[iTest].iRegDst != UINT8_MAX) 4004 Bs3RegCtxSetGpr(&Ctx, paTests[iTest].iRegDst, paValues[iVal].uDstOut & fDstValMask, paTests[iTest].cbDst); 4055 if (fGprDst && bXcptExpect == X86_XCPT_DB && paTests[iTest].iGprReg != UINT8_MAX) 4056 Bs3RegCtxSetGpr(&Ctx, paTests[iTest].iGprReg, paValues[iVal].uGpr & fGprValMask, 4057 paTests[iTest].cbGpr >= 4 ? 8 : paTests[iTest].cbGpr); 4005 4058 /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */ 4006 4059 if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC)) … … 4015 4068 4016 4069 if ( paTests[iTest].enmRm >= RM_MEM 4017 && Bs3MemCmp(puMemOp, &uMemOpExpect, cb Operand) != 0)4070 && Bs3MemCmp(puMemOp, &uMemOpExpect, cbMemOp) != 0) 4018 4071 Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &uMemOpExpect, cbMemOp, puMemOp); 4019 4072 … … 4082 4135 static BS3CPUINSTR3_TEST2_T const s_aTests16[] = 4083 4136 { 4084 { bs3CpuInstr3_pmovmskb_EAX_MM2_icebp_c16, 255, RM_REG, T_AXMMX_OR_SSE, 4, 8, false, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },4085 { bs3CpuInstr3_pmovmskb_EAX_qword_FSxBX_icebp_c16, 255, RM_MEM, T_AXMMX_OR_SSE, 4, 8, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },4086 { bs3CpuInstr3_pmovmskb_EAX_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 4, 16, false, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },4087 { bs3CpuInstr3_pmovmskb_EAX_dqword_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 4, 16, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },4088 { bs3CpuInstr3_vpmovmskb_EAX_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 4, 16, false, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },4089 { bs3CpuInstr3_vpmovmskb_EAX_dqword_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 4, 16, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },4090 { bs3CpuInstr3_vpmovmskb_EAX_YMM2_icebp_c16, 255, RM_REG, T_AVX2_256, 4, 32, false, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },4091 { bs3CpuInstr3_vpmovmskb_EAX_qqword_FSxBX_icebp_c16, 255, RM_MEM, T_AVX2_256, 4, 32, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },4137 { bs3CpuInstr3_pmovmskb_EAX_MM2_icebp_c16, 255, RM_REG, T_AXMMX_OR_SSE, 4, 8, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4138 { bs3CpuInstr3_pmovmskb_EAX_qword_FSxBX_icebp_c16, 255, RM_MEM, T_AXMMX_OR_SSE, 4, 8, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4139 { bs3CpuInstr3_pmovmskb_EAX_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 4, 16, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4140 { bs3CpuInstr3_pmovmskb_EAX_dqword_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 4, 16, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4141 { bs3CpuInstr3_vpmovmskb_EAX_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 4, 16, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4142 { bs3CpuInstr3_vpmovmskb_EAX_dqword_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 4, 16, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4143 { bs3CpuInstr3_vpmovmskb_EAX_YMM2_icebp_c16, 255, RM_REG, T_AVX2_256, 4, 32, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4144 { bs3CpuInstr3_vpmovmskb_EAX_qqword_FSxBX_icebp_c16, 255, RM_MEM, T_AVX2_256, 4, 32, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4092 4145 }; 4093 4146 static BS3CPUINSTR3_TEST2_T const s_aTests32[] = 4094 4147 { 4095 { bs3CpuInstr3_pmovmskb_EAX_MM2_icebp_c32, 255, RM_REG, T_AXMMX_OR_SSE, 4, 8, false, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },4096 { bs3CpuInstr3_pmovmskb_EAX_qword_FSxBX_icebp_c32, 255, RM_MEM, T_AXMMX_OR_SSE, 4, 8, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },4097 { bs3CpuInstr3_pmovmskb_EAX_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 4, 16, false, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },4098 { bs3CpuInstr3_pmovmskb_EAX_dqword_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 4, 16, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },4099 { bs3CpuInstr3_vpmovmskb_EAX_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 4, 16, false, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },4100 { bs3CpuInstr3_vpmovmskb_EAX_dqword_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 4, 16, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },4101 { bs3CpuInstr3_vpmovmskb_EAX_YMM2_icebp_c32, 255, RM_REG, T_AVX2_256, 4, 32, false, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },4102 { bs3CpuInstr3_vpmovmskb_EAX_qqword_FSxBX_icebp_c32, 255, RM_MEM, T_AVX2_256, 4, 32, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },4148 { bs3CpuInstr3_pmovmskb_EAX_MM2_icebp_c32, 255, RM_REG, T_AXMMX_OR_SSE, 4, 8, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4149 { bs3CpuInstr3_pmovmskb_EAX_qword_FSxBX_icebp_c32, 255, RM_MEM, T_AXMMX_OR_SSE, 4, 8, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4150 { bs3CpuInstr3_pmovmskb_EAX_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 4, 16, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4151 { bs3CpuInstr3_pmovmskb_EAX_dqword_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 4, 16, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4152 { bs3CpuInstr3_vpmovmskb_EAX_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 4, 16, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4153 { bs3CpuInstr3_vpmovmskb_EAX_dqword_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 4, 16, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4154 { bs3CpuInstr3_vpmovmskb_EAX_YMM2_icebp_c32, 255, RM_REG, T_AVX2_256, 4, 32, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4155 { bs3CpuInstr3_vpmovmskb_EAX_qqword_FSxBX_icebp_c32, 255, RM_MEM, T_AVX2_256, 4, 32, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4103 4156 }; 4104 4157 static BS3CPUINSTR3_TEST2_T const s_aTests64[] = 4105 4158 { 4106 { bs3CpuInstr3_pmovmskb_EAX_MM2_icebp_c64, 255, RM_REG, T_AXMMX_OR_SSE, 8, 8, false, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },4107 { bs3CpuInstr3_pmovmskb_EAX_qword_FSxBX_icebp_c64, 255, RM_MEM, T_AXMMX_OR_SSE, 8, 8, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },4108 { bs3CpuInstr3_pmovmskb_EAX_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 8, 16, false, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },4109 { bs3CpuInstr3_pmovmskb_EAX_dqword_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 16, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },4110 { bs3CpuInstr3_vpmovmskb_EAX_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 8, 16, false, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },4111 { bs3CpuInstr3_vpmovmskb_EAX_dqword_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 8, 16, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },4112 { bs3CpuInstr3_vpmovmskb_EAX_YMM2_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 32, false, 0, 2, RT_ELEMENTS(s_aValues), s_aValues },4113 { bs3CpuInstr3_vpmovmskb_EAX_qqword_FSxBX_icebp_c64, 255, RM_MEM, T_AVX2_256, 8, 32, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues },4114 { bs3CpuInstr3_vpmovmskb_RAX_YMM9_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 32, false, 0, 9, RT_ELEMENTS(s_aValues), s_aValues },4159 { bs3CpuInstr3_pmovmskb_EAX_MM2_icebp_c64, 255, RM_REG, T_AXMMX_OR_SSE, 8, 8, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4160 { bs3CpuInstr3_pmovmskb_EAX_qword_FSxBX_icebp_c64, 255, RM_MEM, T_AXMMX_OR_SSE, 8, 8, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4161 { bs3CpuInstr3_pmovmskb_EAX_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 8, 16, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4162 { bs3CpuInstr3_pmovmskb_EAX_dqword_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 16, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4163 { bs3CpuInstr3_vpmovmskb_EAX_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 8, 16, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4164 { bs3CpuInstr3_vpmovmskb_EAX_dqword_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 8, 16, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4165 { bs3CpuInstr3_vpmovmskb_EAX_YMM2_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 32, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, 4166 { bs3CpuInstr3_vpmovmskb_EAX_qqword_FSxBX_icebp_c64, 255, RM_MEM, T_AVX2_256, 8, 32, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 4167 { bs3CpuInstr3_vpmovmskb_RAX_YMM9_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 32, false, true, 0, 9, RT_ELEMENTS(s_aValues), s_aValues }, 4115 4168 }; 4116 4169 static BS3CPUINSTR3_TEST2_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST2_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); … … 4119 4172 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); 4120 4173 } 4174 4175 4176 /* 4177 * [V]MOVD / [V]MOVQ - greg/mem variants only. 4178 */ 4179 4180 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movd_MM1_EDX_icebp); 4181 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movd_MM1_FSxBX_icebp); 4182 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movd_EAX_MM1_icebp); 4183 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movd_FSxBX_MM1_icebp); 4184 extern FNBS3FAR bs3CpuInstr3_movd_MM1_R9D_icebp_c64; 4185 extern FNBS3FAR bs3CpuInstr3_movd_R10D_MM0_icebp_c64; 4186 4187 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movd_XMM1_EAX_icebp); 4188 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movd_XMM1_FSxBX_icebp); 4189 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movd_EAX_XMM1_icebp); 4190 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movd_FSxBX_XMM1_icebp); 4191 extern FNBS3FAR bs3CpuInstr3_movd_XMM9_R8D_icebp_c64; 4192 extern FNBS3FAR bs3CpuInstr3_movd_R8D_XMM9_icebp_c64; 4193 extern FNBS3FAR bs3CpuInstr3_movd_XMM9_FSxBX_icebp_c64; 4194 extern FNBS3FAR bs3CpuInstr3_movd_FSxBX_XMM9_icebp_c64; 4195 4196 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovd_XMM1_EAX_icebp); 4197 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovd_XMM1_FSxBX_icebp); 4198 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovd_EDX_XMM1_icebp); 4199 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovd_FSxBX_XMM1_icebp); 4200 extern FNBS3FAR bs3CpuInstr3_vmovd_XMM9_R9D_icebp_c64; 4201 extern FNBS3FAR bs3CpuInstr3_vmovd_R8D_XMM9_icebp_c64; 4202 extern FNBS3FAR bs3CpuInstr3_vmovd_XMM9_FSxBX_icebp_c64; 4203 extern FNBS3FAR bs3CpuInstr3_vmovd_FSxBX_XMM9_icebp_c64; 4204 4205 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movq_MM1_MM2_icebp); 4206 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movq_MM1_FSxBX_icebp); 4207 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movq_FSxBX_MM1_icebp); 4208 extern FNBS3FAR bs3CpuInstr3_movq_R9_MM1_icebp_c64; 4209 extern FNBS3FAR bs3CpuInstr3_06e_movq_MM1_FSxBX_icebp_c64; 4210 extern FNBS3FAR bs3CpuInstr3_07e_movq_FSxBX_MM1_icebp_c64; 4211 extern FNBS3FAR bs3CpuInstr3_movq_MM1_R9_icebp_c64; 4212 4213 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movq_XMM1_XMM2_icebp); 4214 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movq_XMM1_FSxBX_icebp); 4215 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movq_FSxBX_XMM1_icebp); 4216 extern FNBS3FAR bs3CpuInstr3_movq_XMM9_R8_icebp_c64; 4217 extern FNBS3FAR bs3CpuInstr3_movq_R8_XMM9_icebp_c64; 4218 extern FNBS3FAR bs3CpuInstr3_movq_XMM9_FSxBX_icebp_c64; 4219 extern FNBS3FAR bs3CpuInstr3_movq_FSxBX_XMM9_icebp_c64; 4220 extern FNBS3FAR bs3CpuInstr3_06e_movq_XMM1_FSxBX_icebp_c64; 4221 extern FNBS3FAR bs3CpuInstr3_06e_movq_XMM9_FSxBX_icebp_c64; 4222 extern FNBS3FAR bs3CpuInstr3_07e_movq_FSxBX_XMM1_icebp_c64; 4223 extern FNBS3FAR bs3CpuInstr3_07e_movq_FSxBX_XMM9_icebp_c64; 4224 4225 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovq_XMM1_XMM2_icebp); 4226 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovq_XMM1_FSxBX_icebp); 4227 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovq_FSxBX_XMM1_icebp); 4228 extern FNBS3FAR bs3CpuInstr3_vmovq_XMM9_R8_icebp_c64; 4229 extern FNBS3FAR bs3CpuInstr3_vmovq_R8_XMM9_icebp_c64; 4230 extern FNBS3FAR bs3CpuInstr3_vmovq_XMM9_FSxBX_icebp_c64; 4231 extern FNBS3FAR bs3CpuInstr3_vmovq_FSxBX_XMM9_icebp_c64; 4232 extern FNBS3FAR bs3CpuInstr3_06e_vmovq_XMM1_FSxBX_icebp_c64; 4233 extern FNBS3FAR bs3CpuInstr3_06e_vmovq_XMM9_FSxBX_icebp_c64; 4234 extern FNBS3FAR bs3CpuInstr3_07e_vmovq_FSxBX_XMM1_icebp_c64; 4235 extern FNBS3FAR bs3CpuInstr3_07e_vmovq_FSxBX_XMM9_icebp_c64; 4236 4237 4238 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movd_movq(uint8_t bMode) 4239 { 4240 static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesRm[] = 4241 { 4242 { RTUINT256_INIT_C(0, 0, 0, 0), /*->*/ UINT64_C(0) }, 4243 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xffffffffffffffff) }, 4244 { RTUINT256_INIT_C(0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x7f7f7f7f7f7f7f7f) }, 4245 { RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), UINT64_C(0x8080808080808080) }, 4246 { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x5555666677778888) }, 4247 { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0x9c5ce073930996bb) }, 4248 }; 4249 static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesMediaD[] = 4250 { 4251 { RTUINT256_INIT_C(0, 0, 0, 0), /*->*/ UINT64_C(0) }, 4252 { RTUINT256_INIT_C(0, 0, 0, 0x00000000ffffffff), UINT64_C(0xffffffffffffffff) }, 4253 { RTUINT256_INIT_C(0, 0, 0, 0x000000007f7f7f7f), UINT64_C(0x7f7f7f7f7f7f7f7f) }, 4254 { RTUINT256_INIT_C(0, 0, 0, 0x0000000080808080), UINT64_C(0x8080808080808080) }, 4255 { RTUINT256_INIT_C(0, 0, 0, 0x0000000077778888), UINT64_C(0x5555666677778888) }, 4256 { RTUINT256_INIT_C(0, 0, 0, 0x00000000930996bb), UINT64_C(0x9c5ce073930996bb) }, 4257 }; 4258 static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesMediaQ[] = 4259 { 4260 { RTUINT256_INIT_C(0, 0, 0, 0), /*->*/ UINT64_C(0) }, 4261 { RTUINT256_INIT_C(0, 0, 0, 0xffffffffffffffff), UINT64_C(0xffffffffffffffff) }, 4262 { RTUINT256_INIT_C(0, 0, 0, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x7f7f7f7f7f7f7f7f) }, 4263 { RTUINT256_INIT_C(0, 0, 0, 0x8080808080808080), UINT64_C(0x8080808080808080) }, 4264 { RTUINT256_INIT_C(0, 0, 0, 0x5555666677778888), UINT64_C(0x5555666677778888) }, 4265 { RTUINT256_INIT_C(0, 0, 0, 0x9c5ce073930996bb), UINT64_C(0x9c5ce073930996bb) }, 4266 }; 4267 4268 /* Note! Seems the 256-bit variants doesn't generate \#ACs on a 10980XE. WEIRD! */ 4269 static BS3CPUINSTR3_TEST2_T const s_aTests16[] = 4270 { 4271 { bs3CpuInstr3_movd_MM1_EDX_icebp_c16, 255, RM_REG, T_MMX, 4, 32, false, false, 2, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, 4272 { bs3CpuInstr3_movd_MM1_FSxBX_icebp_c16, 255, RM_MEM32, T_MMX, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, 4273 { bs3CpuInstr3_movd_EAX_MM1_icebp_c16, 255, RM_REG, T_MMX, 4, 32, false, true, 0, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4274 { bs3CpuInstr3_movd_FSxBX_MM1_icebp_c16, 255, RM_MEM32, T_MMX, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4275 4276 { bs3CpuInstr3_movd_XMM1_EAX_icebp_c16, 255, RM_REG, T_SSE2, 4, 32, false, false, 0, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, 4277 { bs3CpuInstr3_movd_XMM1_FSxBX_icebp_c16, 255, RM_MEM32, T_SSE2, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, 4278 { bs3CpuInstr3_movd_EAX_XMM1_icebp_c16, 255, RM_REG, T_SSE2, 4, 32, false, true, 0, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4279 { bs3CpuInstr3_movd_FSxBX_XMM1_icebp_c16, 255, RM_MEM32, T_SSE2, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4280 4281 { bs3CpuInstr3_vmovd_XMM1_EAX_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, false, 0, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, 4282 { bs3CpuInstr3_vmovd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, 4283 { bs3CpuInstr3_vmovd_EDX_XMM1_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4284 { bs3CpuInstr3_vmovd_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4285 { bs3CpuInstr3_movq_MM1_FSxBX_icebp_c16, 255, RM_MEM64, T_MMX, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, 4286 { bs3CpuInstr3_movq_FSxBX_MM1_icebp_c16, 255, RM_MEM64, T_MMX, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4287 { bs3CpuInstr3_movq_XMM1_FSxBX_icebp_c16, 255, RM_MEM64, T_SSE2, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, 4288 { bs3CpuInstr3_movq_FSxBX_XMM1_icebp_c16, 255, RM_MEM64, T_SSE2, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4289 4290 { bs3CpuInstr3_vmovq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, 4291 { bs3CpuInstr3_vmovq_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4292 }; 4293 static BS3CPUINSTR3_TEST2_T const s_aTests32[] = 4294 { 4295 { bs3CpuInstr3_movd_MM1_EDX_icebp_c32, 255, RM_REG, T_MMX, 4, 32, false, false, 2, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, 4296 { bs3CpuInstr3_movd_MM1_FSxBX_icebp_c32, 255, RM_MEM32, T_MMX, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, 4297 { bs3CpuInstr3_movd_EAX_MM1_icebp_c32, 255, RM_REG, T_MMX, 4, 32, false, true, 0, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4298 { bs3CpuInstr3_movd_FSxBX_MM1_icebp_c32, 255, RM_MEM32, T_MMX, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4299 4300 { bs3CpuInstr3_movd_XMM1_EAX_icebp_c32, 255, RM_REG, T_SSE2, 4, 32, false, false, 0, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, 4301 { bs3CpuInstr3_movd_XMM1_FSxBX_icebp_c32, 255, RM_MEM32, T_SSE2, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, 4302 { bs3CpuInstr3_movd_EAX_XMM1_icebp_c32, 255, RM_REG, T_SSE2, 4, 32, false, true, 0, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4303 { bs3CpuInstr3_movd_FSxBX_XMM1_icebp_c32, 255, RM_MEM32, T_SSE2, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4304 4305 { bs3CpuInstr3_vmovd_XMM1_EAX_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, false, 0, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, 4306 { bs3CpuInstr3_vmovd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, 4307 { bs3CpuInstr3_vmovd_EDX_XMM1_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4308 { bs3CpuInstr3_vmovd_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4309 4310 { bs3CpuInstr3_movq_MM1_FSxBX_icebp_c32, 255, RM_MEM64, T_MMX, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, 4311 { bs3CpuInstr3_movq_FSxBX_MM1_icebp_c32, 255, RM_MEM64, T_MMX, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4312 4313 { bs3CpuInstr3_movq_XMM1_FSxBX_icebp_c32, 255, RM_MEM64, T_SSE2, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, 4314 { bs3CpuInstr3_movq_FSxBX_XMM1_icebp_c32, 255, RM_MEM64, T_SSE2, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4315 4316 { bs3CpuInstr3_vmovq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, 4317 { bs3CpuInstr3_vmovq_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4318 }; 4319 static BS3CPUINSTR3_TEST2_T const s_aTests64[] = 4320 { 4321 { bs3CpuInstr3_movd_MM1_EDX_icebp_c64, 255, RM_REG, T_MMX, 4, 32, false, false, 2, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, 4322 { bs3CpuInstr3_movd_MM1_R9D_icebp_c64, 255, RM_REG, T_MMX, 4, 32, false, false, 9, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, 4323 { bs3CpuInstr3_movd_MM1_FSxBX_icebp_c64, 255, RM_MEM32, T_MMX, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, 4324 { bs3CpuInstr3_movd_EAX_MM1_icebp_c64, 255, RM_REG, T_MMX, 4, 32, false, true, 0, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4325 { bs3CpuInstr3_movd_R10D_MM0_icebp_c64, 255, RM_REG, T_MMX, 4, 32, false, true, 10, 0, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4326 { bs3CpuInstr3_movd_FSxBX_MM1_icebp_c64, 255, RM_MEM32, T_MMX, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4327 4328 { bs3CpuInstr3_movd_XMM1_EAX_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, false, 0, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, 4329 { bs3CpuInstr3_movd_XMM9_R8D_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, false, 8, 9, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, 4330 { bs3CpuInstr3_movd_XMM1_FSxBX_icebp_c64, 255, RM_MEM32, T_SSE2, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, 4331 { bs3CpuInstr3_movd_XMM9_FSxBX_icebp_c64, 255, RM_MEM32, T_SSE2, 4, 32, false, false, 255, 9, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, 4332 { bs3CpuInstr3_movd_EAX_XMM1_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, true, 0, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4333 { bs3CpuInstr3_movd_R8D_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, true, 8, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4334 { bs3CpuInstr3_movd_FSxBX_XMM1_icebp_c64, 255, RM_MEM32, T_SSE2, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4335 4336 { bs3CpuInstr3_vmovd_XMM1_EAX_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, false, 0, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, 4337 { bs3CpuInstr3_vmovd_XMM9_R9D_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, false, 9, 9, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, 4338 { bs3CpuInstr3_vmovd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, 4339 { bs3CpuInstr3_vmovd_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, false, 255, 9, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, 4340 { bs3CpuInstr3_vmovd_EDX_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4341 { bs3CpuInstr3_vmovd_R8D_XMM9_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 8, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4342 { bs3CpuInstr3_vmovd_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4343 { bs3CpuInstr3_vmovd_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4344 4345 { bs3CpuInstr3_movq_MM1_R9_icebp_c64, 255, RM_REG, T_MMX, 8, 64, false, false, 9, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4346 { bs3CpuInstr3_movq_MM1_FSxBX_icebp_c64, 255, RM_MEM64, T_MMX, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, 4347 { bs3CpuInstr3_06e_movq_MM1_FSxBX_icebp_c64, 255, RM_MEM64, T_MMX, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, 4348 { bs3CpuInstr3_movq_R9_MM1_icebp_c64, 255, RM_REG, T_MMX, 8, 64, false, true, 9, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4349 { bs3CpuInstr3_movq_FSxBX_MM1_icebp_c64, 255, RM_MEM64, T_MMX, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4350 { bs3CpuInstr3_07e_movq_FSxBX_MM1_icebp_c64, 255, RM_MEM64, T_MMX, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4351 4352 { bs3CpuInstr3_movq_XMM9_R8_icebp_c64, 255, RM_REG, T_SSE2, 8, 64, false, false, 8, 9, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, 4353 { bs3CpuInstr3_movq_XMM1_FSxBX_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, 4354 { bs3CpuInstr3_06e_movq_XMM1_FSxBX_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, 4355 { bs3CpuInstr3_movq_XMM9_FSxBX_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, false, 255, 9, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, 4356 { bs3CpuInstr3_06e_movq_XMM9_FSxBX_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, false, 255, 9, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, 4357 { bs3CpuInstr3_movq_R8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 64, false, true, 8, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4358 { bs3CpuInstr3_movq_FSxBX_XMM1_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4359 { bs3CpuInstr3_07e_movq_FSxBX_XMM1_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4360 { bs3CpuInstr3_movq_FSxBX_XMM9_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, true, 255, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4361 { bs3CpuInstr3_07e_movq_FSxBX_XMM9_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, true, 255, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4362 4363 { bs3CpuInstr3_vmovq_XMM9_R8_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, false, false, 8, 9, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, 4364 { bs3CpuInstr3_vmovq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, 4365 { bs3CpuInstr3_06e_vmovq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, 4366 { bs3CpuInstr3_vmovq_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, false, 255, 9, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, 4367 { bs3CpuInstr3_06e_vmovq_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, false, 255, 9, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, 4368 { bs3CpuInstr3_vmovq_R8_XMM9_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, false, true, 8, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4369 { bs3CpuInstr3_vmovq_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4370 { bs3CpuInstr3_07e_vmovq_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4371 { bs3CpuInstr3_vmovq_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4372 { bs3CpuInstr3_07e_vmovq_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, 4373 }; 4374 static BS3CPUINSTR3_TEST2_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST2_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 4375 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); 4376 return bs3CpuInstr3_WorkerTestType2(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 4377 g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); 4378 } 4379 4380 4121 4381 4122 4382 … … 5368 5628 5369 5629 5630 5370 5631 /** 5371 5632 * The 32-bit protected mode main function. … … 5383 5644 static const BS3TESTMODEBYONEENTRY g_aTests[] = 5384 5645 { 5385 #define ALL_TESTS 5646 #ifndef DEBUG_bird 5647 # define ALL_TESTS 5648 #endif 5386 5649 #if defined(ALL_TESTS) 5387 5650 { "[v]andps/[v]andpd/[v]pand", bs3CpuInstr3_v_andps_andpd_pand, 0 }, … … 5438 5701 { "[v]movddup", bs3CpuInstr3_v_movddup, 0 }, 5439 5702 { "[v]movaps_movapd", bs3CpuInstr3_v_movaps_movapd, 0 }, 5703 { "[v]movd_movq", bs3CpuInstr3_v_movd_movq, 0 }, 5440 5704 #endif 5441 5705 };
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