Changeset 95577 in vbox for trunk/src/VBox
- Timestamp:
- Jul 8, 2022 11:18:23 PM (3 years ago)
- svn:sync-xref-src-repo-rev:
- 152204
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 2 edited
-
bs3-cpu-instr-3-template.mac (modified) (1 diff)
-
bs3-cpu-instr-3.c32 (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac
r95553 r95577 1368 1368 %endif 1369 1369 1370 ; 1371 ; [V]PTEST 1372 ; 1373 EMIT_INSTR_PLUS_ICEBP ptest, XMM1, XMM2 1374 EMIT_INSTR_PLUS_ICEBP ptest, XMM1, FSxBX 1375 EMIT_INSTR_PLUS_ICEBP vptest, XMM1, XMM2 1376 EMIT_INSTR_PLUS_ICEBP vptest, XMM1, FSxBX 1377 EMIT_INSTR_PLUS_ICEBP vptest, YMM1, YMM2 1378 EMIT_INSTR_PLUS_ICEBP vptest, YMM1, FSxBX 1379 %if TMPL_BITS == 64 1380 EMIT_INSTR_PLUS_ICEBP ptest, XMM9, XMM8 1381 EMIT_INSTR_PLUS_ICEBP ptest, XMM9, FSxBX 1382 EMIT_INSTR_PLUS_ICEBP vptest, XMM9, XMM8 1383 EMIT_INSTR_PLUS_ICEBP vptest, XMM9, FSxBX 1384 EMIT_INSTR_PLUS_ICEBP vptest, YMM9, YMM8 1385 EMIT_INSTR_PLUS_ICEBP vptest, YMM9, FSxBX 1386 %endif 1387 1370 1388 1371 1389 %endif ; BS3_INSTANTIATING_CMN -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32
r95553 r95577 4382 4382 4383 4383 /* 4384 * Test type #3 .4384 * Test type #3 - two MM/XMM/YMM operands, no flags. 4385 4385 */ 4386 4386 … … 4589 4589 if (cErrors != Bs3TestSubErrorCount()) 4590 4590 { 4591 /*if (paConfigs[iCfg].fAligned)4591 if (paConfigs[iCfg].fAligned) 4592 4592 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x)", 4593 4593 bRing, iCfg, iTest, iVal, bXcptExpect); 4594 else */4594 else 4595 4595 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)", 4596 4596 bRing, iCfg, iTest, iVal, bXcptExpect, puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0); … … 5863 5863 return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 5864 5864 g_aXcptConfig1, RT_ELEMENTS(g_aXcptConfig1), 255 /*cbMaxAlign*/); 5865 } 5866 5867 5868 5869 /* 5870 * Test type #4 - two source MM/XMM/YMM operands, outputs only eflags. 5871 * 5872 * Probably only used by the PTEST instruction. 5873 */ 5874 5875 typedef struct BS3CPUINSTR3_TEST4_VALUES_T 5876 { 5877 RTUINT256U uSrc2; 5878 RTUINT256U uSrc1; 5879 uint16_t afEflOut[3]; /* [0]=MM result, [1]=XMM result, [2]=YMM result */ 5880 } BS3CPUINSTR3_TEST4_VALUES_T; 5881 5882 typedef struct BS3CPUINSTR3_TEST4_T 5883 { 5884 FPFNBS3FAR pfnWorker; 5885 uint8_t bAvxMisalignXcpt; 5886 uint8_t enmRm; 5887 uint8_t enmType; 5888 uint8_t iRegSrc1; 5889 uint8_t iRegSrc2; 5890 uint8_t cValues; 5891 BS3CPUINSTR3_TEST4_VALUES_T const BS3_FAR *paValues; 5892 } BS3CPUINSTR3_TEST4_T; 5893 5894 typedef struct BS3CPUINSTR3_TEST4_MODE_T 5895 { 5896 BS3CPUINSTR3_TEST4_T const BS3_FAR *paTests; 5897 unsigned cTests; 5898 } BS3CPUINSTR3_TEST4_MODE_T; 5899 5900 /** Initializer for a BS3CPUINSTR3_TEST4_MODE_T array (three entries). */ 5901 #define BS3CPUINSTR3_TEST4_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \ 5902 { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } } 5903 5904 5905 /** 5906 * Test type #4 worker. 5907 */ 5908 static uint8_t bs3CpuInstr3_WorkerTestType4(uint8_t bMode, BS3CPUINSTR3_TEST4_T const BS3_FAR *paTests, unsigned cTests, 5909 PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs, uint32_t fEflCheck) 5910 { 5911 BS3REGCTX Ctx; 5912 BS3TRAPFRAME TrapFrame; 5913 const char BS3_FAR * const pszMode = Bs3GetModeName(bMode); 5914 uint8_t BS3_FAR *pbBuf = g_pbBuf; 5915 uint32_t cbBuf = g_cbBuf; 5916 uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0; 5917 PBS3EXTCTX pExtCtxOut; 5918 PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut); 5919 if (!pExtCtx) 5920 return 0; 5921 5922 /* Ensure the structures are allocated before we sample the stack pointer. */ 5923 Bs3MemSet(&Ctx, 0, sizeof(Ctx)); 5924 Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); 5925 5926 /* 5927 * Create test context. 5928 */ 5929 Bs3RegCtxSaveForMode(&Ctx, bMode, 1024); 5930 bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx); 5931 pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode); 5932 5933 /* 5934 * Run the tests in all rings since alignment issues may behave 5935 * differently in ring-3 compared to ring-0. 5936 */ 5937 for (;;) 5938 { 5939 unsigned iCfg; 5940 for (iCfg = 0; iCfg < cConfigs; iCfg++) 5941 { 5942 unsigned iTest; 5943 BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg; 5944 if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode)) 5945 continue; /* unsupported config */ 5946 5947 /* 5948 * Iterate the tests. 5949 */ 5950 for (iTest = 0; iTest < cTests; iTest++) 5951 { 5952 BS3CPUINSTR3_TEST4_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues; 5953 uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1]; 5954 unsigned const cValues = paTests[iTest].cValues; 5955 bool const fMmxInstr = paTests[iTest].enmType < T_SSE; 5956 bool const fSseInstr = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128; 5957 bool const fAvxInstr = paTests[iTest].enmType >= T_AVX_128; 5958 uint8_t const cbOperand = paTests[iTest].enmType < T_128BITS ? 64/8 5959 : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8; 5960 uint8_t const cbMemOp = cbOperand; 5961 uint8_t const cbAlign = RT_MIN(cbOperand, 16); 5962 PRTUINT256U puMemOp = bs3CpuInstr3BufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg]); 5963 uint8_t const idxEflOut = cbOperand == 32 ? 2 : cbOperand == 16 ? 1 : 0; 5964 uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType] ? X86_XCPT_UD 5965 : fMmxInstr ? paConfigs[iCfg].bXcptMmx 5966 : fSseInstr ? paConfigs[iCfg].bXcptSse 5967 : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx; 5968 uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10; 5969 unsigned iVal; 5970 5971 /* If testing unaligned memory accesses, skip register-only tests. This allows 5972 setting bXcptMmx, bXcptSse and bXcptAvx to reflect the misaligned exceptions. */ 5973 if (paTests[iTest].enmRm == RM_REG && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck)) 5974 continue; 5975 5976 /* #AC is only raised in ring-3.: */ 5977 if (bXcptExpect == X86_XCPT_AC) 5978 { 5979 if (bRing != 3) 5980 bXcptExpect = X86_XCPT_DB; 5981 else if (fAvxInstr) 5982 bXcptExpect = paTests[iTest].bAvxMisalignXcpt; /* they generally don't raise #AC */ 5983 } 5984 5985 Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker); 5986 5987 /* 5988 * Iterate the test values and do the actual testing. 5989 */ 5990 for (iVal = 0; iVal < cValues; iVal++, idTestStep++) 5991 { 5992 unsigned iEflVariation; 5993 uint32_t const fSavedEfl = Ctx.rflags.u32; 5994 for (iEflVariation = 0; iEflVariation < 2; iEflVariation++) 5995 { 5996 uint16_t cErrors; 5997 uint16_t uSavedFtw = 0xff; 5998 RTUINT256U uMemOpExpect; 5999 6000 /* 6001 * Set up the context and some expectations. 6002 */ 6003 /* eflags */ 6004 if (iEflVariation) 6005 Ctx.rflags.u32 = fSavedEfl | X86_EFL_STATUS_BITS; 6006 else 6007 Ctx.rflags.u32 = fSavedEfl & ~X86_EFL_STATUS_BITS; 6008 6009 /* source1 */ 6010 if (paTests[iTest].iRegSrc1 == UINT8_MAX) 6011 { 6012 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); 6013 BS3_ASSERT(paTests[iTest].iRegSrc2 != UINT8_MAX); 6014 Bs3MemCpy(puMemOp, &paValues[iVal].uSrc1, cbMemOp); 6015 uMemOpExpect = paValues[iVal].uSrc1; 6016 } 6017 else if (fMmxInstr) 6018 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc1, paValues[iVal].uSrc1.QWords.qw0, BS3EXTCTXTOPMM_ZERO); 6019 else if (fSseInstr) 6020 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1.DQWords.dqw0); 6021 else 6022 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1, 32); 6023 6024 /* source2 */ 6025 if (paTests[iTest].iRegSrc2 == UINT8_MAX) 6026 { 6027 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); 6028 BS3_ASSERT(paTests[iTest].iRegSrc1 != UINT8_MAX); 6029 Bs3MemCpy(puMemOp, &paValues[iVal].uSrc2, cbMemOp); 6030 uMemOpExpect = paValues[iVal].uSrc2; 6031 } 6032 else if (fMmxInstr) 6033 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc2, paValues[iVal].uSrc2.QWords.qw0, BS3EXTCTXTOPMM_ZERO); 6034 else if (fSseInstr) 6035 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2.DQWords.dqw0); 6036 else 6037 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2, 32); 6038 6039 /* Memory pointer. */ 6040 if (paTests[iTest].enmRm >= RM_MEM) 6041 { 6042 BS3_ASSERT( paTests[iTest].iRegSrc1 == UINT8_MAX 6043 || paTests[iTest].iRegSrc2 == UINT8_MAX); 6044 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp); 6045 } 6046 6047 /* 6048 * Execute. 6049 */ 6050 Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut); 6051 6052 /* 6053 * Check the result: 6054 */ 6055 cErrors = Bs3TestSubErrorCount(); 6056 6057 if (bXcptExpect == X86_XCPT_DB && fMmxInstr) 6058 { 6059 uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx); 6060 Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff); 6061 } 6062 Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep); 6063 6064 if (TrapFrame.bXcpt != bXcptExpect) 6065 Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt); 6066 6067 /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */ 6068 if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC)) 6069 { 6070 if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC) 6071 Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt); 6072 TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC; 6073 } 6074 if (bXcptExpect == X86_XCPT_DB) 6075 Ctx.rflags.u32 = (Ctx.rflags.u32 & ~fEflCheck) | paValues[iVal].afEflOut[idxEflOut]; 6076 Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0, 6077 bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF, 6078 pszMode, idTestStep); 6079 6080 if ( paTests[iTest].enmRm >= RM_MEM 6081 && Bs3MemCmp(puMemOp, &uMemOpExpect, cbMemOp) != 0) 6082 Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &uMemOpExpect, cbMemOp, puMemOp); 6083 6084 if (cErrors != Bs3TestSubErrorCount()) 6085 { 6086 if (paConfigs[iCfg].fAligned) 6087 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u/efl#%u failed (bXcptExpect=%#x)", 6088 bRing, iCfg, iTest, iVal, iEflVariation, bXcptExpect); 6089 else 6090 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u/efl#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)", 6091 bRing, iCfg, iTest, iVal, iEflVariation, bXcptExpect, 6092 puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0); 6093 Bs3TestPrintf("\n"); 6094 } 6095 6096 if (uSavedFtw != 0xff) 6097 Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw); 6098 } 6099 Ctx.rflags.u32 = fSavedEfl; 6100 } 6101 } 6102 6103 bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx); 6104 } 6105 6106 /* 6107 * Next ring. 6108 */ 6109 bRing++; 6110 if (bRing > 3 || bMode == BS3_MODE_RM) 6111 break; 6112 Bs3RegCtxConvertToRingX(&Ctx, bRing); 6113 } 6114 6115 /* 6116 * Cleanup. 6117 */ 6118 bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode); 6119 bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut); 6120 return 0; 6121 } 6122 6123 6124 /* 6125 * PTEST 6126 */ 6127 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_ptest_XMM1_XMM2_icebp); 6128 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_ptest_XMM1_FSxBX_icebp); 6129 extern FNBS3FAR bs3CpuInstr3_ptest_XMM9_XMM8_icebp_c64; 6130 extern FNBS3FAR bs3CpuInstr3_ptest_XMM9_FSxBX_icebp_c64; 6131 6132 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vptest_XMM1_XMM2_icebp); 6133 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vptest_XMM1_FSxBX_icebp); 6134 extern FNBS3FAR bs3CpuInstr3_vptest_XMM9_XMM8_icebp_c64; 6135 extern FNBS3FAR bs3CpuInstr3_vptest_XMM9_FSxBX_icebp_c64; 6136 6137 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vptest_YMM1_YMM2_icebp); 6138 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vptest_YMM1_FSxBX_icebp); 6139 extern FNBS3FAR bs3CpuInstr3_vptest_YMM9_YMM8_icebp_c64; 6140 extern FNBS3FAR bs3CpuInstr3_vptest_YMM9_FSxBX_icebp_c64; 6141 6142 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_ptest(uint8_t bMode) 6143 { 6144 static BS3CPUINSTR3_TEST4_VALUES_T const s_aValues[] = 6145 { 6146 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 6147 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 6148 /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_CF } }, 6149 { /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 6150 /*src1*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 6151 /* => */ { 0, X86_EFL_CF, X86_EFL_CF } }, 6152 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 6153 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), 6154 /* => */ { 0, 0, 0 } }, 6155 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 6156 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), 6157 /* => */ { 0, 0, 0 } }, 6158 { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), 6159 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), 6160 /* => */ { 0, 0, 0 } }, 6161 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 6162 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 6163 /* => */ { 0, 0, 0 } }, 6164 }; 6165 6166 static BS3CPUINSTR3_TEST4_T const s_aTests16[] = 6167 { 6168 { bs3CpuInstr3_ptest_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 6169 { bs3CpuInstr3_ptest_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 6170 { bs3CpuInstr3_vptest_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 6171 { bs3CpuInstr3_vptest_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 6172 { bs3CpuInstr3_vptest_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 6173 { bs3CpuInstr3_vptest_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 6174 }; 6175 static BS3CPUINSTR3_TEST4_T const s_aTests32[] = 6176 { 6177 { bs3CpuInstr3_ptest_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 6178 { bs3CpuInstr3_ptest_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 6179 { bs3CpuInstr3_vptest_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 6180 { bs3CpuInstr3_vptest_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 6181 { bs3CpuInstr3_vptest_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 6182 { bs3CpuInstr3_vptest_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 6183 }; 6184 static BS3CPUINSTR3_TEST4_T const s_aTests64[] = 6185 { 6186 { bs3CpuInstr3_ptest_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 6187 { bs3CpuInstr3_ptest_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 6188 { bs3CpuInstr3_ptest_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValues), s_aValues }, 6189 { bs3CpuInstr3_ptest_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, 6190 { bs3CpuInstr3_vptest_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 6191 { bs3CpuInstr3_vptest_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 6192 { bs3CpuInstr3_vptest_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValues), s_aValues }, 6193 { bs3CpuInstr3_vptest_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, 6194 { bs3CpuInstr3_vptest_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 6195 { bs3CpuInstr3_vptest_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 6196 { bs3CpuInstr3_vptest_YMM9_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValues), s_aValues }, 6197 { bs3CpuInstr3_vptest_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, 6198 }; 6199 static BS3CPUINSTR3_TEST4_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST4_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 6200 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); 6201 return bs3CpuInstr3_WorkerTestType4(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 6202 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), X86_EFL_STATUS_BITS); 5865 6203 } 5866 6204 … … 5943 6281 { "[v]movdqa", bs3CpuInstr3_v_movdqa, 0 }, 5944 6282 #endif 6283 { "[v]ptest", bs3CpuInstr3_v_ptest, 0 }, 5945 6284 }; 5946 6285 Bs3TestInit("bs3-cpu-instr-3");
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