Index: trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac
===================================================================
--- trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac	(revision 95553)
+++ trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac	(revision 95577)
@@ -1368,4 +1368,22 @@
  %endif
 
+;
+; [V]PTEST
+;
+EMIT_INSTR_PLUS_ICEBP ptest,  XMM1, XMM2
+EMIT_INSTR_PLUS_ICEBP ptest,  XMM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP vptest, XMM1, XMM2
+EMIT_INSTR_PLUS_ICEBP vptest, XMM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP vptest, YMM1, YMM2
+EMIT_INSTR_PLUS_ICEBP vptest, YMM1, FSxBX
+ %if TMPL_BITS == 64
+EMIT_INSTR_PLUS_ICEBP ptest,  XMM9, XMM8
+EMIT_INSTR_PLUS_ICEBP ptest,  XMM9, FSxBX
+EMIT_INSTR_PLUS_ICEBP vptest, XMM9, XMM8
+EMIT_INSTR_PLUS_ICEBP vptest, XMM9, FSxBX
+EMIT_INSTR_PLUS_ICEBP vptest, YMM9, YMM8
+EMIT_INSTR_PLUS_ICEBP vptest, YMM9, FSxBX
+ %endif
+
 
 %endif ; BS3_INSTANTIATING_CMN
Index: trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32
===================================================================
--- trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32	(revision 95553)
+++ trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32	(revision 95577)
@@ -4382,5 +4382,5 @@
 
 /*
- * Test type #3.
+ * Test type #3 - two MM/XMM/YMM operands, no flags.
  */
 
@@ -4589,8 +4589,8 @@
                     if (cErrors != Bs3TestSubErrorCount())
                     {
-                        /*if (paConfigs[iCfg].fAligned)
+                        if (paConfigs[iCfg].fAligned)
                             Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x)",
                                            bRing, iCfg, iTest, iVal, bXcptExpect);
-                        else*/
+                        else
                             Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)",
                                            bRing, iCfg, iTest, iVal, bXcptExpect, puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0);
@@ -5863,4 +5863,342 @@
     return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig1, RT_ELEMENTS(g_aXcptConfig1), 255 /*cbMaxAlign*/);
+}
+
+
+
+/*
+ * Test type #4 - two source MM/XMM/YMM operands, outputs only eflags.
+ *
+ * Probably only used by the PTEST instruction.
+ */
+
+typedef struct BS3CPUINSTR3_TEST4_VALUES_T
+{
+    RTUINT256U      uSrc2;
+    RTUINT256U      uSrc1;
+    uint16_t        afEflOut[3];    /* [0]=MM result, [1]=XMM result, [2]=YMM result */
+} BS3CPUINSTR3_TEST4_VALUES_T;
+
+typedef struct BS3CPUINSTR3_TEST4_T
+{
+    FPFNBS3FAR      pfnWorker;
+    uint8_t         bAvxMisalignXcpt;
+    uint8_t         enmRm;
+    uint8_t         enmType;
+    uint8_t         iRegSrc1;
+    uint8_t         iRegSrc2;
+    uint8_t         cValues;
+    BS3CPUINSTR3_TEST4_VALUES_T const BS3_FAR *paValues;
+} BS3CPUINSTR3_TEST4_T;
+
+typedef struct BS3CPUINSTR3_TEST4_MODE_T
+{
+    BS3CPUINSTR3_TEST4_T const BS3_FAR *paTests;
+    unsigned                            cTests;
+} BS3CPUINSTR3_TEST4_MODE_T;
+
+/** Initializer for a BS3CPUINSTR3_TEST4_MODE_T array (three entries). */
+#define BS3CPUINSTR3_TEST4_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \
+    { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } }
+
+
+/**
+ * Test type #4 worker.
+ */
+static uint8_t bs3CpuInstr3_WorkerTestType4(uint8_t bMode, BS3CPUINSTR3_TEST4_T const BS3_FAR *paTests, unsigned cTests,
+                                            PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs, uint32_t fEflCheck)
+{
+    BS3REGCTX                   Ctx;
+    BS3TRAPFRAME                TrapFrame;
+    const char BS3_FAR * const  pszMode = Bs3GetModeName(bMode);
+    uint8_t BS3_FAR            *pbBuf   = g_pbBuf;
+    uint32_t                    cbBuf   = g_cbBuf;
+    uint8_t                     bRing   = BS3_MODE_IS_V86(bMode) ? 3 : 0;
+    PBS3EXTCTX                  pExtCtxOut;
+    PBS3EXTCTX                  pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut);
+    if (!pExtCtx)
+        return 0;
+
+    /* Ensure the structures are allocated before we sample the stack pointer. */
+    Bs3MemSet(&Ctx, 0, sizeof(Ctx));
+    Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame));
+
+    /*
+     * Create test context.
+     */
+    Bs3RegCtxSaveForMode(&Ctx, bMode, 1024);
+    bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx);
+    pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode);
+
+    /*
+     * Run the tests in all rings since alignment issues may behave
+     * differently in ring-3 compared to ring-0.
+     */
+    for (;;)
+    {
+        unsigned iCfg;
+        for (iCfg = 0; iCfg < cConfigs; iCfg++)
+        {
+            unsigned                    iTest;
+            BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg;
+            if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode))
+                continue; /* unsupported config */
+
+            /*
+             * Iterate the tests.
+             */
+            for (iTest = 0; iTest < cTests; iTest++)
+            {
+                BS3CPUINSTR3_TEST4_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues;
+                uint8_t const   cbInstr     = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1];
+                unsigned const  cValues     = paTests[iTest].cValues;
+                bool const      fMmxInstr   = paTests[iTest].enmType < T_SSE;
+                bool const      fSseInstr   = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128;
+                bool const      fAvxInstr   = paTests[iTest].enmType >= T_AVX_128;
+                uint8_t const   cbOperand   = paTests[iTest].enmType < T_128BITS ? 64/8
+                                            : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8;
+                uint8_t const   cbMemOp     = cbOperand;
+                uint8_t const   cbAlign     = RT_MIN(cbOperand, 16);
+                PRTUINT256U     puMemOp     = bs3CpuInstr3BufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg]);
+                uint8_t const   idxEflOut   = cbOperand == 32 ? 2 : cbOperand == 16 ? 1 : 0;
+                uint8_t         bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType] ? X86_XCPT_UD
+                                            : fMmxInstr ? paConfigs[iCfg].bXcptMmx
+                                            : fSseInstr ? paConfigs[iCfg].bXcptSse
+                                            : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx;
+                uint16_t        idTestStep  = bRing * 10000 + iCfg * 100 + iTest * 10;
+                unsigned        iVal;
+
+                /* If testing unaligned memory accesses, skip register-only tests.  This allows
+                   setting bXcptMmx, bXcptSse and bXcptAvx to reflect the misaligned exceptions.  */
+                if (paTests[iTest].enmRm == RM_REG && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck))
+                    continue;
+
+                /* #AC is only raised in ring-3.: */
+                if (bXcptExpect == X86_XCPT_AC)
+                {
+                    if (bRing != 3)
+                        bXcptExpect = X86_XCPT_DB;
+                    else if (fAvxInstr)
+                        bXcptExpect = paTests[iTest].bAvxMisalignXcpt; /* they generally don't raise #AC */
+                }
+
+                Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker);
+
+                /*
+                 * Iterate the test values and do the actual testing.
+                 */
+                for (iVal = 0; iVal < cValues; iVal++, idTestStep++)
+                {
+                    unsigned       iEflVariation;
+                    uint32_t const fSavedEfl = Ctx.rflags.u32;
+                    for (iEflVariation = 0; iEflVariation < 2; iEflVariation++)
+                    {
+                        uint16_t   cErrors;
+                        uint16_t   uSavedFtw = 0xff;
+                        RTUINT256U uMemOpExpect;
+
+                        /*
+                         * Set up the context and some expectations.
+                         */
+                        /* eflags */
+                        if (iEflVariation)
+                            Ctx.rflags.u32 = fSavedEfl | X86_EFL_STATUS_BITS;
+                        else
+                            Ctx.rflags.u32 = fSavedEfl & ~X86_EFL_STATUS_BITS;
+
+                        /* source1 */
+                        if (paTests[iTest].iRegSrc1 == UINT8_MAX)
+                        {
+                            BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM);
+                            BS3_ASSERT(paTests[iTest].iRegSrc2 != UINT8_MAX);
+                            Bs3MemCpy(puMemOp, &paValues[iVal].uSrc1, cbMemOp);
+                            uMemOpExpect = paValues[iVal].uSrc1;
+                        }
+                        else if (fMmxInstr)
+                            Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc1, paValues[iVal].uSrc1.QWords.qw0, BS3EXTCTXTOPMM_ZERO);
+                        else if (fSseInstr)
+                            Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1.DQWords.dqw0);
+                        else
+                            Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1, 32);
+
+                        /* source2 */
+                        if (paTests[iTest].iRegSrc2 == UINT8_MAX)
+                        {
+                            BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM);
+                            BS3_ASSERT(paTests[iTest].iRegSrc1 != UINT8_MAX);
+                            Bs3MemCpy(puMemOp, &paValues[iVal].uSrc2, cbMemOp);
+                            uMemOpExpect = paValues[iVal].uSrc2;
+                        }
+                        else if (fMmxInstr)
+                            Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc2, paValues[iVal].uSrc2.QWords.qw0, BS3EXTCTXTOPMM_ZERO);
+                        else if (fSseInstr)
+                            Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2.DQWords.dqw0);
+                        else
+                            Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2, 32);
+
+                        /* Memory pointer. */
+                        if (paTests[iTest].enmRm >= RM_MEM)
+                        {
+                            BS3_ASSERT(   paTests[iTest].iRegSrc1 == UINT8_MAX
+                                       || paTests[iTest].iRegSrc2 == UINT8_MAX);
+                            Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp);
+                        }
+
+                        /*
+                         * Execute.
+                         */
+                        Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut);
+
+                        /*
+                         * Check the result:
+                         */
+                        cErrors = Bs3TestSubErrorCount();
+
+                        if (bXcptExpect == X86_XCPT_DB && fMmxInstr)
+                        {
+                            uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx);
+                            Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff);
+                        }
+                        Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep);
+
+                        if (TrapFrame.bXcpt != bXcptExpect)
+                            Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt);
+
+                        /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */
+                        if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC))
+                        {
+                            if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC)
+                                Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt);
+                            TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC;
+                        }
+                        if (bXcptExpect == X86_XCPT_DB)
+                            Ctx.rflags.u32 = (Ctx.rflags.u32 & ~fEflCheck) | paValues[iVal].afEflOut[idxEflOut];
+                        Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0,
+                                             bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF,
+                                             pszMode, idTestStep);
+
+                        if (   paTests[iTest].enmRm >= RM_MEM
+                            && Bs3MemCmp(puMemOp, &uMemOpExpect, cbMemOp) != 0)
+                            Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &uMemOpExpect, cbMemOp, puMemOp);
+
+                        if (cErrors != Bs3TestSubErrorCount())
+                        {
+                            if (paConfigs[iCfg].fAligned)
+                                Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u/efl#%u failed (bXcptExpect=%#x)",
+                                               bRing, iCfg, iTest, iVal, iEflVariation, bXcptExpect);
+                            else
+                                Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u/efl#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)",
+                                               bRing, iCfg, iTest, iVal, iEflVariation, bXcptExpect,
+                                               puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0);
+                            Bs3TestPrintf("\n");
+                        }
+
+                        if (uSavedFtw != 0xff)
+                            Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw);
+                    }
+                    Ctx.rflags.u32 = fSavedEfl;
+                }
+            }
+
+            bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx);
+        }
+
+        /*
+         * Next ring.
+         */
+        bRing++;
+        if (bRing > 3 || bMode == BS3_MODE_RM)
+            break;
+        Bs3RegCtxConvertToRingX(&Ctx, bRing);
+    }
+
+    /*
+     * Cleanup.
+     */
+    bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode);
+    bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut);
+    return 0;
+}
+
+
+/*
+ * PTEST
+ */
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_ptest_XMM1_XMM2_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_ptest_XMM1_FSxBX_icebp);
+extern FNBS3FAR             bs3CpuInstr3_ptest_XMM9_XMM8_icebp_c64;
+extern FNBS3FAR             bs3CpuInstr3_ptest_XMM9_FSxBX_icebp_c64;
+
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vptest_XMM1_XMM2_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vptest_XMM1_FSxBX_icebp);
+extern FNBS3FAR             bs3CpuInstr3_vptest_XMM9_XMM8_icebp_c64;
+extern FNBS3FAR             bs3CpuInstr3_vptest_XMM9_FSxBX_icebp_c64;
+
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vptest_YMM1_YMM2_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vptest_YMM1_FSxBX_icebp);
+extern FNBS3FAR             bs3CpuInstr3_vptest_YMM9_YMM8_icebp_c64;
+extern FNBS3FAR             bs3CpuInstr3_vptest_YMM9_FSxBX_icebp_c64;
+
+BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_ptest(uint8_t bMode)
+{
+    static BS3CPUINSTR3_TEST4_VALUES_T const s_aValues[] =
+    {
+        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
+            /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
+            /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_CF } },
+        {   /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
+            /*src1*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
+            /* => */ { 0, X86_EFL_CF, X86_EFL_CF } },
+        {   /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
+            /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
+            /* => */ { 0, 0, 0 } },
+        {   /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
+            /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
+            /* => */ { 0, 0, 0 } },
+        {   /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
+            /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
+            /* => */ { 0, 0, 0 } },
+        {   /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
+            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
+            /* => */ { 0, 0, 0 } },
+    };
+
+    static BS3CPUINSTR3_TEST4_T const s_aTests16[] =
+    {
+        {  bs3CpuInstr3_ptest_XMM1_XMM2_icebp_c16,   255,         RM_REG, T_SSE4_1,   1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_ptest_XMM1_FSxBX_icebp_c16,  255,         RM_MEM, T_SSE4_1,   1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vptest_XMM1_XMM2_icebp_c16,  255,         RM_REG, T_AVX_128,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vptest_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vptest_YMM1_YMM2_icebp_c16,  255,         RM_REG, T_AVX_256,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vptest_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+    };
+    static BS3CPUINSTR3_TEST4_T const s_aTests32[] =
+    {
+        {  bs3CpuInstr3_ptest_XMM1_XMM2_icebp_c32,   255,         RM_REG, T_SSE4_1,   1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_ptest_XMM1_FSxBX_icebp_c32,  255,         RM_MEM, T_SSE4_1,   1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vptest_XMM1_XMM2_icebp_c32,  255,         RM_REG, T_AVX_128,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vptest_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vptest_YMM1_YMM2_icebp_c32,  255,         RM_REG, T_AVX_256,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vptest_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+    };
+    static BS3CPUINSTR3_TEST4_T const s_aTests64[] =
+    {
+        {  bs3CpuInstr3_ptest_XMM1_XMM2_icebp_c64,   255,         RM_REG, T_SSE4_1,   1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_ptest_XMM1_FSxBX_icebp_c64,  255,         RM_MEM, T_SSE4_1,   1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_ptest_XMM9_XMM8_icebp_c64,   255,         RM_REG, T_SSE4_1,   9,   8, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_ptest_XMM9_FSxBX_icebp_c64,  255,         RM_MEM, T_SSE4_1,   9, 255, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vptest_XMM1_XMM2_icebp_c64,  255,         RM_REG, T_AVX_128,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vptest_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vptest_XMM9_XMM8_icebp_c64,  255,         RM_REG, T_AVX_128,  9,   8, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vptest_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,  9, 255, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vptest_YMM1_YMM2_icebp_c64,  255,         RM_REG, T_AVX_256,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vptest_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vptest_YMM9_YMM8_icebp_c64,  255,         RM_REG, T_AVX_256,  9,   8, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vptest_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256,  9, 255, RT_ELEMENTS(s_aValues), s_aValues },
+    };
+    static BS3CPUINSTR3_TEST4_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST4_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
+    unsigned const                         iTest       = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
+    return bs3CpuInstr3_WorkerTestType4(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+                                        g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), X86_EFL_STATUS_BITS);
 }
 
@@ -5943,4 +6281,5 @@
         { "[v]movdqa",                                      bs3CpuInstr3_v_movdqa, 0 },
 #endif
+        { "[v]ptest",                                       bs3CpuInstr3_v_ptest, 0 },
     };
     Bs3TestInit("bs3-cpu-instr-3");
