Changeset 95988 in vbox for trunk/src/VBox/ValidationKit

Timestamp:

Aug 2, 2022 2:48:12 PM (3 years ago)

Author:

vboxsync

Message:

ValKit/bs3-cpu-instr-3: Simple [v]pmaxub test. ​bugref:9898 [fix for the MMX variants]

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32 (modified) (5 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32

@@ -3374 +3374 @@
 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmaxub(uint8_t bMode)
 {
-#define NO_PMAXUB_64 /** @todo Throws errors on Intel hardware in HM mode. */
-#ifndef NO_PMAXUB_64
     static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] =
     {
@@ -3386 +3384 @@
         {   /*src2*/ RTUINT256_INIT_C( 4,  5,  7, 0x5555666677778888),
             /*src1*/ RTUINT256_INIT_C( 4,  6,  7, 0xddddeeeeffff0000),
-            /* => */ RTUINT256_INIT_C( 4,  6,  7, 0xddddeeeeffff0000) },
+            /* => */ RTUINT256_INIT_C( 4,  6,  7, 0xddddeeeeffff8888) },
         {   /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb),
             /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd),
-            /* => */ RTUINT256_INIT_C(12, 13, 14, 0x9cd3cda0938499fd) },
+            /* => */ RTUINT256_INIT_C(12, 13, 14, 0x9cd3e0a0938499fd) },
         {   /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xff820064fffe0042),
             /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x0022fe00ff80ff81),
             /* => */ RTUINT256_INIT_C(12, 13, 14, 0xff82fe64fffeff81) },
     };
-#endif
     static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] =
     {
@@ -3410 +3407 @@
     static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
     {
-#ifndef NO_PMAXUB_64
-        {  bs3CpuInstr3_pmaxub_MM1_MM2_icebp_c16,          255,         RM_REG, T_SSE,       1, 1,   2, RT_ELEMENTS(s_aValues64), s_aValues64 },
-        {  bs3CpuInstr3_pmaxub_MM1_FSxBX_icebp_c16,        255,         RM_MEM, T_SSE,       1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
-#endif
+        {  bs3CpuInstr3_pmaxub_MM1_MM2_icebp_c16,          255,         RM_REG, T_MMX_SSE,   1, 1,   2, RT_ELEMENTS(s_aValues64), s_aValues64 },
+        {  bs3CpuInstr3_pmaxub_MM1_FSxBX_icebp_c16,        255,         RM_MEM, T_MMX_SSE,   1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
         {  bs3CpuInstr3_pmaxub_XMM1_XMM2_icebp_c16,        255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
         {  bs3CpuInstr3_pmaxub_XMM1_FSxBX_icebp_c16,       255,         RM_MEM, T_SSE2,      1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
@@ -3423 +3418 @@
     static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
     {
-#ifndef NO_PMAXUB_64
-        {  bs3CpuInstr3_pmaxub_MM1_MM2_icebp_c32,          255,         RM_REG, T_SSE,       1, 1,   2, RT_ELEMENTS(s_aValues64), s_aValues64 },
-        {  bs3CpuInstr3_pmaxub_MM1_FSxBX_icebp_c32,        255,         RM_MEM, T_SSE,       1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
-#endif
+        {  bs3CpuInstr3_pmaxub_MM1_MM2_icebp_c32,          255,         RM_REG, T_MMX_SSE,   1, 1,   2, RT_ELEMENTS(s_aValues64), s_aValues64 },
+        {  bs3CpuInstr3_pmaxub_MM1_FSxBX_icebp_c32,        255,         RM_MEM, T_MMX_SSE,   1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
         {  bs3CpuInstr3_pmaxub_XMM1_XMM2_icebp_c32,        255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
         {  bs3CpuInstr3_pmaxub_XMM1_FSxBX_icebp_c32,       255,         RM_MEM, T_SSE2,      1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
@@ -3436 +3429 @@
     static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
     {
-#ifndef NO_PMAXUB_64
-        {  bs3CpuInstr3_pmaxub_MM1_MM2_icebp_c64,          255,         RM_REG, T_SSE,       1, 1,   2, RT_ELEMENTS(s_aValues64), s_aValues64 },
-        {  bs3CpuInstr3_pmaxub_MM1_FSxBX_icebp_c64,        255,         RM_MEM, T_SSE,       1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
-#endif
+        {  bs3CpuInstr3_pmaxub_MM1_MM2_icebp_c64,          255,         RM_REG, T_MMX_SSE,   1, 1,   2, RT_ELEMENTS(s_aValues64), s_aValues64 },
+        {  bs3CpuInstr3_pmaxub_MM1_FSxBX_icebp_c64,        255,         RM_MEM, T_MMX_SSE,   1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 },
         {  bs3CpuInstr3_pmaxub_XMM1_XMM2_icebp_c64,        255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },
         {  bs3CpuInstr3_pmaxub_XMM1_FSxBX_icebp_c64,       255,         RM_MEM, T_SSE2,      1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers },