VirtualBox

Changeset 96021 in vbox


Ignore:
Timestamp:
Aug 4, 2022 8:54:56 AM (3 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
152816
Message:

ValidationKit/bs3-cpu-instr-3: Add [v]pmull{w,d} instructions testcase, bugref:9898

Location:
trunk/src/VBox/ValidationKit/bootsectors
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac

    r96011 r96021  
    529529
    530530EMIT_TYPE2_ONE_INSTR pmovmskb, vpmovmskb, 1, 0d7h
     531
     532;
     533; [V]PMULLW
     534;
     535EMIT_INSTR_PLUS_ICEBP   pmullw, MM1, MM2
     536EMIT_INSTR_PLUS_ICEBP   pmullw, MM1, FSxBX
     537
     538EMIT_INSTR_PLUS_ICEBP   pmullw, XMM1, XMM2
     539EMIT_INSTR_PLUS_ICEBP   pmullw, XMM1, FSxBX
     540 %if TMPL_BITS == 64
     541EMIT_INSTR_PLUS_ICEBP   pmullw, XMM8, XMM9
     542EMIT_INSTR_PLUS_ICEBP   pmullw, XMM8, FSxBX
     543 %endif
     544
     545EMIT_INSTR_PLUS_ICEBP   vpmullw, XMM1, XMM1, XMM2
     546EMIT_INSTR_PLUS_ICEBP   vpmullw, XMM1, XMM1, FSxBX
     547 %if TMPL_BITS == 64
     548EMIT_INSTR_PLUS_ICEBP   vpmullw, XMM8, XMM9, XMM10
     549EMIT_INSTR_PLUS_ICEBP   vpmullw, XMM8, XMM9, FSxBX
     550 %endif
     551
     552EMIT_INSTR_PLUS_ICEBP   vpmullw, YMM1, YMM1, YMM2
     553EMIT_INSTR_PLUS_ICEBP   vpmullw, YMM1, YMM1, FSxBX
     554 %if TMPL_BITS == 64
     555EMIT_INSTR_PLUS_ICEBP   vpmullw, YMM8, YMM9, YMM10
     556EMIT_INSTR_PLUS_ICEBP   vpmullw, YMM8, YMM9, FSxBX
     557 %endif
     558
     559;
     560; [V]PMULLD
     561;
     562EMIT_INSTR_PLUS_ICEBP   pmulld, XMM1, XMM2
     563EMIT_INSTR_PLUS_ICEBP   pmulld, XMM1, FSxBX
     564 %if TMPL_BITS == 64
     565EMIT_INSTR_PLUS_ICEBP   pmulld, XMM8, XMM9
     566EMIT_INSTR_PLUS_ICEBP   pmulld, XMM8, FSxBX
     567 %endif
     568
     569EMIT_INSTR_PLUS_ICEBP   vpmulld, XMM2, XMM1, XMM0
     570EMIT_INSTR_PLUS_ICEBP   vpmulld, XMM2, XMM1, FSxBX
     571 %if TMPL_BITS == 64
     572EMIT_INSTR_PLUS_ICEBP   vpmulld, XMM8, XMM9, XMM10
     573EMIT_INSTR_PLUS_ICEBP   vpmulld, XMM8, XMM9, FSxBX
     574 %endif
     575
     576EMIT_INSTR_PLUS_ICEBP   vpmulld, YMM2, YMM1, YMM0
     577EMIT_INSTR_PLUS_ICEBP   vpmulld, YMM2, YMM1, FSxBX
     578 %if TMPL_BITS == 64
     579EMIT_INSTR_PLUS_ICEBP   vpmulld, YMM10, YMM8, YMM15
     580EMIT_INSTR_PLUS_ICEBP   vpmulld, YMM10, YMM8, FSxBX
     581 %endif
    531582
    532583;

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32

    r96011 r96021  
    21272127        {  bs3CpuInstr3_vpsubq_YMM2_YMM1_FSxBX_icebp_c64,    X86_XCPT_DB, RM_MEM, T_AVX_256,  2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
    21282128        {  bs3CpuInstr3_vpsubq_YMM10_YMM8_YMM15_icebp_c64,   255,         RM_REG, T_AVX_256, 10, 8,  15, RT_ELEMENTS(s_aValuesQ), s_aValuesQ },
     2129    };
     2130    static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     2131    unsigned const                         iTest       = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
     2132    return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
     2133                                        g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
     2134}
     2135
     2136
     2137/*
     2138 * PMULLW, VPMULLW, PMULLD, VPMULLD.
     2139 */
     2140BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmullw_MM1_MM2_icebp);
     2141BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmullw_MM1_FSxBX_icebp);
     2142BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmullw_XMM1_XMM2_icebp);
     2143BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmullw_XMM1_FSxBX_icebp);
     2144BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmullw_XMM1_XMM1_XMM2_icebp);
     2145BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmullw_XMM1_XMM1_FSxBX_icebp);
     2146BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmullw_YMM1_YMM1_YMM2_icebp);
     2147BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmullw_YMM1_YMM1_FSxBX_icebp);
     2148
     2149BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulld_XMM1_XMM2_icebp);
     2150BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulld_XMM1_FSxBX_icebp);
     2151BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulld_XMM2_XMM1_XMM0_icebp);
     2152BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulld_XMM2_XMM1_FSxBX_icebp);
     2153BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulld_YMM2_YMM1_YMM0_icebp);
     2154BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulld_YMM2_YMM1_FSxBX_icebp);
     2155extern FNBS3FAR             bs3CpuInstr3_vpmulld_YMM10_YMM8_YMM15_icebp_c64;
     2156extern FNBS3FAR             bs3CpuInstr3_vpmulld_YMM10_YMM8_FSxBX_icebp_c64;
     2157
     2158BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmullw_pmulld(uint8_t bMode)
     2159{
     2160    static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] =
     2161    {
     2162        {           RTUINT256_INIT_C(0, 0, 0, 0),
     2163            /* * */ RTUINT256_INIT_C(0, 0, 0, 0),
     2164            /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
     2165        {           RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
     2166            /* * */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
     2167            /* = */ RTUINT256_INIT_C(0x0b6106d488890000, 0x5c293e94a7419630, 0x5c293e94a7419630, 0x0b6106d488890000) },
     2168        {           RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
     2169            /* * */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     2170            /* = */ RTUINT256_INIT_C(0x8ec59e38d5149124, 0xf3b0dc605ba6fed2, 0x8800d8b8476c9066, 0xf3d45ee00ba4b9cf) },
     2171    };
     2172
     2173    static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] =
     2174    {
     2175        {           RTUINT256_INIT_C(0, 0, 0, 0),
     2176            /* * */ RTUINT256_INIT_C(0, 0, 0, 0),
     2177            /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
     2178        {           RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
     2179            /* * */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
     2180            /* = */ RTUINT256_INIT_C(0x2ea606d477780000, 0x6e5d3e9430ec9630, 0x6e5d3e9430ec9630, 0x2ea606d477780000) },
     2181        {           RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
     2182            /* * */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     2183            /* = */ RTUINT256_INIT_C(0x97439e3846719124, 0x8216dc606340fed2, 0x7c2bd8b8f1c09066, 0x31915ee054fbb9cf) },
     2184    };
     2185
     2186    static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
     2187    {
     2188        {  bs3CpuInstr3_pmullw_MM1_MM2_icebp_c16,            255,         RM_REG, T_MMX,      1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2189        {  bs3CpuInstr3_pmullw_MM1_FSxBX_icebp_c16,          255,         RM_MEM, T_MMX,      1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2190        {  bs3CpuInstr3_pmullw_XMM1_XMM2_icebp_c16,          255,         RM_REG, T_SSE2,     1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2191        {  bs3CpuInstr3_pmullw_XMM1_FSxBX_icebp_c16,         255,         RM_MEM, T_SSE2,     1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2192        {  bs3CpuInstr3_vpmullw_XMM1_XMM1_XMM2_icebp_c16,    255,         RM_REG, T_AVX_128,  1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2193        {  bs3CpuInstr3_vpmullw_XMM1_XMM1_FSxBX_icebp_c16,   X86_XCPT_DB, RM_MEM, T_AVX_128,  1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2194        {  bs3CpuInstr3_vpmullw_YMM1_YMM1_YMM2_icebp_c16,    255,         RM_REG, T_AVX_256,  1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2195        {  bs3CpuInstr3_vpmullw_YMM1_YMM1_FSxBX_icebp_c16,   X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2196
     2197        {  bs3CpuInstr3_pmulld_XMM1_XMM2_icebp_c16,          255,         RM_REG, T_SSE4_1,   1, 1,   2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
     2198        {  bs3CpuInstr3_pmulld_XMM1_FSxBX_icebp_c16,         255,         RM_MEM, T_SSE4_1,   1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
     2199        {  bs3CpuInstr3_vpmulld_XMM2_XMM1_XMM0_icebp_c16,    255,         RM_REG, T_AVX_128,  2, 1,   0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
     2200        {  bs3CpuInstr3_vpmulld_XMM2_XMM1_FSxBX_icebp_c16,   X86_XCPT_DB, RM_MEM, T_AVX_128,  2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
     2201        {  bs3CpuInstr3_vpmulld_YMM2_YMM1_YMM0_icebp_c16,    255,         RM_REG, T_AVX_256,  2, 1,   0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
     2202        {  bs3CpuInstr3_vpmulld_YMM2_YMM1_FSxBX_icebp_c16,   X86_XCPT_DB, RM_MEM, T_AVX_256,  2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
     2203    };
     2204    static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
     2205    {
     2206        {  bs3CpuInstr3_pmullw_MM1_MM2_icebp_c32,            255,         RM_REG, T_MMX,      1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2207        {  bs3CpuInstr3_pmullw_MM1_FSxBX_icebp_c32,          255,         RM_MEM, T_MMX,      1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2208        {  bs3CpuInstr3_pmullw_XMM1_XMM2_icebp_c32,          255,         RM_REG, T_SSE2,     1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2209        {  bs3CpuInstr3_pmullw_XMM1_FSxBX_icebp_c32,         255,         RM_MEM, T_SSE2,     1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2210        {  bs3CpuInstr3_vpmullw_XMM1_XMM1_XMM2_icebp_c32,    255,         RM_REG, T_AVX_128,  1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2211        {  bs3CpuInstr3_vpmullw_XMM1_XMM1_FSxBX_icebp_c32,   X86_XCPT_DB, RM_MEM, T_AVX_128,  1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2212        {  bs3CpuInstr3_vpmullw_YMM1_YMM1_YMM2_icebp_c32,    255,         RM_REG, T_AVX_256,  1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2213        {  bs3CpuInstr3_vpmullw_YMM1_YMM1_FSxBX_icebp_c32,   X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2214
     2215        {  bs3CpuInstr3_pmulld_XMM1_XMM2_icebp_c32,          255,         RM_REG, T_SSE4_1,   1, 1,   2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
     2216        {  bs3CpuInstr3_pmulld_XMM1_FSxBX_icebp_c32,         255,         RM_MEM, T_SSE4_1,   1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
     2217        {  bs3CpuInstr3_vpmulld_XMM2_XMM1_XMM0_icebp_c32,    255,         RM_REG, T_AVX_128,  2, 1,   0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
     2218        {  bs3CpuInstr3_vpmulld_XMM2_XMM1_FSxBX_icebp_c32,   X86_XCPT_DB, RM_MEM, T_AVX_128,  2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
     2219        {  bs3CpuInstr3_vpmulld_YMM2_YMM1_YMM0_icebp_c32,    255,         RM_REG, T_AVX_256,  2, 1,   0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
     2220        {  bs3CpuInstr3_vpmulld_YMM2_YMM1_FSxBX_icebp_c32,   X86_XCPT_DB, RM_MEM, T_AVX_256,  2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
     2221    };
     2222    static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
     2223    {
     2224        {  bs3CpuInstr3_pmullw_MM1_MM2_icebp_c64,            255,         RM_REG, T_MMX,      1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2225        {  bs3CpuInstr3_pmullw_MM1_FSxBX_icebp_c64,          255,         RM_MEM, T_MMX,      1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2226        {  bs3CpuInstr3_pmullw_XMM1_XMM2_icebp_c64,          255,         RM_REG, T_SSE2,     1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2227        {  bs3CpuInstr3_pmullw_XMM1_FSxBX_icebp_c64,         255,         RM_MEM, T_SSE2,     1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2228        {  bs3CpuInstr3_vpmullw_XMM1_XMM1_XMM2_icebp_c64,    255,         RM_REG, T_AVX_128,  1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2229        {  bs3CpuInstr3_vpmullw_XMM1_XMM1_FSxBX_icebp_c64,   X86_XCPT_DB, RM_MEM, T_AVX_128,  1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2230        {  bs3CpuInstr3_vpmullw_YMM1_YMM1_YMM2_icebp_c64,    255,         RM_REG, T_AVX_256,  1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2231        {  bs3CpuInstr3_vpmullw_YMM1_YMM1_FSxBX_icebp_c64,   X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2232
     2233        {  bs3CpuInstr3_pmulld_XMM1_XMM2_icebp_c64,          255,         RM_REG, T_SSE4_1,   1, 1,   2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
     2234        {  bs3CpuInstr3_pmulld_XMM1_FSxBX_icebp_c64,         255,         RM_MEM, T_SSE4_1,   1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
     2235        {  bs3CpuInstr3_vpmulld_XMM2_XMM1_XMM0_icebp_c64,    255,         RM_REG, T_AVX_128,  2, 1,   0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
     2236        {  bs3CpuInstr3_vpmulld_XMM2_XMM1_FSxBX_icebp_c64,   X86_XCPT_DB, RM_MEM, T_AVX_128,  2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
     2237        {  bs3CpuInstr3_vpmulld_YMM2_YMM1_YMM0_icebp_c64,    255,         RM_REG, T_AVX_256,  2, 1,   0, RT_ELEMENTS(s_aValuesD), s_aValuesD },
     2238        {  bs3CpuInstr3_vpmulld_YMM2_YMM1_FSxBX_icebp_c64,   X86_XCPT_DB, RM_MEM, T_AVX_256,  2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
     2239        {  bs3CpuInstr3_vpmulld_YMM10_YMM8_YMM15_icebp_c64,  255,         RM_REG, T_AVX_256, 10, 8,  15, RT_ELEMENTS(s_aValuesD), s_aValuesD },
     2240        {  bs3CpuInstr3_vpmulld_YMM10_YMM8_FSxBX_icebp_c64,  X86_XCPT_DB, RM_MEM, T_AVX_256, 10, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
    21292241    };
    21302242    static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
    … …  
    70477159        { "[v]paddb/[v]paddw/[v]paddd/[v]paddq",            bs3CpuInstr3_v_paddb_paddw_paddd_paddq, 0 },
    70487160        { "[v]psubb/[v]psubw/[v]psubd/[v]psubq",            bs3CpuInstr3_v_psubb_psubw_psubd_psubq, 0 },
     7161#endif
     7162#if defined(ALL_TESTS)
     7163        { "[v]pmullw/[v]pmulld",                            bs3CpuInstr3_v_pmullw_pmulld,           0 },
    70497164#endif
    70507165#if defined(ALL_TESTS)
Note: See TracChangeset for help on using the changeset viewer.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette