VirtualBox

Changeset 96023 in vbox


Ignore:
Timestamp:
Aug 4, 2022 9:13:05 AM (2 years ago)
Author:
vboxsync
Message:

ValidationKit/bs3-cpu-instr-3: Add [v]pmulhw instructions testcase, bugref:9898

Location:
trunk/src/VBox/ValidationKit/bootsectors
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac

    r96021 r96023  
    579579EMIT_INSTR_PLUS_ICEBP   vpmulld, YMM10, YMM8, YMM15
    580580EMIT_INSTR_PLUS_ICEBP   vpmulld, YMM10, YMM8, FSxBX
     581 %endif
     582
     583;
     584; [V]PMULHW
     585;
     586EMIT_INSTR_PLUS_ICEBP   pmulhw, MM1, MM2
     587EMIT_INSTR_PLUS_ICEBP   pmulhw, MM1, FSxBX
     588
     589EMIT_INSTR_PLUS_ICEBP   pmulhw, XMM1, XMM2
     590EMIT_INSTR_PLUS_ICEBP   pmulhw, XMM1, FSxBX
     591 %if TMPL_BITS == 64
     592EMIT_INSTR_PLUS_ICEBP   pmulhw, XMM8, XMM9
     593EMIT_INSTR_PLUS_ICEBP   pmulhw, XMM8, FSxBX
     594 %endif
     595
     596EMIT_INSTR_PLUS_ICEBP   vpmulhw, XMM1, XMM1, XMM2
     597EMIT_INSTR_PLUS_ICEBP   vpmulhw, XMM1, XMM1, FSxBX
     598 %if TMPL_BITS == 64
     599EMIT_INSTR_PLUS_ICEBP   vpmulhw, XMM8, XMM9, XMM10
     600EMIT_INSTR_PLUS_ICEBP   vpmulhw, XMM8, XMM9, FSxBX
     601 %endif
     602
     603EMIT_INSTR_PLUS_ICEBP   vpmulhw, YMM1, YMM1, YMM2
     604EMIT_INSTR_PLUS_ICEBP   vpmulhw, YMM1, YMM1, FSxBX
     605 %if TMPL_BITS == 64
     606EMIT_INSTR_PLUS_ICEBP   vpmulhw, YMM8, YMM9, YMM10
     607EMIT_INSTR_PLUS_ICEBP   vpmulhw, YMM8, YMM9, FSxBX
    581608 %endif
    582609

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32

    r96021 r96023  
    22392239        {  bs3CpuInstr3_vpmulld_YMM10_YMM8_YMM15_icebp_c64,  255,         RM_REG, T_AVX_256, 10, 8,  15, RT_ELEMENTS(s_aValuesD), s_aValuesD },
    22402240        {  bs3CpuInstr3_vpmulld_YMM10_YMM8_FSxBX_icebp_c64,  X86_XCPT_DB, RM_MEM, T_AVX_256, 10, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
     2241    };
     2242    static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     2243    unsigned const                         iTest       = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
     2244    return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
     2245                                        g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
     2246}
     2247
     2248
     2249/*
     2250 * PMULHW, VPMULHW.
     2251 */
     2252BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhw_MM1_MM2_icebp);
     2253BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhw_MM1_FSxBX_icebp);
     2254BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhw_XMM1_XMM2_icebp);
     2255BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhw_XMM1_FSxBX_icebp);
     2256BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhw_XMM1_XMM1_XMM2_icebp);
     2257BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhw_XMM1_XMM1_FSxBX_icebp);
     2258BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhw_YMM1_YMM1_YMM2_icebp);
     2259BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhw_YMM1_YMM1_FSxBX_icebp);
     2260
     2261BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmulhw(uint8_t bMode)
     2262{
     2263    static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] =
     2264    {
     2265        {           RTUINT256_INIT_C(0, 0, 0, 0),
     2266            /* * */ RTUINT256_INIT_C(0, 0, 0, 0),
     2267            /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
     2268        {           RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
     2269            /* * */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
     2270            /* = */ RTUINT256_INIT_C(0xf49ff92cffff0000, 0xf92cf49ff258f258, 0xf92cf49ff258f258, 0xf49ff92cffff0000) },
     2271        {           RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
     2272            /* * */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     2273            /* = */ RTUINT256_INIT_C(0x0949021f03fd16e2, 0xfe5df57e19c81583, 0x2390fbc8ea4ad947, 0xe5990635f0e229f2) },
     2274    };
     2275
     2276    static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
     2277    {
     2278        {  bs3CpuInstr3_pmulhw_MM1_MM2_icebp_c16,            255,         RM_REG, T_MMX,      1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2279        {  bs3CpuInstr3_pmulhw_MM1_FSxBX_icebp_c16,          255,         RM_MEM, T_MMX,      1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2280        {  bs3CpuInstr3_pmulhw_XMM1_XMM2_icebp_c16,          255,         RM_REG, T_SSE2,     1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2281        {  bs3CpuInstr3_pmulhw_XMM1_FSxBX_icebp_c16,         255,         RM_MEM, T_SSE2,     1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2282        {  bs3CpuInstr3_vpmulhw_XMM1_XMM1_XMM2_icebp_c16,    255,         RM_REG, T_AVX_128,  1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2283        {  bs3CpuInstr3_vpmulhw_XMM1_XMM1_FSxBX_icebp_c16,   X86_XCPT_DB, RM_MEM, T_AVX_128,  1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2284        {  bs3CpuInstr3_vpmulhw_YMM1_YMM1_YMM2_icebp_c16,    255,         RM_REG, T_AVX_256,  1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2285        {  bs3CpuInstr3_vpmulhw_YMM1_YMM1_FSxBX_icebp_c16,   X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2286    };
     2287    static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
     2288    {
     2289        {  bs3CpuInstr3_pmulhw_MM1_MM2_icebp_c32,            255,         RM_REG, T_MMX,      1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2290        {  bs3CpuInstr3_pmulhw_MM1_FSxBX_icebp_c32,          255,         RM_MEM, T_MMX,      1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2291        {  bs3CpuInstr3_pmulhw_XMM1_XMM2_icebp_c32,          255,         RM_REG, T_SSE2,     1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2292        {  bs3CpuInstr3_pmulhw_XMM1_FSxBX_icebp_c32,         255,         RM_MEM, T_SSE2,     1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2293        {  bs3CpuInstr3_vpmulhw_XMM1_XMM1_XMM2_icebp_c32,    255,         RM_REG, T_AVX_128,  1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2294        {  bs3CpuInstr3_vpmulhw_XMM1_XMM1_FSxBX_icebp_c32,   X86_XCPT_DB, RM_MEM, T_AVX_128,  1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2295        {  bs3CpuInstr3_vpmulhw_YMM1_YMM1_YMM2_icebp_c32,    255,         RM_REG, T_AVX_256,  1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2296        {  bs3CpuInstr3_vpmulhw_YMM1_YMM1_FSxBX_icebp_c32,   X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2297    };
     2298    static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
     2299    {
     2300        {  bs3CpuInstr3_pmulhw_MM1_MM2_icebp_c64,            255,         RM_REG, T_MMX,      1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2301        {  bs3CpuInstr3_pmulhw_MM1_FSxBX_icebp_c64,          255,         RM_MEM, T_MMX,      1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2302        {  bs3CpuInstr3_pmulhw_XMM1_XMM2_icebp_c64,          255,         RM_REG, T_SSE2,     1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2303        {  bs3CpuInstr3_pmulhw_XMM1_FSxBX_icebp_c64,         255,         RM_MEM, T_SSE2,     1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2304        {  bs3CpuInstr3_vpmulhw_XMM1_XMM1_XMM2_icebp_c64,    255,         RM_REG, T_AVX_128,  1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2305        {  bs3CpuInstr3_vpmulhw_XMM1_XMM1_FSxBX_icebp_c64,   X86_XCPT_DB, RM_MEM, T_AVX_128,  1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2306        {  bs3CpuInstr3_vpmulhw_YMM1_YMM1_YMM2_icebp_c64,    255,         RM_REG, T_AVX_256,  1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2307        {  bs3CpuInstr3_vpmulhw_YMM1_YMM1_FSxBX_icebp_c64,   X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
    22412308    };
    22422309    static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
    … …  
    71447211    {
    71457212#ifndef DEBUG_bird
    7146 # define ALL_TESTS
     7213//# define ALL_TESTS
    71477214#endif
    71487215#if defined(ALL_TESTS)
    … …  
    71607227        { "[v]psubb/[v]psubw/[v]psubd/[v]psubq",            bs3CpuInstr3_v_psubb_psubw_psubd_psubq, 0 },
    71617228#endif
    7162 #if defined(ALL_TESTS)
    7163         { "[v]pmullw/[v]pmulld",                            bs3CpuInstr3_v_pmullw_pmulld,           0 },
     7229#if 1 //defined(ALL_TESTS)
     7230        //{ "[v]pmullw/[v]pmulld",                            bs3CpuInstr3_v_pmullw_pmulld,           0 },
     7231        { "[v]pmulhw",                                      bs3CpuInstr3_v_pmulhw,                  0 },
    71647232#endif
    71657233#if defined(ALL_TESTS)
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