VirtualBox

Changeset 96026 in vbox


Ignore:
Timestamp:
Aug 4, 2022 9:40:00 AM (2 years ago)
Author:
vboxsync
Message:

ValidationKit/bs3-cpu-instr-3: Add [v]pmulhuw instructions testcase, bugref:9898

Location:
trunk/src/VBox/ValidationKit/bootsectors
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac

    r96023 r96026  
    606606EMIT_INSTR_PLUS_ICEBP   vpmulhw, YMM8, YMM9, YMM10
    607607EMIT_INSTR_PLUS_ICEBP   vpmulhw, YMM8, YMM9, FSxBX
     608 %endif
     609
     610;
     611; [V]PMULHUW
     612;
     613EMIT_INSTR_PLUS_ICEBP   pmulhuw, MM1, MM2
     614EMIT_INSTR_PLUS_ICEBP   pmulhuw, MM1, FSxBX
     615
     616EMIT_INSTR_PLUS_ICEBP   pmulhuw, XMM1, XMM2
     617EMIT_INSTR_PLUS_ICEBP   pmulhuw, XMM1, FSxBX
     618 %if TMPL_BITS == 64
     619EMIT_INSTR_PLUS_ICEBP   pmulhuw, XMM8, XMM9
     620EMIT_INSTR_PLUS_ICEBP   pmulhuw, XMM8, FSxBX
     621 %endif
     622
     623EMIT_INSTR_PLUS_ICEBP   vpmulhuw, XMM1, XMM1, XMM2
     624EMIT_INSTR_PLUS_ICEBP   vpmulhuw, XMM1, XMM1, FSxBX
     625 %if TMPL_BITS == 64
     626EMIT_INSTR_PLUS_ICEBP   vpmulhuw, XMM8, XMM9, XMM10
     627EMIT_INSTR_PLUS_ICEBP   vpmulhuw, XMM8, XMM9, FSxBX
     628 %endif
     629
     630EMIT_INSTR_PLUS_ICEBP   vpmulhuw, YMM1, YMM1, YMM2
     631EMIT_INSTR_PLUS_ICEBP   vpmulhuw, YMM1, YMM1, FSxBX
     632 %if TMPL_BITS == 64
     633EMIT_INSTR_PLUS_ICEBP   vpmulhuw, YMM8, YMM9, YMM10
     634EMIT_INSTR_PLUS_ICEBP   vpmulhuw, YMM8, YMM9, FSxBX
    608635 %endif
    609636
  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32

    r96023 r96026  
    23062306        {  bs3CpuInstr3_vpmulhw_YMM1_YMM1_YMM2_icebp_c64,    255,         RM_REG, T_AVX_256,  1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
    23072307        {  bs3CpuInstr3_vpmulhw_YMM1_YMM1_FSxBX_icebp_c64,   X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2308    };
     2309    static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     2310    unsigned const                         iTest       = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
     2311    return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
     2312                                        g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
     2313}
     2314
     2315
     2316/*
     2317 * PMULHUW, VPMULHUW.
     2318 */
     2319BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhuw_MM1_MM2_icebp);
     2320BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhuw_MM1_FSxBX_icebp);
     2321BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhuw_XMM1_XMM2_icebp);
     2322BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhuw_XMM1_FSxBX_icebp);
     2323BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhuw_XMM1_XMM1_XMM2_icebp);
     2324BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhuw_XMM1_XMM1_FSxBX_icebp);
     2325BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhuw_YMM1_YMM1_YMM2_icebp);
     2326BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhuw_YMM1_YMM1_FSxBX_icebp);
     2327
     2328BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmulhuw(uint8_t bMode)
     2329{
     2330    static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] =
     2331    {
     2332        {           RTUINT256_INIT_C(0, 0, 0, 0),
     2333            /* * */ RTUINT256_INIT_C(0, 0, 0, 0),
     2334            /* = */ RTUINT256_INIT_C(0, 0, 0, 0) },
     2335        {           RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888),
     2336            /* * */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000),
     2337            /* = */ RTUINT256_INIT_C(0x49f45f9277760000, 0x0a3d16c1258b369c, 0x0a3d16c1258b369c, 0x49f45f9277760000) },
     2338        {           RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
     2339            /* * */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     2340            /* = */ RTUINT256_INIT_C(0x0949cff503fd16e2, 0x3d510d4619c81583, 0x5fb12b7040963c0a, 0x296cb44814665aaa) },
     2341    };
     2342
     2343    static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
     2344    {
     2345        {  bs3CpuInstr3_pmulhuw_MM1_MM2_icebp_c16,           255,         RM_REG, T_MMX_SSE,  1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2346        {  bs3CpuInstr3_pmulhuw_MM1_FSxBX_icebp_c16,         255,         RM_MEM, T_MMX_SSE,  1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2347        {  bs3CpuInstr3_pmulhuw_XMM1_XMM2_icebp_c16,         255,         RM_REG, T_SSE2,     1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2348        {  bs3CpuInstr3_pmulhuw_XMM1_FSxBX_icebp_c16,        255,         RM_MEM, T_SSE2,     1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2349        {  bs3CpuInstr3_vpmulhuw_XMM1_XMM1_XMM2_icebp_c16,   255,         RM_REG, T_AVX_128,  1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2350        {  bs3CpuInstr3_vpmulhuw_XMM1_XMM1_FSxBX_icebp_c16,  X86_XCPT_DB, RM_MEM, T_AVX_128,  1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2351        {  bs3CpuInstr3_vpmulhuw_YMM1_YMM1_YMM2_icebp_c16,   255,         RM_REG, T_AVX_256,  1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2352        {  bs3CpuInstr3_vpmulhuw_YMM1_YMM1_FSxBX_icebp_c16,  X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2353    };
     2354    static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
     2355    {
     2356        {  bs3CpuInstr3_pmulhuw_MM1_MM2_icebp_c32,           255,         RM_REG, T_MMX_SSE,  1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2357        {  bs3CpuInstr3_pmulhuw_MM1_FSxBX_icebp_c32,         255,         RM_MEM, T_MMX_SSE,  1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2358        {  bs3CpuInstr3_pmulhuw_XMM1_XMM2_icebp_c32,         255,         RM_REG, T_SSE2,     1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2359        {  bs3CpuInstr3_pmulhuw_XMM1_FSxBX_icebp_c32,        255,         RM_MEM, T_SSE2,     1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2360        {  bs3CpuInstr3_vpmulhuw_XMM1_XMM1_XMM2_icebp_c32,   255,         RM_REG, T_AVX_128,  1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2361        {  bs3CpuInstr3_vpmulhuw_XMM1_XMM1_FSxBX_icebp_c32,  X86_XCPT_DB, RM_MEM, T_AVX_128,  1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2362        {  bs3CpuInstr3_vpmulhuw_YMM1_YMM1_YMM2_icebp_c32,   255,         RM_REG, T_AVX_256,  1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2363        {  bs3CpuInstr3_vpmulhuw_YMM1_YMM1_FSxBX_icebp_c32,  X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2364    };
     2365    static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
     2366    {
     2367        {  bs3CpuInstr3_pmulhuw_MM1_MM2_icebp_c64,           255,         RM_REG, T_MMX_SSE,  1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2368        {  bs3CpuInstr3_pmulhuw_MM1_FSxBX_icebp_c64,         255,         RM_MEM, T_MMX_SSE,  1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2369        {  bs3CpuInstr3_pmulhuw_XMM1_XMM2_icebp_c64,         255,         RM_REG, T_SSE2,     1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2370        {  bs3CpuInstr3_pmulhuw_XMM1_FSxBX_icebp_c64,        255,         RM_MEM, T_SSE2,     1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2371        {  bs3CpuInstr3_vpmulhuw_XMM1_XMM1_XMM2_icebp_c64,   255,         RM_REG, T_AVX_128,  1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2372        {  bs3CpuInstr3_vpmulhuw_XMM1_XMM1_FSxBX_icebp_c64,  X86_XCPT_DB, RM_MEM, T_AVX_128,  1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2373        {  bs3CpuInstr3_vpmulhuw_YMM1_YMM1_YMM2_icebp_c64,   255,         RM_REG, T_AVX_256,  1, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
     2374        {  bs3CpuInstr3_vpmulhuw_YMM1_YMM1_FSxBX_icebp_c64,  X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
    23082375    };
    23092376    static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     
    72117278    {
    72127279#ifndef DEBUG_bird
    7213 //# define ALL_TESTS
     7280# define ALL_TESTS
    72147281#endif
    72157282#if defined(ALL_TESTS)
     
    72277294        { "[v]psubb/[v]psubw/[v]psubd/[v]psubq",            bs3CpuInstr3_v_psubb_psubw_psubd_psubq, 0 },
    72287295#endif
    7229 #if 1 //defined(ALL_TESTS)
    7230         //{ "[v]pmullw/[v]pmulld",                            bs3CpuInstr3_v_pmullw_pmulld,           0 },
     7296#if defined(ALL_TESTS)
     7297        { "[v]pmullw/[v]pmulld",                            bs3CpuInstr3_v_pmullw_pmulld,           0 },
    72317298        { "[v]pmulhw",                                      bs3CpuInstr3_v_pmulhw,                  0 },
     7299        { "[v]pmulhuw",                                     bs3CpuInstr3_v_pmulhuw,                 0 },
    72327300#endif
    72337301#if defined(ALL_TESTS)
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