Index: /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac
===================================================================
--- /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac	(revision 96032)
+++ /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac	(revision 96033)
@@ -1845,4 +1845,64 @@
  %endif
 
+;
+; [V]ABSB
+;
+EMIT_INSTR_PLUS_ICEBP pabsb,  MM1, MM2
+EMIT_INSTR_PLUS_ICEBP pabsb,  MM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP pabsb,  XMM1, XMM2
+EMIT_INSTR_PLUS_ICEBP pabsb,  XMM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP vpabsb, XMM1, XMM2
+EMIT_INSTR_PLUS_ICEBP vpabsb, XMM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP vpabsb, YMM1, YMM2
+EMIT_INSTR_PLUS_ICEBP vpabsb, YMM1, FSxBX
+ %if TMPL_BITS == 64
+EMIT_INSTR_PLUS_ICEBP pabsb,  XMM9, XMM8
+EMIT_INSTR_PLUS_ICEBP pabsb,  XMM9, FSxBX
+EMIT_INSTR_PLUS_ICEBP vpabsb, XMM9, XMM8
+EMIT_INSTR_PLUS_ICEBP vpabsb, XMM9, FSxBX
+EMIT_INSTR_PLUS_ICEBP vpabsb, YMM9, YMM8
+EMIT_INSTR_PLUS_ICEBP vpabsb, YMM9, FSxBX
+ %endif
+
+;
+; [V]ABSW
+;
+EMIT_INSTR_PLUS_ICEBP pabsw,  MM1, MM2
+EMIT_INSTR_PLUS_ICEBP pabsw,  MM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP pabsw,  XMM1, XMM2
+EMIT_INSTR_PLUS_ICEBP pabsw,  XMM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP vpabsw, XMM1, XMM2
+EMIT_INSTR_PLUS_ICEBP vpabsw, XMM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP vpabsw, YMM1, YMM2
+EMIT_INSTR_PLUS_ICEBP vpabsw, YMM1, FSxBX
+ %if TMPL_BITS == 64
+EMIT_INSTR_PLUS_ICEBP pabsw,  XMM9, XMM8
+EMIT_INSTR_PLUS_ICEBP pabsw,  XMM9, FSxBX
+EMIT_INSTR_PLUS_ICEBP vpabsw, XMM9, XMM8
+EMIT_INSTR_PLUS_ICEBP vpabsw, XMM9, FSxBX
+EMIT_INSTR_PLUS_ICEBP vpabsw, YMM9, YMM8
+EMIT_INSTR_PLUS_ICEBP vpabsw, YMM9, FSxBX
+ %endif
+
+;
+; [V]ABSD
+;
+EMIT_INSTR_PLUS_ICEBP pabsd,  MM1, MM2
+EMIT_INSTR_PLUS_ICEBP pabsd,  MM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP pabsd,  XMM1, XMM2
+EMIT_INSTR_PLUS_ICEBP pabsd,  XMM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP vpabsd, XMM1, XMM2
+EMIT_INSTR_PLUS_ICEBP vpabsd, XMM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP vpabsd, YMM1, YMM2
+EMIT_INSTR_PLUS_ICEBP vpabsd, YMM1, FSxBX
+ %if TMPL_BITS == 64
+EMIT_INSTR_PLUS_ICEBP pabsd,  XMM9, XMM8
+EMIT_INSTR_PLUS_ICEBP pabsd,  XMM9, FSxBX
+EMIT_INSTR_PLUS_ICEBP vpabsd, XMM9, XMM8
+EMIT_INSTR_PLUS_ICEBP vpabsd, XMM9, FSxBX
+EMIT_INSTR_PLUS_ICEBP vpabsd, YMM9, YMM8
+EMIT_INSTR_PLUS_ICEBP vpabsd, YMM9, FSxBX
+ %endif
+
 
 %endif ; BS3_INSTANTIATING_CMN
Index: /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32
===================================================================
--- /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32	(revision 96032)
+++ /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32	(revision 96033)
@@ -7060,4 +7060,200 @@
     return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig1, RT_ELEMENTS(g_aXcptConfig1), 255 /*cbMaxAlign*/);
+}
+
+
+/*
+ * [V]PABSB / [V]PABSW / [V]PABSD
+ */
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsb_MM1_MM2_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsb_MM1_FSxBX_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsb_XMM1_XMM2_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsb_XMM1_FSxBX_icebp);
+extern FNBS3FAR             bs3CpuInstr3_pabsb_XMM9_XMM8_icebp_c64;
+extern FNBS3FAR             bs3CpuInstr3_pabsb_XMM9_FSxBX_icebp_c64;
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsb_XMM1_XMM2_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsb_XMM1_FSxBX_icebp);
+extern FNBS3FAR             bs3CpuInstr3_vpabsb_XMM9_XMM8_icebp_c64;
+extern FNBS3FAR             bs3CpuInstr3_vpabsb_XMM9_FSxBX_icebp_c64;
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsb_YMM1_YMM2_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsb_YMM1_FSxBX_icebp);
+extern FNBS3FAR             bs3CpuInstr3_vpabsb_YMM9_YMM8_icebp_c64;
+extern FNBS3FAR             bs3CpuInstr3_vpabsb_YMM9_FSxBX_icebp_c64;
+
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsw_MM1_MM2_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsw_MM1_FSxBX_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsw_XMM1_XMM2_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsw_XMM1_FSxBX_icebp);
+extern FNBS3FAR             bs3CpuInstr3_pabsw_XMM9_XMM8_icebp_c64;
+extern FNBS3FAR             bs3CpuInstr3_pabsw_XMM9_FSxBX_icebp_c64;
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsw_XMM1_XMM2_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsw_XMM1_FSxBX_icebp);
+extern FNBS3FAR             bs3CpuInstr3_vpabsw_XMM9_XMM8_icebp_c64;
+extern FNBS3FAR             bs3CpuInstr3_vpabsw_XMM9_FSxBX_icebp_c64;
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsw_YMM1_YMM2_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsw_YMM1_FSxBX_icebp);
+extern FNBS3FAR             bs3CpuInstr3_vpabsw_YMM9_YMM8_icebp_c64;
+extern FNBS3FAR             bs3CpuInstr3_vpabsw_YMM9_FSxBX_icebp_c64;
+
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsd_MM1_MM2_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsd_MM1_FSxBX_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsd_XMM1_XMM2_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsd_XMM1_FSxBX_icebp);
+extern FNBS3FAR             bs3CpuInstr3_pabsd_XMM9_XMM8_icebp_c64;
+extern FNBS3FAR             bs3CpuInstr3_pabsd_XMM9_FSxBX_icebp_c64;
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsd_XMM1_XMM2_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsd_XMM1_FSxBX_icebp);
+extern FNBS3FAR             bs3CpuInstr3_vpabsd_XMM9_XMM8_icebp_c64;
+extern FNBS3FAR             bs3CpuInstr3_vpabsd_XMM9_FSxBX_icebp_c64;
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsd_YMM1_YMM2_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsd_YMM1_FSxBX_icebp);
+extern FNBS3FAR             bs3CpuInstr3_vpabsd_YMM9_YMM8_icebp_c64;
+extern FNBS3FAR             bs3CpuInstr3_vpabsd_YMM9_FSxBX_icebp_c64;
+
+BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pabsb_pabsw_pabsd(uint8_t bMode)
+{
+    static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesB[] =
+    {
+        {            RTUINT256_INIT_C(0, 0, 0, 0),
+            /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
+        {            RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
+            /* => */ RTUINT256_INIT_C(0x0101010101010101, 0x0101010101010101, 0x0101010101010101, 0x0101010101010101) },
+        {            RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888),
+            /* => */ RTUINT256_INIT_C(0x6767565645453434, 0x2323121201012121, 0x1111222233334444, 0x5555666677777878) },
+        {            RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
+            /* => */ RTUINT256_INIT_C(0x4d09102a6c24732b, 0x3e0c1738666b3f1a, 0x4c212f58564c655e, 0x645c20736d096a45) },
+    };
+    static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesW[] =
+    {
+        {            RTUINT256_INIT_C(0, 0, 0, 0),
+            /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
+        {            RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
+            /* => */ RTUINT256_INIT_C(0x0001000100010001, 0x0001000100010001, 0x0001000100010001, 0x0001000100010001) },
+        {            RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888),
+            /* => */ RTUINT256_INIT_C(0x6667555644453334, 0x2223111200012121, 0x1111222233334444, 0x5555666677777778) },
+        {            RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
+            /* => */ RTUINT256_INIT_C(0x4d090fd66cdc73d5, 0x3ef417c8666b3fe6, 0x4bdf2fa8564c645e, 0x63a41f8d6cf76945) },
+    };
+    static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesD[] =
+    {
+        {            RTUINT256_INIT_C(0, 0, 0, 0),
+            /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
+        {            RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
+            /* => */ RTUINT256_INIT_C(0x0000000100000001, 0x0000000100000001, 0x0000000100000001, 0x0000000100000001) },
+        {            RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888),
+            /* => */ RTUINT256_INIT_C(0x6666555644443334, 0x222211120000dedf, 0x1111222233334444, 0x5555666677778888) },
+        {            RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
+            /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0x4bded058564c9ba2, 0x63a31f8d6cf66945) },
+    };
+
+    static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
+    {
+        {  bs3CpuInstr3_pabsb_MM1_MM2_icebp_c16,     255,         RM_REG, T_MMX_SSSE3, 1,   2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_pabsb_MM1_FSxBX_icebp_c16,   255,         RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_pabsb_XMM1_XMM2_icebp_c16,   255,         RM_REG, T_SSSE3,     1,   2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_pabsb_XMM1_FSxBX_icebp_c16,  255,         RM_MEM, T_SSSE3,     1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_vpabsb_XMM1_XMM2_icebp_c16,  255,         RM_REG, T_AVX_128,   1,   2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_vpabsb_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_vpabsb_YMM1_YMM2_icebp_c16,  255,         RM_REG, T_AVX_256,   1,   2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_vpabsb_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256,   1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+
+        {  bs3CpuInstr3_pabsw_MM1_MM2_icebp_c16,     255,         RM_REG, T_MMX_SSSE3, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_pabsw_MM1_FSxBX_icebp_c16,   255,         RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_pabsw_XMM1_XMM2_icebp_c16,   255,         RM_REG, T_SSSE3,     1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_pabsw_XMM1_FSxBX_icebp_c16,  255,         RM_MEM, T_SSSE3,     1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_vpabsw_XMM1_XMM2_icebp_c16,  255,         RM_REG, T_AVX_128,   1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_vpabsw_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_vpabsw_YMM1_YMM2_icebp_c16,  255,         RM_REG, T_AVX_256,   1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_vpabsw_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256,   1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+
+        {  bs3CpuInstr3_pabsd_MM1_MM2_icebp_c16,     255,         RM_REG, T_MMX_SSSE3, 1,   2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_pabsd_MM1_FSxBX_icebp_c16,   255,         RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_pabsd_XMM1_XMM2_icebp_c16,   255,         RM_REG, T_SSSE3,     1,   2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_pabsd_XMM1_FSxBX_icebp_c16,  255,         RM_MEM, T_SSSE3,     1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_vpabsd_XMM1_XMM2_icebp_c16,  255,         RM_REG, T_AVX_128,   1,   2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_vpabsd_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_vpabsd_YMM1_YMM2_icebp_c16,  255,         RM_REG, T_AVX_256,   1,   2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_vpabsd_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256,   1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+    };
+    static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
+    {
+        {  bs3CpuInstr3_pabsb_MM1_MM2_icebp_c32,     255,         RM_REG, T_MMX_SSSE3, 1,   2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_pabsb_MM1_FSxBX_icebp_c32,   255,         RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_pabsb_XMM1_XMM2_icebp_c32,   255,         RM_REG, T_SSSE3,     1,   2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_pabsb_XMM1_FSxBX_icebp_c32,  255,         RM_MEM, T_SSSE3,     1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_vpabsb_XMM1_XMM2_icebp_c32,  255,         RM_REG, T_AVX_128,   1,   2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_vpabsb_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_vpabsb_YMM1_YMM2_icebp_c32,  255,         RM_REG, T_AVX_256,   1,   2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_vpabsb_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256,   1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+
+        {  bs3CpuInstr3_pabsw_MM1_MM2_icebp_c32,     255,         RM_REG, T_MMX_SSSE3, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_pabsw_MM1_FSxBX_icebp_c32,   255,         RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_pabsw_XMM1_XMM2_icebp_c32,   255,         RM_REG, T_SSSE3,     1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_pabsw_XMM1_FSxBX_icebp_c32,  255,         RM_MEM, T_SSSE3,     1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_vpabsw_XMM1_XMM2_icebp_c32,  255,         RM_REG, T_AVX_128,   1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_vpabsw_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_vpabsw_YMM1_YMM2_icebp_c32,  255,         RM_REG, T_AVX_256,   1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_vpabsw_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256,   1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+
+        {  bs3CpuInstr3_pabsd_MM1_MM2_icebp_c32,     255,         RM_REG, T_MMX_SSSE3, 1,   2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_pabsd_MM1_FSxBX_icebp_c32,   255,         RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_pabsd_XMM1_XMM2_icebp_c32,   255,         RM_REG, T_SSSE3,     1,   2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_pabsd_XMM1_FSxBX_icebp_c32,  255,         RM_MEM, T_SSSE3,     1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_vpabsd_XMM1_XMM2_icebp_c32,  255,         RM_REG, T_AVX_128,   1,   2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_vpabsd_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_vpabsd_YMM1_YMM2_icebp_c32,  255,         RM_REG, T_AVX_256,   1,   2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_vpabsd_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256,   1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+    };
+    static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
+    {
+        {  bs3CpuInstr3_pabsb_MM1_MM2_icebp_c64,     255,         RM_REG, T_MMX_SSSE3, 1,   2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_pabsb_MM1_FSxBX_icebp_c64,   255,         RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_pabsb_XMM1_XMM2_icebp_c64,   255,         RM_REG, T_SSSE3,     1,   2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_pabsb_XMM1_FSxBX_icebp_c64,  255,         RM_MEM, T_SSSE3,     1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_pabsb_XMM9_XMM8_icebp_c64,   255,         RM_REG, T_SSSE3,     9,   8, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_pabsb_XMM9_FSxBX_icebp_c64,  255,         RM_MEM, T_SSSE3,     9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_vpabsb_XMM1_XMM2_icebp_c64,  255,         RM_REG, T_AVX_128,   1,   2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_vpabsb_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_vpabsb_XMM9_XMM8_icebp_c64,  255,         RM_REG, T_AVX_128,   9,   8, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_vpabsb_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,   9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_vpabsb_YMM1_YMM2_icebp_c64,  255,         RM_REG, T_AVX_256,   1,   2, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_vpabsb_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256,   1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_vpabsb_YMM9_YMM8_icebp_c64,  255,         RM_REG, T_AVX_256,   9,   8, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+        {  bs3CpuInstr3_vpabsb_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256,   9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB },
+
+        {  bs3CpuInstr3_pabsw_MM1_MM2_icebp_c64,     255,         RM_REG, T_MMX_SSSE3, 1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_pabsw_MM1_FSxBX_icebp_c64,   255,         RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_pabsw_XMM1_XMM2_icebp_c64,   255,         RM_REG, T_SSSE3,     1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_pabsw_XMM1_FSxBX_icebp_c64,  255,         RM_MEM, T_SSSE3,     1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_pabsw_XMM9_XMM8_icebp_c64,   255,         RM_REG, T_SSSE3,     9,   8, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_pabsw_XMM9_FSxBX_icebp_c64,  255,         RM_MEM, T_SSSE3,     9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_vpabsw_XMM1_XMM2_icebp_c64,  255,         RM_REG, T_AVX_128,   1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_vpabsw_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_vpabsw_XMM9_XMM8_icebp_c64,  255,         RM_REG, T_AVX_128,   9,   8, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_vpabsw_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,   9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_vpabsw_YMM1_YMM2_icebp_c64,  255,         RM_REG, T_AVX_256,   1,   2, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_vpabsw_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256,   1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_vpabsw_YMM9_YMM8_icebp_c64,  255,         RM_REG, T_AVX_256,   9,   8, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+        {  bs3CpuInstr3_vpabsw_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256,   9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW },
+
+        {  bs3CpuInstr3_pabsd_MM1_MM2_icebp_c64,     255,         RM_REG, T_MMX_SSSE3, 1,   2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_pabsd_MM1_FSxBX_icebp_c64,   255,         RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_pabsd_XMM1_XMM2_icebp_c64,   255,         RM_REG, T_SSSE3,     1,   2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_pabsd_XMM1_FSxBX_icebp_c64,  255,         RM_MEM, T_SSSE3,     1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_pabsd_XMM9_XMM8_icebp_c64,   255,         RM_REG, T_SSSE3,     9,   8, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_pabsd_XMM9_FSxBX_icebp_c64,  255,         RM_MEM, T_SSSE3,     9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_vpabsd_XMM1_XMM2_icebp_c64,  255,         RM_REG, T_AVX_128,   1,   2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_vpabsd_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_vpabsd_XMM9_XMM8_icebp_c64,  255,         RM_REG, T_AVX_128,   9,   8, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_vpabsd_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,   9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_vpabsd_YMM1_YMM2_icebp_c64,  255,         RM_REG, T_AVX_256,   1,   2, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_vpabsd_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256,   1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_vpabsd_YMM9_YMM8_icebp_c64,  255,         RM_REG, T_AVX_256,   9,   8, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+        {  bs3CpuInstr3_vpabsd_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256,   9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD },
+    };
+    static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
+    unsigned const                         iTest       = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
+    return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+                                        g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), X86_EFL_STATUS_BITS);
 }
 
@@ -7495,4 +7691,7 @@
         { "[v]pavgb/[v]pavgw",                              bs3CpuInstr3_v_pavgb_pavgw, 0 },
 #endif
+#if defined(ALL_TESTS)
+        { "[v]pabsb/[v]pabsw/[v]pabsd",                     bs3CpuInstr3_v_pabsb_pabsw_pabsd, 0 },
+#endif
     };
     Bs3TestInit("bs3-cpu-instr-3");
