Changeset 96047 in vbox for trunk/src/VBox/ValidationKit/bootsectors
- Timestamp:
- Aug 5, 2022 9:48:23 AM (3 years ago)
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 2 edited
-
bs3-cpu-instr-3-template.mac (modified) (1 diff)
-
bs3-cpu-instr-3.c32 (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac
r96035 r96047 1986 1986 %endif 1987 1987 1988 ; 1989 ; [V]PHADDW 1990 ; 1991 EMIT_INSTR_PLUS_ICEBP phaddw, MM1, MM2 1992 EMIT_INSTR_PLUS_ICEBP phaddw, MM1, FSxBX 1993 EMIT_INSTR_PLUS_ICEBP phaddw, XMM1, XMM2 1994 EMIT_INSTR_PLUS_ICEBP phaddw, XMM1, FSxBX 1995 EMIT_INSTR_PLUS_ICEBP vphaddw, XMM1, XMM2, XMM3 1996 EMIT_INSTR_PLUS_ICEBP vphaddw, XMM1, XMM2, FSxBX 1997 EMIT_INSTR_PLUS_ICEBP vphaddw, YMM1, YMM2, YMM3 1998 EMIT_INSTR_PLUS_ICEBP vphaddw, YMM1, YMM2, FSxBX 1999 %if TMPL_BITS == 64 2000 EMIT_INSTR_PLUS_ICEBP phaddw, XMM8, XMM9 2001 EMIT_INSTR_PLUS_ICEBP phaddw, XMM8, FSxBX 2002 EMIT_INSTR_PLUS_ICEBP vphaddw, XMM8, XMM9, XMM10 2003 EMIT_INSTR_PLUS_ICEBP vphaddw, XMM8, XMM9, FSxBX 2004 EMIT_INSTR_PLUS_ICEBP vphaddw, YMM8, YMM9, YMM10 2005 EMIT_INSTR_PLUS_ICEBP vphaddw, YMM8, YMM9, FSxBX 2006 %endif 2007 2008 ; 2009 ; [V]PHADDD 2010 ; 2011 EMIT_INSTR_PLUS_ICEBP phaddd, MM1, MM2 2012 EMIT_INSTR_PLUS_ICEBP phaddd, MM1, FSxBX 2013 EMIT_INSTR_PLUS_ICEBP phaddd, XMM1, XMM2 2014 EMIT_INSTR_PLUS_ICEBP phaddd, XMM1, FSxBX 2015 EMIT_INSTR_PLUS_ICEBP vphaddd, XMM1, XMM2, XMM3 2016 EMIT_INSTR_PLUS_ICEBP vphaddd, XMM1, XMM2, FSxBX 2017 EMIT_INSTR_PLUS_ICEBP vphaddd, YMM1, YMM2, YMM3 2018 EMIT_INSTR_PLUS_ICEBP vphaddd, YMM1, YMM2, FSxBX 2019 %if TMPL_BITS == 64 2020 EMIT_INSTR_PLUS_ICEBP phaddd, XMM8, XMM9 2021 EMIT_INSTR_PLUS_ICEBP phaddd, XMM8, FSxBX 2022 EMIT_INSTR_PLUS_ICEBP vphaddd, XMM8, XMM9, XMM10 2023 EMIT_INSTR_PLUS_ICEBP vphaddd, XMM8, XMM9, FSxBX 2024 EMIT_INSTR_PLUS_ICEBP vphaddd, YMM8, YMM9, YMM10 2025 EMIT_INSTR_PLUS_ICEBP vphaddd, YMM8, YMM9, FSxBX 2026 %endif 2027 1988 2028 1989 2029 %endif ; BS3_INSTANTIATING_CMN -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32
r96035 r96047 5199 5199 { bs3CpuInstr3_vpsignd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 5200 5200 { bs3CpuInstr3_vpsignd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, 5201 }; 5202 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 5203 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); 5204 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 5205 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); 5206 } 5207 5208 5209 /* 5210 * [V]PHADDW - Horizontally add word sized signed integers. 5211 * [V]PHADDD - Horizontally add doubleword sized signed integers. 5212 */ 5213 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddw_MM1_MM2_icebp); 5214 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddw_MM1_FSxBX_icebp); 5215 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddw_XMM1_XMM2_icebp); 5216 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddw_XMM1_FSxBX_icebp); 5217 extern FNBS3FAR bs3CpuInstr3_phaddw_XMM8_XMM9_icebp_c64; 5218 extern FNBS3FAR bs3CpuInstr3_phaddw_XMM8_FSxBX_icebp_c64; 5219 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddw_XMM1_XMM2_XMM3_icebp); 5220 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddw_XMM1_XMM2_FSxBX_icebp); 5221 extern FNBS3FAR bs3CpuInstr3_vphaddw_XMM8_XMM9_XMM10_icebp_c64; 5222 extern FNBS3FAR bs3CpuInstr3_vphaddw_XMM8_XMM9_FSxBX_icebp_c64; 5223 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddw_YMM1_YMM2_YMM3_icebp); 5224 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddw_YMM1_YMM2_FSxBX_icebp); 5225 extern FNBS3FAR bs3CpuInstr3_vphaddw_YMM8_YMM9_YMM10_icebp_c64; 5226 extern FNBS3FAR bs3CpuInstr3_vphaddw_YMM8_YMM9_FSxBX_icebp_c64; 5227 5228 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddd_MM1_MM2_icebp); 5229 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddd_MM1_FSxBX_icebp); 5230 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddd_XMM1_XMM2_icebp); 5231 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddd_XMM1_FSxBX_icebp); 5232 extern FNBS3FAR bs3CpuInstr3_phaddd_XMM8_XMM9_icebp_c64; 5233 extern FNBS3FAR bs3CpuInstr3_phaddd_XMM8_FSxBX_icebp_c64; 5234 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddd_XMM1_XMM2_XMM3_icebp); 5235 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddd_XMM1_XMM2_FSxBX_icebp); 5236 extern FNBS3FAR bs3CpuInstr3_vphaddd_XMM8_XMM9_XMM10_icebp_c64; 5237 extern FNBS3FAR bs3CpuInstr3_vphaddd_XMM8_XMM9_FSxBX_icebp_c64; 5238 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddd_YMM1_YMM2_YMM3_icebp); 5239 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddd_YMM1_YMM2_FSxBX_icebp); 5240 extern FNBS3FAR bs3CpuInstr3_vphaddd_YMM8_YMM9_YMM10_icebp_c64; 5241 extern FNBS3FAR bs3CpuInstr3_vphaddd_YMM8_YMM9_FSxBX_icebp_c64; 5242 5243 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_phaddw_phaddd(uint8_t bMode) 5244 { 5245 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64W[] = 5246 { 5247 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 5248 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 5249 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 5250 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 5251 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), 5252 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x85868d8e05060d0e) }, 5253 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 5254 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 5255 /* => */ RTUINT256_INIT_C( 5, 6, 7, 0x7ccf29c41173bd81) }, 5256 }; 5257 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128W[] = 5258 { 5259 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 5260 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 5261 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 5262 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 5263 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), 5264 /* => */ RTUINT256_INIT_C( 9, 10, 0xa5a6adae85868d8e, 0x25262d2e05060d0e) }, 5265 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 5266 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 5267 /* => */ RTUINT256_INIT_C( 13, 14, 0xe3c9f1ee7ccf29c4, 0x715b225c1173bd81) }, 5268 }; 5269 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256W[] = 5270 { 5271 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 5272 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 5273 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 5274 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 5275 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), 5276 /* => */ RTUINT256_INIT_C(0xe5e6edeec5c6cdce, 0x65666d6e45464d4e, 0xa5a6adae85868d8e, 0x25262d2e05060d0e) }, 5277 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 5278 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 5279 /* => */ RTUINT256_INIT_C(0x3d33e0b156bca651, 0xfc893bf7884896a5, 0xe3c9f1ee7ccf29c4, 0x715b225c1173bd81) }, 5280 }; 5281 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64D[] = 5282 { 5283 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 5284 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 5285 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 5286 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 5287 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), 5288 /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x87898b8c07090b0c) }, 5289 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 5290 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 5291 /* => */ RTUINT256_INIT_C( 5, 6, 7, 0x2f66772e6758679d) }, 5292 }; 5293 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128D[] = 5294 { 5295 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 5296 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 5297 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 5298 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 5299 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), 5300 /* => */ RTUINT256_INIT_C( 9, 10, 0xa7a9abac87898b8c, 0x27292b2c07090b0c) }, 5301 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 5302 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 5303 /* => */ RTUINT256_INIT_C( 13, 14, 0x0a6dcb4a2f66772e, 0x479a4c1e6758679d) }, 5304 }; 5305 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256D[] = 5306 { 5307 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 5308 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 5309 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 5310 { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 5311 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), 5312 /* => */ RTUINT256_INIT_C(0xe7e9ebecc7c9cbcc, 0x67696b6c47494b4c, 0xa7a9abac87898b8c, 0x27292b2c07090b0c) }, 5313 { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 5314 /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 5315 /* => */ RTUINT256_INIT_C(0xb9e663ffa55f57ae, 0x2841104039cee51f, 0x0a6dcb4a2f66772e, 0x479a4c1e6758679d) }, 5316 }; 5317 5318 static BS3CPUINSTR3_TEST1_T const s_aTests16[] = 5319 { 5320 { bs3CpuInstr3_phaddw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, 5321 { bs3CpuInstr3_phaddw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, 5322 { bs3CpuInstr3_phaddw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, 5323 { bs3CpuInstr3_phaddw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, 5324 { bs3CpuInstr3_vphaddw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, 5325 { bs3CpuInstr3_vphaddw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, 5326 { bs3CpuInstr3_vphaddw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, 5327 { bs3CpuInstr3_vphaddw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, 5328 5329 { bs3CpuInstr3_phaddd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64D), s_aValues64D }, 5330 { bs3CpuInstr3_phaddd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64D), s_aValues64D }, 5331 { bs3CpuInstr3_phaddd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128D), s_aValues128D }, 5332 { bs3CpuInstr3_phaddd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, 5333 { bs3CpuInstr3_vphaddd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128D), s_aValues128D }, 5334 { bs3CpuInstr3_vphaddd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, 5335 { bs3CpuInstr3_vphaddd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256D), s_aValues256D }, 5336 { bs3CpuInstr3_vphaddd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D }, 5337 }; 5338 static BS3CPUINSTR3_TEST1_T const s_aTests32[] = 5339 { 5340 { bs3CpuInstr3_phaddw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, 5341 { bs3CpuInstr3_phaddw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, 5342 { bs3CpuInstr3_phaddw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, 5343 { bs3CpuInstr3_phaddw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, 5344 { bs3CpuInstr3_vphaddw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, 5345 { bs3CpuInstr3_vphaddw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, 5346 { bs3CpuInstr3_vphaddw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, 5347 { bs3CpuInstr3_vphaddw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, 5348 5349 { bs3CpuInstr3_phaddd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64D), s_aValues64D }, 5350 { bs3CpuInstr3_phaddd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64D), s_aValues64D }, 5351 { bs3CpuInstr3_phaddd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128D), s_aValues128D }, 5352 { bs3CpuInstr3_phaddd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, 5353 { bs3CpuInstr3_vphaddd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128D), s_aValues128D }, 5354 { bs3CpuInstr3_vphaddd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, 5355 { bs3CpuInstr3_vphaddd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256D), s_aValues256D }, 5356 { bs3CpuInstr3_vphaddd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D }, 5357 }; 5358 static BS3CPUINSTR3_TEST1_T const s_aTests64[] = 5359 { 5360 { bs3CpuInstr3_phaddw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, 5361 { bs3CpuInstr3_phaddw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, 5362 { bs3CpuInstr3_phaddw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, 5363 { bs3CpuInstr3_phaddw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, 5364 { bs3CpuInstr3_phaddw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128W), s_aValues128W }, 5365 { bs3CpuInstr3_phaddw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, 5366 { bs3CpuInstr3_vphaddw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, 5367 { bs3CpuInstr3_vphaddw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, 5368 { bs3CpuInstr3_vphaddw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128W), s_aValues128W }, 5369 { bs3CpuInstr3_vphaddw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, 5370 { bs3CpuInstr3_vphaddw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, 5371 { bs3CpuInstr3_vphaddw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, 5372 { bs3CpuInstr3_vphaddw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256W), s_aValues256W }, 5373 { bs3CpuInstr3_vphaddw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, 5374 5375 { bs3CpuInstr3_phaddd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64D), s_aValues64D }, 5376 { bs3CpuInstr3_phaddd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64D), s_aValues64D }, 5377 { bs3CpuInstr3_phaddd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128D), s_aValues128D }, 5378 { bs3CpuInstr3_phaddd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, 5379 { bs3CpuInstr3_phaddd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128D), s_aValues128D }, 5380 { bs3CpuInstr3_phaddd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, 5381 { bs3CpuInstr3_vphaddd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128D), s_aValues128D }, 5382 { bs3CpuInstr3_vphaddd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, 5383 { bs3CpuInstr3_vphaddd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128D), s_aValues128D }, 5384 { bs3CpuInstr3_vphaddd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, 5385 { bs3CpuInstr3_vphaddd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256D), s_aValues256D }, 5386 { bs3CpuInstr3_vphaddd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D }, 5387 { bs3CpuInstr3_vphaddd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256D), s_aValues256D }, 5388 { bs3CpuInstr3_vphaddd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D }, 5201 5389 }; 5202 5390 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); … … 7896 8084 { "[v]psignb/[v]psignw/[v]psignd", bs3CpuInstr3_v_psignb_psignw_psignd, 0 }, 7897 8085 #endif 8086 #if defined(ALL_TESTS) 8087 { "[v]phaddw/[v]phaddd", bs3CpuInstr3_v_phaddw_phaddd, 0 }, 8088 #endif 7898 8089 }; 7899 8090 Bs3TestInit("bs3-cpu-instr-3");
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