Changeset 9606 in vbox
- Timestamp:
- Jun 11, 2008 12:25:36 PM (17 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/PGM.cpp
r9597 r9606 2383 2383 /** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */ 2384 2384 /* Big pages supported? */ 2385 const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE); 2385 bool fPSE; 2386 2387 if (CPUMGetGuestMode(pVM) == CPUMMODE_LONG) 2388 fPSE = true; 2389 else 2390 fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE); 2391 2386 2392 /* Global pages supported? */ 2387 2393 const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE); … … 3256 3262 return VERR_INVALID_PARAMETER; 3257 3263 } 3264 bool fBigPagesSupported; 3265 3266 if (CPUMGetGuestMode(pVM) == CPUMMODE_LONG) 3267 fBigPagesSupported = true; 3268 else 3269 fBigPagesSupported = !!(cr4 & X86_CR4_PSE); 3270 3258 3271 int rc = VINF_SUCCESS; 3259 3272 for (unsigned i = 0; i < ELEMENTS(pPD->a); i++) … … 3262 3275 if (Pde.n.u1Present) 3263 3276 { 3264 if ( (cr4 & X86_CR4_PSE)&& Pde.b.u1Size)3277 if (fBigPagesSupported && Pde.b.u1Size) 3265 3278 pHlp->pfnPrintf(pHlp, 3266 3279 fLongMode /*P R S A D G WT CD AT NX 4M a p ? */ -
trunk/src/VBox/VMM/VMMAll/PGMAllBth.h
r9589 r9606 304 304 305 305 # if PGM_WITH_PAGING(PGM_GST_TYPE) 306 uint32_t cr4 = CPUMGetGuestCR4(pVM); 306 # if PGM_GST_TYPE == PGM_TYPE_AMD64 307 bool fBigPagesSupported = true; 308 # else 309 bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE); 310 # endif 307 311 if ( PdeSrc.b.u1Size 308 && (cr4 & X86_CR4_PSE))312 && fBigPagesSupported) 309 313 GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK) 310 314 | ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK)); … … 925 929 926 930 const uint32_t cr4 = CPUMGetGuestCR4(pVM); 931 # if PGM_GST_TYPE == PGM_TYPE_AMD64 932 const bool fIsBigPage = PdeSrc.b.u1Size; 933 # else 927 934 const bool fIsBigPage = PdeSrc.b.u1Size && (cr4 & X86_CR4_PSE); 935 # endif 928 936 929 937 # ifdef IN_RING3 … … 1463 1471 * Check that the page is present and that the shadow PDE isn't out of sync. 1464 1472 */ 1473 # if PGM_GST_TYPE == PGM_TYPE_AMD64 1474 const bool fBigPage = PdeSrc.b.u1Size; 1475 # else 1465 1476 const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE); 1477 # endif 1466 1478 RTGCPHYS GCPhys; 1467 1479 if (!fBigPage) … … 1800 1812 bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US); 1801 1813 bool fWriteFault = !!(uErr & X86_TRAP_PF_RW); 1814 # if PGM_GST_TYPE == PGM_TYPE_AMD64 1815 bool fBigPagesSupported = true; 1816 # else 1802 1817 bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE); 1818 # endif 1803 1819 # if PGM_WITH_NX(PGM_GST_TYPE) 1804 1820 bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE); … … 2189 2205 */ 2190 2206 PSHWPT pPTDst; 2207 # if PGM_GST_TYPE == PGM_TYPE_AMD64 2208 const bool fPageTable = !PdeSrc.b.u1Size; 2209 # else 2191 2210 const bool fPageTable = !PdeSrc.b.u1Size || !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE); 2211 # endif 2192 2212 PPGMPOOLPAGE pShwPage; 2193 2213 RTGCPHYS GCPhys; … … 2788 2808 DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4) 2789 2809 { 2810 # if PMG_GST_TYPE == PGM_TYPE_AMD64 2811 if (!pPdeSrc->n.u1Size) 2812 # else 2790 2813 if (!pPdeSrc->n.u1Size || !(cr4 & X86_CR4_PSE)) 2814 # endif 2791 2815 return BTH_PGMPOOLKIND_PT_FOR_PT; 2792 2816 //switch (pPdeSrc->u & (X86_PDE4M_RW | X86_PDE4M_US /*| X86_PDE4M_PAE_NX*/)) … … 2879 2903 2880 2904 # if PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE || PGM_GST_TYPE == PGM_TYPE_AMD64 2905 # if PGM_GST_TYPE == PGM_TYPE_AMD64 2906 bool fBigPagesSupported = true; 2907 # else 2908 bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE); 2909 # endif 2910 2881 2911 /* 2882 2912 * Get page directory addresses. … … 3099 3129 RTGCPHYS GCPhys; 3100 3130 if ( !PdeSrc.b.u1Size 3101 || ! (cr4 & X86_CR4_PSE))3131 || !fBigPagesSupported) 3102 3132 { 3103 3133 GCPhys = PdeSrc.u & GST_PDE_PG_MASK; … … 3123 3153 # ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH 3124 3154 || ( (PdeSrc.u & (X86_PDE4M_PS | X86_PDE4M_G)) == (X86_PDE4M_PS | X86_PDE4M_G) 3155 # if PGM_GST_TYPE == PGM_TYPE_AMD64 3156 && (cr4 & X86_CR4_PGE)) /* global 2/4MB page. */ 3157 # else 3125 3158 && (cr4 & (X86_CR4_PGE | X86_CR4_PSE)) == (X86_CR4_PGE | X86_CR4_PSE)) /* global 2/4MB page. */ 3159 # endif 3126 3160 || ( !pShwPage->fSeenNonGlobal 3127 3161 && (cr4 & X86_CR4_PGE)) … … 3131 3165 ) 3132 3166 && ( (PdeSrc.u & (X86_PDE_US | X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US | X86_PDE_RW)) 3133 || ( (cr4 & X86_CR4_PSE)3167 || ( fBigPagesSupported 3134 3168 && ((PdeSrc.u & (X86_PDE_US | X86_PDE4M_PS | X86_PDE4M_D)) | PGM_PDFLAGS_TRACK_DIRTY) 3135 3169 == ((PdeDst.u & (X86_PDE_US | X86_PDE_RW | PGM_PDFLAGS_TRACK_DIRTY)) | X86_PDE4M_PS)) … … 3140 3174 if ( !fGlobal 3141 3175 && (PdeSrc.u & (X86_PDE4M_PS | X86_PDE4M_G)) == (X86_PDE4M_PS | X86_PDE4M_G) 3176 # if PGM_GST_TYPE == PGM_TYPE_AMD64 3177 && (cr4 & X86_CR4_PGE)) /* global 2/4MB page. */ 3178 # else 3142 3179 && (cr4 & (X86_CR4_PGE | X86_CR4_PSE)) == (X86_CR4_PGE | X86_CR4_PSE)) 3180 # endif 3143 3181 MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPD)); 3144 3182 else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE)) … … 3320 3358 || PGM_GST_TYPE == PGM_TYPE_PAE 3321 3359 3360 # if PGM_GST_TYPE == PGM_TYPE_AMD64 3361 bool fBigPagesSupported = true; 3362 # else 3363 bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE); 3364 # endif 3322 3365 PPGM pPGM = &pVM->pgm.s; 3323 3366 RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */ … … 3461 3504 3462 3505 if ( !PdeSrc.b.u1Size 3463 || ! (cr4 & X86_CR4_PSE))3506 || !fBigPagesSupported) 3464 3507 { 3465 3508 GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK; … … 3486 3529 3487 3530 if ( pPoolPage->enmKind 3488 != (!PdeSrc.b.u1Size || ! (cr4 & X86_CR4_PSE)? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))3531 != (!PdeSrc.b.u1Size || !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG)) 3489 3532 { 3490 3533 AssertMsgFailed(("Invalid shadow page table kind %d at %VGv! PdeSrc=%#RX64\n", … … 3511 3554 3512 3555 if ( !PdeSrc.b.u1Size 3513 || ! (cr4 & X86_CR4_PSE))3556 || !fBigPagesSupported) 3514 3557 { 3515 3558 /* -
trunk/src/VBox/VMM/VMMAll/PGMAllGst.h
r9575 r9606 194 194 195 195 if ( !Pde.b.u1Size 196 || !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)) 196 # if PGM_GST_TYPE != PGM_TYPE_AMD64 197 || !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE) 198 # endif 199 ) 197 200 { 198 201 PGSTPT pPT; … … 276 279 * Get the PD entry. 277 280 */ 278 # if PGM_GST_TYPE == PGM_TYPE_32BIT281 # if PGM_GST_TYPE == PGM_TYPE_32BIT 279 282 PX86PDE pPde = &CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT]; 280 # elif PGM_GST_TYPE == PGM_TYPE_PAE283 # elif PGM_GST_TYPE == PGM_TYPE_PAE 281 284 /* pgmGstGetPaePDEPtr will return 0 if the PDPTE is marked as not present 282 285 * All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx) … … 286 289 if (!pPde) 287 290 return VERR_PAGE_TABLE_NOT_PRESENT; 288 # elif PGM_GST_TYPE == PGM_TYPE_AMD64291 # elif PGM_GST_TYPE == PGM_TYPE_AMD64 289 292 /** @todo Setting the r/w, u/s & nx bits might have no effect depending on the pdpte & pml4 values */ 290 293 PX86PDEPAE pPde = pgmGstGetLongModePDEPtr(&pVM->pgm.s, GCPtr); … … 292 295 if (!pPde) 293 296 return VERR_PAGE_TABLE_NOT_PRESENT; 294 # endif297 # endif 295 298 GSTPDE Pde = *pPde; 296 299 Assert(Pde.n.u1Present); … … 299 302 300 303 if ( !Pde.b.u1Size 301 || !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)) 304 # if PGM_GST_TYPE != PGM_TYPE_AMD64 305 || !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE) 306 # endif 307 ) 302 308 { 303 309 /* … … 728 734 if (Pde.n.u1Present) 729 735 { 730 if (!Pde.b.u1Size || !(pState->cr4 & X86_CR4_PSE)) 736 if ( !Pde.b.u1Size 737 # if PGM_GST_TYPE != PGM_TYPE_AMD64 738 || !(pState->cr4 & X86_CR4_PSE) 739 # endif 740 ) 731 741 { 732 742 /* -
trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp
r9341 r9606 988 988 * PAE or 32-bit? 989 989 */ 990 Assert(CPUMGetGuestMode(pVM) != CPUMMODE_LONG); 991 990 992 int rc; 991 993 if (!(fFlags & X86_CR4_PAE))
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