Index: /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac
===================================================================
--- /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac	(revision 96094)
+++ /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac	(revision 96095)
@@ -2147,4 +2147,24 @@
  %endif
 
+;
+; [V]PSADDBW
+;
+EMIT_INSTR_PLUS_ICEBP   psadbw,  MM1, MM2
+EMIT_INSTR_PLUS_ICEBP   psadbw,  MM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP   psadbw,  XMM1, XMM2
+EMIT_INSTR_PLUS_ICEBP   psadbw,  XMM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP   vpsadbw, XMM1, XMM2, XMM3
+EMIT_INSTR_PLUS_ICEBP   vpsadbw, XMM1, XMM2, FSxBX
+EMIT_INSTR_PLUS_ICEBP   vpsadbw, YMM1, YMM2, YMM3
+EMIT_INSTR_PLUS_ICEBP   vpsadbw, YMM1, YMM2, FSxBX
+ %if TMPL_BITS == 64
+EMIT_INSTR_PLUS_ICEBP   psadbw,  XMM8, XMM9
+EMIT_INSTR_PLUS_ICEBP   psadbw,  XMM8, FSxBX
+EMIT_INSTR_PLUS_ICEBP   vpsadbw, XMM8, XMM9, XMM10
+EMIT_INSTR_PLUS_ICEBP   vpsadbw, XMM8, XMM9, FSxBX
+EMIT_INSTR_PLUS_ICEBP   vpsadbw, YMM8, YMM9, YMM10
+EMIT_INSTR_PLUS_ICEBP   vpsadbw, YMM8, YMM9, FSxBX
+ %endif
+
 
 %endif ; BS3_INSTANTIATING_CMN
Index: /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32
===================================================================
--- /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32	(revision 96094)
+++ /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32	(revision 96095)
@@ -5963,4 +5963,83 @@
         {  bs3CpuInstr3_vpmulhrsw_YMM8_YMM9_YMM10_icebp_c64, 255,         RM_REG, T_AVX2_256,  8, 9,  10, RT_ELEMENTS(s_aValues),  s_aValues },
         {  bs3CpuInstr3_vpmulhrsw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256,  8, 9, 255, RT_ELEMENTS(s_aValues),  s_aValues },
+    };
+    static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
+    unsigned const                         iTest       = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
+    return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+                                        g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
+}
+
+
+/*
+ * [V]PSADBW  - Compute sum of absolute differences of packed unsigned byte integers.
+ */
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psadbw_MM1_MM2_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psadbw_MM1_FSxBX_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psadbw_XMM1_XMM2_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psadbw_XMM1_FSxBX_icebp);
+extern FNBS3FAR             bs3CpuInstr3_psadbw_XMM8_XMM9_icebp_c64;
+extern FNBS3FAR             bs3CpuInstr3_psadbw_XMM8_FSxBX_icebp_c64;
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsadbw_XMM1_XMM2_XMM3_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsadbw_XMM1_XMM2_FSxBX_icebp);
+extern FNBS3FAR             bs3CpuInstr3_vpsadbw_XMM8_XMM9_XMM10_icebp_c64;
+extern FNBS3FAR             bs3CpuInstr3_vpsadbw_XMM8_XMM9_FSxBX_icebp_c64;
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsadbw_YMM1_YMM2_YMM3_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsadbw_YMM1_YMM2_FSxBX_icebp);
+extern FNBS3FAR             bs3CpuInstr3_vpsadbw_YMM8_YMM9_YMM10_icebp_c64;
+extern FNBS3FAR             bs3CpuInstr3_vpsadbw_YMM8_YMM9_FSxBX_icebp_c64;
+
+BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_psadbw(uint8_t bMode)
+{
+    static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] =
+    {
+        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
+            /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
+            /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
+        {   /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
+            /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
+            /* => */ RTUINT256_INIT_C(0x0000000000000200, 0x0000000000000200, 0x0000000000000200, 0x0000000000000200) },
+        {   /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
+            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
+            /* => */ RTUINT256_INIT_C(0x00000000000002f6, 0x00000000000002e5, 0x0000000000000264, 0x0000000000000240) },
+    };
+
+    static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
+    {
+        {  bs3CpuInstr3_psadbw_MM1_MM2_icebp_c16,          255,         RM_REG, T_MMX_SSE,   1, 1,   2, RT_ELEMENTS(s_aValues),  s_aValues  },
+        {  bs3CpuInstr3_psadbw_MM1_FSxBX_icebp_c16,        255,         RM_MEM, T_MMX_SSE,   1, 1, 255, RT_ELEMENTS(s_aValues),  s_aValues  },
+        {  bs3CpuInstr3_psadbw_XMM1_XMM2_icebp_c16,        255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_psadbw_XMM1_FSxBX_icebp_c16,       255,         RM_MEM, T_SSE2,      1, 1, 255, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_vpsadbw_XMM1_XMM2_XMM3_icebp_c16,  255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_vpsadbw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_vpsadbw_YMM1_YMM2_YMM3_icebp_c16,  255,         RM_REG, T_AVX2_256,  1, 2,   3, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_vpsadbw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256,  1, 2, 255, RT_ELEMENTS(s_aValues),  s_aValues },
+    };
+    static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
+    {
+        {  bs3CpuInstr3_psadbw_MM1_MM2_icebp_c32,          255,         RM_REG, T_MMX_SSE,   1, 1,   2, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_psadbw_MM1_FSxBX_icebp_c32,        255,         RM_MEM, T_MMX_SSE,   1, 1, 255, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_psadbw_XMM1_XMM2_icebp_c32,        255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_psadbw_XMM1_FSxBX_icebp_c32,       255,         RM_MEM, T_SSE2,      1, 1, 255, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_vpsadbw_XMM1_XMM2_XMM3_icebp_c32,  255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_vpsadbw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_vpsadbw_YMM1_YMM2_YMM3_icebp_c32,  255,         RM_REG, T_AVX2_256,  1, 2,   3, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_vpsadbw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256,  1, 2, 255, RT_ELEMENTS(s_aValues),  s_aValues },
+    };
+    static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
+    {
+        {  bs3CpuInstr3_psadbw_MM1_MM2_icebp_c64,          255,         RM_REG, T_MMX_SSE,   1, 1,   2, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_psadbw_MM1_FSxBX_icebp_c64,        255,         RM_MEM, T_MMX_SSE,   1, 1, 255, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_psadbw_XMM1_XMM2_icebp_c64,        255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_psadbw_XMM1_FSxBX_icebp_c64,       255,         RM_MEM, T_SSE2,      1, 1, 255, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_psadbw_XMM8_XMM9_icebp_c64,        255,         RM_REG, T_SSE2,      8, 8,   9, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_psadbw_XMM8_FSxBX_icebp_c64,       255,         RM_MEM, T_SSE2,      8, 8, 255, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_vpsadbw_XMM1_XMM2_XMM3_icebp_c64,  255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_vpsadbw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_vpsadbw_XMM8_XMM9_XMM10_icebp_c64, 255,         RM_REG, T_AVX_128,   8, 9,  10, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_vpsadbw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,   8, 9, 255, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_vpsadbw_YMM1_YMM2_YMM3_icebp_c64,  255,         RM_REG, T_AVX2_256,  1, 2,   3, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_vpsadbw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256,  1, 2, 255, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_vpsadbw_YMM8_YMM9_YMM10_icebp_c64, 255,         RM_REG, T_AVX2_256,  8, 9,  10, RT_ELEMENTS(s_aValues),  s_aValues },
+        {  bs3CpuInstr3_vpsadbw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256,  8, 9, 255, RT_ELEMENTS(s_aValues),  s_aValues },
     };
     static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -8669,4 +8748,5 @@
 #if defined(ALL_TESTS)
         { "[v]pmulhrsw",                                    bs3CpuInstr3_v_pmulhrsw, 0 },
+        { "[v]psadbw",                                      bs3CpuInstr3_v_psadbw,   0 },
 #endif
     };
