Changeset 96286 in vbox

Timestamp:

Aug 18, 2022 8:11:28 AM (2 years ago)

Author:

vboxsync

Message:

VMM/IEM: Implement mulps/mulpd instructions, bugref:9898

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/IEMAllAImpl.asm (modified) (1 diff)
• VMMAll/IEMAllAImplC.cpp (modified) (14 diffs)
• VMMAll/IEMAllInstructionsTwoByte0f.cpp.h (modified) (1 diff)
• include/IEMInternal.h (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm

@@ -4587 +4587 @@
 IEMIMPL_FP_F2 addps
 IEMIMPL_FP_F2 addpd
+IEMIMPL_FP_F2 mulps
+IEMIMPL_FP_F2 mulpd

trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp

@@ -13881 +13881 @@
 
     /* If DAZ is set \#DE is never set. */
-    if (fMxcsr & X86_MXCSR_DAZ)
+    if (   fMxcsr & X86_MXCSR_DAZ
+        || (   (fXcpt & X86_MXCSR_DE) /* Softfloat sets DE for sub-normal values. */
+            && (RTFLOAT32U_IS_SUBNORMAL(pr32Result))))
         fXcpt &= ~X86_MXCSR_DE;
-    else /* Need to set \#DE when either the result or one of the source operands is a De-normal (softfloat doesn't do this always). */
-        fXcpt |=   (   RTFLOAT32U_IS_SUBNORMAL(pr32Result)
-                    || RTFLOAT32U_IS_SUBNORMAL(pr32Src1)
+    else /* Need to set \#DE when one of the source operands is a De-normal. */
+        fXcpt |=   (   RTFLOAT32U_IS_SUBNORMAL(pr32Src1)
                     || RTFLOAT32U_IS_SUBNORMAL(pr32Src2))
                  ? X86_MXCSR_DE
@@ -13924 +13925 @@
 
     /* If DAZ is set \#DE is never set. */
-    if (fMxcsr & X86_MXCSR_DAZ)
+    if (   fMxcsr & X86_MXCSR_DAZ
+        || (   (fXcpt & X86_MXCSR_DE) /* Softfloat sets DE for sub-normal values. */
+            && (RTFLOAT64U_IS_SUBNORMAL(pr64Result))))
         fXcpt &= ~X86_MXCSR_DE;
-    else /* Need to set \#DE when either the result or one of the source operands is a De-normal (softfloat doesn't do this always). */
-        fXcpt |=   (   RTFLOAT64U_IS_SUBNORMAL(pr64Result)
-                    || RTFLOAT64U_IS_SUBNORMAL(pr64Src1)
+    else /* Need to set \#DE when one of the source operands is a De-normal. */
+        fXcpt |=   (   RTFLOAT64U_IS_SUBNORMAL(pr64Src1)
                     || RTFLOAT64U_IS_SUBNORMAL(pr64Src2))
                  ? X86_MXCSR_DE
@@ -13989 +13991 @@
  * of the source operands contains a NaN value, setting the output accordingly.
  *
- * @returns Flag whether the operation can continue (true) or whether a NaN value was detected in one of the operands (false).
+ * @returns Flag whether the operation can continue (false) or whether a NaN value was detected in one of the operands (true).
  * @param   pr32Res         Where to store the result in case the operation can't continue.
  * @param   pr32Val1        The first input operand.
@@ -14005 +14007 @@
         pr32Res->s.uFraction |= RT_BIT_32(RTFLOAT32U_FRACTION_BITS - 1);
         *pfMxcsr |= (cSNan ? X86_MXCSR_IE : 0);
-        return false;
+        return true;
     }
     else if (cSNan)
@@ -14013 +14015 @@
         pr32Res->s.uFraction |= RT_BIT_32(RTFLOAT32U_FRACTION_BITS - 1);
         *pfMxcsr |= X86_MXCSR_IE;
-        return false;
+        return true;
     }
     else if (cQNan)
@@ -14019 +14021 @@
         /* The QNan operand is placed into the result. */
         *pr32Res = RTFLOAT32U_IS_QUIET_NAN(pr32Val1) ? *pr32Val1 : *pr32Val2;
-        return false;
+        return true;
     }
 
     Assert(!cQNan && !cSNan);
-    return true;
+    return false;
+}
+
+
+/**
+ * Checks all input values for valid inputs returning whether the operation can continue.
+ *
+ * @returns Flag whether the operation can continue (true) or whether a NaN value was detected in one of the operands (false).
+ * @param   pResult         Where to store the result in case the operation can't continue.
+ * @param   puSrc1          The first input operand.
+ * @param   puSrc2          The second input operand.
+ * @param   fMxcsr          The MXCSR flags.
+ */
+static bool iemSseCheckXmmInputBinaryR32(PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2, uint32_t fMxcsr)
+{
+    bool fNan = iemSseCheckInputBinaryR32(&pResult->uResult.ar32[0], &puSrc1->ar32[0], &puSrc2->ar32[0], &fMxcsr);
+    fNan     |= iemSseCheckInputBinaryR32(&pResult->uResult.ar32[1], &puSrc1->ar32[1], &puSrc2->ar32[1], &fMxcsr);
+    fNan     |= iemSseCheckInputBinaryR32(&pResult->uResult.ar32[2], &puSrc1->ar32[3], &puSrc2->ar32[2], &fMxcsr);
+    fNan     |= iemSseCheckInputBinaryR32(&pResult->uResult.ar32[3], &puSrc1->ar32[2], &puSrc2->ar32[3], &fMxcsr);
+    if (fNan)
+        pResult->MXCSR = fMxcsr;
+
+    return !fNan;
 }
 
@@ -14031 +14055 @@
  * of the source operands contains a NaN value, setting the output accordingly.
  *
- * @returns Flag whether the operation can continue (true) or whether a NaN value was detected in one of the operands (false).
+ * @returns Flag whether the operation can continue (false) or whether a NaN value was detected in one of the operands (true).
  * @param   pr64Res         Where to store the result in case the operation can't continue.
  * @param   pr64Val1        The first input operand.
@@ -14047 +14071 @@
         pr64Res->s64.uFraction |= RT_BIT_64(RTFLOAT64U_FRACTION_BITS - 1);
         *pfMxcsr |= (cSNan ? X86_MXCSR_IE : 0);
-        return false;
+        return true;
     }
     else if (cSNan)
@@ -14055 +14079 @@
         pr64Res->s64.uFraction |= RT_BIT_64(RTFLOAT64U_FRACTION_BITS - 1);
         *pfMxcsr |= X86_MXCSR_IE;
-        return false;
+        return true;
     }
     else if (cQNan)
@@ -14061 +14085 @@
         /* The QNan operand is placed into the result. */
         *pr64Res = RTFLOAT64U_IS_QUIET_NAN(pr64Val1) ? *pr64Val1 : *pr64Val2;
-        return false;
+        return true;
     }
 
     Assert(!cQNan && !cSNan);
-    return true;
-}
+    return false;
+}
+
+
+/**
+ * Checks all input values for valid inputs returning whether the operation can continue.
+ *
+ * @returns Flag whether the operation can continue (true) or whether a NaN value was detected in one of the operands (false).
+ * @param   pResult         Where to store the result in case the operation can't continue.
+ * @param   puSrc1          The first input operand.
+ * @param   puSrc2          The second input operand.
+ * @param   fMxcsr          The MXCSR flags.
+ */
+static bool iemSseCheckXmmInputBinaryR64(PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2, uint32_t fMxcsr)
+{
+    bool fNan = iemSseCheckInputBinaryR64(&pResult->uResult.ar64[0], &puSrc1->ar64[0], &puSrc2->ar64[0], &fMxcsr);
+    fNan     |= iemSseCheckInputBinaryR64(&pResult->uResult.ar64[1], &puSrc1->ar64[1], &puSrc2->ar64[1], &fMxcsr);
+    if (fNan)
+        pResult->MXCSR = fMxcsr;
+
+    return !fNan;
+}
+
 #endif
 
@@ -14076 +14121 @@
 static uint32_t iemAImpl_addps_u128_worker(PRTFLOAT32U pr32Res, uint32_t fMxcsr, PCRTFLOAT32U pr32Val1, PCRTFLOAT32U pr32Val2)
 {
-    if (!iemSseCheckInputBinaryR32(pr32Res, pr32Val1, pr32Val2, &fMxcsr))
-        return fMxcsr;
-
     RTFLOAT32U r32Src1, r32Src2;
     iemSsePrepareValueR32(&r32Src1, fMxcsr, pr32Val1);
@@ -14090 +14132 @@
 IEM_DECL_IMPL_DEF(void, iemAImpl_addps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
 {
-    pResult->MXCSR |= iemAImpl_addps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], &puSrc2->ar32[0]);
-    pResult->MXCSR |= iemAImpl_addps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc1->ar32[1], &puSrc2->ar32[1]);
-    pResult->MXCSR |= iemAImpl_addps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc1->ar32[2], &puSrc2->ar32[2]);
-    pResult->MXCSR |= iemAImpl_addps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc1->ar32[3], &puSrc2->ar32[3]);
+    if (iemSseCheckXmmInputBinaryR32(pResult, puSrc1, puSrc2, pFpuState->MXCSR))
+    {
+        pResult->MXCSR |= iemAImpl_addps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], &puSrc2->ar32[0]);
+        pResult->MXCSR |= iemAImpl_addps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc1->ar32[1], &puSrc2->ar32[1]);
+        pResult->MXCSR |= iemAImpl_addps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc1->ar32[2], &puSrc2->ar32[2]);
+        pResult->MXCSR |= iemAImpl_addps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc1->ar32[3], &puSrc2->ar32[3]);
+    }
 }
 #endif
@@ -14104 +14149 @@
 static uint32_t iemAImpl_addpd_u128_worker(PRTFLOAT64U pr64Res, uint32_t fMxcsr, PCRTFLOAT64U pr64Val1, PCRTFLOAT64U pr64Val2)
 {
-    if (!iemSseCheckInputBinaryR64(pr64Res, pr64Val1, pr64Val2, &fMxcsr))
-        return fMxcsr;
-
     RTFLOAT64U r64Src1, r64Src2;
     iemSsePrepareValueR64(&r64Src1, fMxcsr, pr64Val1);
@@ -14118 +14160 @@
 IEM_DECL_IMPL_DEF(void, iemAImpl_addpd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
 {
-    pResult->MXCSR |= iemAImpl_addpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], &puSrc2->ar64[0]);
-    pResult->MXCSR |= iemAImpl_addpd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc1->ar64[1], &puSrc2->ar64[1]);
+    if (iemSseCheckXmmInputBinaryR64(pResult, puSrc1, puSrc2, pFpuState->MXCSR))
+    {
+        pResult->MXCSR |= iemAImpl_addpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], &puSrc2->ar64[0]);
+        pResult->MXCSR |= iemAImpl_addpd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc1->ar64[1], &puSrc2->ar64[1]);
+    }
 }
 #endif
+
+
+/**
+ * MULPS
+ */
+#ifdef IEM_WITHOUT_ASSEMBLY
+static uint32_t iemAImpl_mulps_u128_worker(PRTFLOAT32U pr32Res, uint32_t fMxcsr, PCRTFLOAT32U pr32Val1, PCRTFLOAT32U pr32Val2)
+{
+    RTFLOAT32U r32Src1, r32Src2;
+    iemSsePrepareValueR32(&r32Src1, fMxcsr, pr32Val1);
+    iemSsePrepareValueR32(&r32Src2, fMxcsr, pr32Val2);
+    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(fMxcsr);
+    float32_t r32Result = f32_mul(iemFpSoftF32FromIprt(&r32Src1), iemFpSoftF32FromIprt(&r32Src2), &SoftState);
+    return iemSseSoftStateAndR32ToMxcsrAndIprtResult(&SoftState, r32Result, pr32Res, fMxcsr, &r32Src1, &r32Src2);
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_mulps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+{
+    if (iemSseCheckXmmInputBinaryR32(pResult, puSrc1, puSrc2, pFpuState->MXCSR))
+    {
+        pResult->MXCSR |= iemAImpl_mulps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], &puSrc2->ar32[0]);
+        pResult->MXCSR |= iemAImpl_mulps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc1->ar32[1], &puSrc2->ar32[1]);
+        pResult->MXCSR |= iemAImpl_mulps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc1->ar32[2], &puSrc2->ar32[2]);
+        pResult->MXCSR |= iemAImpl_mulps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc1->ar32[3], &puSrc2->ar32[3]);
+    }
+}
+#endif
+
+
+/**
+ * MULPD
+ */
+#ifdef IEM_WITHOUT_ASSEMBLY
+static uint32_t iemAImpl_mulpd_u128_worker(PRTFLOAT64U pr64Res, uint32_t fMxcsr, PCRTFLOAT64U pr64Val1, PCRTFLOAT64U pr64Val2)
+{
+    RTFLOAT64U r64Src1, r64Src2;
+    iemSsePrepareValueR64(&r64Src1, fMxcsr, pr64Val1);
+    iemSsePrepareValueR64(&r64Src2, fMxcsr, pr64Val2);
+    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(fMxcsr);
+    float64_t r64Result = f64_mul(iemFpSoftF64FromIprt(&r64Src1), iemFpSoftF64FromIprt(&r64Src2), &SoftState);
+    return iemSseSoftStateAndR64ToMxcsrAndIprtResult(&SoftState, r64Result, pr64Res, fMxcsr, &r64Src1, &r64Src2);
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_mulpd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+{
+    if (iemSseCheckXmmInputBinaryR64(pResult, puSrc1, puSrc2, pFpuState->MXCSR))
+    {
+        pResult->MXCSR |= iemAImpl_mulpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], &puSrc2->ar64[0]);
+        pResult->MXCSR |= iemAImpl_mulpd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc1->ar64[1], &puSrc2->ar64[1]);
+    }
+}
+#endif

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h

@@ -3879 +3879 @@
 FNIEMOP_STUB(iemOp_addsd_Vsd_Wsd);
 
+
 /** Opcode      0x0f 0x59 - mulps Vps, Wps */
-FNIEMOP_STUB(iemOp_mulps_Vps_Wps);
+FNIEMOP_DEF(iemOp_mulps_Vps_Wps)
+{
+    IEMOP_MNEMONIC2(RM, MULPS, mulps, Vps, Wps, DISOPTYPE_HARMLESS, 0);
+    return FNIEMOP_CALL_1(iemOpCommonSseFp_FullFull_To_Full, iemAImpl_mulps_u128);
+}
+
+
 /** Opcode 0x66 0x0f 0x59 - mulpd Vpd, Wpd */
-FNIEMOP_STUB(iemOp_mulpd_Vpd_Wpd);
+FNIEMOP_DEF(iemOp_mulpd_Vpd_Wpd)
+{
+    IEMOP_MNEMONIC2(RM, MULPD, mulpd, Vpd, Wpd, DISOPTYPE_HARMLESS, 0);
+    return FNIEMOP_CALL_1(iemOpCommonSseFp_FullFull_To_Full, iemAImpl_mulpd_u128);
+}
+
+
 /** Opcode 0xf3 0x0f 0x59 - mulss Vss, Wss */
 FNIEMOP_STUB(iemOp_mulss_Vss_Wss);

trunk/src/VBox/VMM/include/IEMInternal.h

@@ -2418 +2418 @@
 FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
 FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
+FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
+FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
 
 FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
 FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
+FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
+FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
 
 FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
 FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
+FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
+FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
 /** @} */